PS11037

MITSUBISHI SEMICONDUCTOR MITSUBISHI SEMICONDUCTOR ARY IMIN PREL . ation nge. pecific ct to cha bje final s not a its are su is is ic lim e: Th tr Notice parame Som PS11037 PS11037 FLAT-BASE TYPE FLAT-BASE TYPE INSULATED TYPE INSULATED TYPE PS11037 INTEGRATED FUNCTIONS AND FEATURES • 3 phase IGBT inverter bridge configured by the latest 3rd. generation IGBT and diode technology. • Inverter output current capability IO (Note 1): Type Name Motor Rating IO (100%) IO (150%; 60sec) 25.5Arms PS11037 3.7 kW/200V AC 17.0Arms (Note 1) : The inverter output current is assumed to be sinusoidal and the peak current value of each of the  above loading cases is defined as : IOP = IO × √ 2, TC < 100°C INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS: • P-Side IGBTs : Drive circuit, high-level-shift circuit, bootstrap circuit supply scheme for Single Control-Power-Source drive, and under voltage (UV) protection. • N-Side IGBTs : Drive circuit, DC-Link current sense and amplifier circuits for overcurrent protection, control-supply under-voltage protection (UV), and fault output (FO) signaling circuit. • Fault Output : N-side IGBT short circuit (SC), over-current (OC), and control supply under-voltage (UV). • Inverter Analog Current Sense : N-Side IGBT DC-Link Current Sense. • Input Interface : 5V CMOS/TTL compatible, Schmitt Trigger input, and Arm-Shoot-Through interlock protective function. APPLICATION Acoustic noise-less 3.7kW/200V AC Class 3 phase inverters, motor control applications, and motors with built-in small size inverter package PACKAGE OUTLINES 95 ± 1 85 ± 0.3 24.5 2 42 6 18 (18.5) 4-φ4.6 (MOUNTING HOLE) 20.4 ± 1 Terminals Assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CBU+ CBU– CBV+ CBV– CBW+ CBW– VD UP VP WP UN VN WN FO Vamp GND 21 22 23 24 25 P U V W N 15 9 0.5 (31.65) 2.5 71 62.35 ± 0.8 59 ± 0.3 74 ± 1 1 15 21 22 23 24 25 9 12.7 ± 0.3 50.8 ± 0.8 3 3 ± 0.5 17 ± 0.8 3.5 MITSUBISHI ELECTRIC JAPAN Type name Lot.No (Fig. 1) 8 ± 0.5 3 23.5 V2 (82.1) 30.7 ± 0.5 (4-φ5) (35) 4 23.5 3 12 34 56 7 16 0.5 Jan. 2000 MITSUBISHI SEMICONDUCTOR . ation nge. pecific ct to cha bje final s not a its are su is is ic lim e: Th tr Notice parame Som PR INA ELIM RY PS11037 FLAT-BASE TYPE INSULATED TYPE INTERNAL FUNCTIONS BLOCK DIAGRAM UV Protection VD Input signal conditioning (Interlock circuit) Level shifter Drive circuit P UP VP WP UN VN WN FO V(amp) U V UV Protection Drive circuit W Fo Circuit OC/SC Protection +– GND N (Fig. 2) MAXIMUM RATINGS (Tj = 25°C) INVERTER PART Symbol VCC Item Supply voltage Condition Applied between P-N Applied between P-N, Surge-value Applied between P-U.V.W, U.V.W-N Applied between P-U.V.W, U.V.W-N (Pulse) TC = 25°C, “( )” means IC peak value Ratings 450 500 600 600 ±50 (±100) Unit V V V V A VCC(surge) Supply voltage (surge) VP or VN Each IGBT collector-emitter static voltage VP(S) or VN(S) ±Ic(±Icp) Each IGBT collector-emitter switching voltage Each IGBT collector current CONTROL PART Symbol VD, VDB VCIN VFO IFO Iamp Supply voltage Input signal voltage Fault output supply voltage Fault output current DC-Link IGBT current signal Amp output current Item Ratings –0.5 ~ 20 –0.5 ~ +7.5 –0.5 ~ +7.5 15 1 Unit V V V mA mA Jan. 2000 MITSUBISHI SEMICONDUCTOR . ation nge. pecific ct to cha bje final s not a its are su is is ic lim e: Th tr Notice parame Som P MIN RELI ARY PS11037 FLAT-BASE TYPE INSULATED TYPE TOTAL SYSTEM Symbol Tj Tstg TC VISO — Item Junction temperature Storage temperature Module case operating temperature Isolation voltage Mounting torque Condition (Note 2) — (Fig. 3) 60 Hz sinusoidal AC applied between all terminals and the base plate for 1 minute. Mounting screw: M4 Ratings –20 ~ +125 –40 ~ +125 –20 ~ +100 2500 0.98 ~ 1.47 Unit °C °C °C Vrms N·m (Note 2) : The indicated values are specified considering the safe operation of all the parts within the ASIPM. The max. ratings for the ASIPM power chips (IGBT & FWDi) is Tj < 150. CASE TEMPERATURE MEASUREMENT POINT LABEL Tc (Fig. 3) THERMAL RESISTANCE Symbol Rth(jc) Q Rth(jc) F Rth(cf) Item Junction to case Thermal Resistance Contact Thermal Resistance Inverter IGBT (1/6) Inverter FWDi (1/6) Case to fin thermal, grease applied (1 Module) Condition Ratings Min. — — — Typ. — — — Max. 1.75 2.4 0.031 Unit °C/W °C/W °C/W ELECTRICAL CHARACTERISTICS (Tj = 25°C, VD = 15V, V DB = 15V unless otherwise noted) Symbol VCE(sat) VEC ton tc(on) toff tc(off) trr Item Collector-emitter saturation voltage FWDi forward voltage Condition Tj = 25°C, Input = ON, Ic = 50A, VD = VDB = 15V (Shunt voltage drop not included) Tj = 25°C, –IC = 50A 1/2 Bridge inductive, Input = 5V ↔ 0V VCC = 300V, IC = 50A, Tj = 125°C VD = 15V, VDB = 15V Note: ton, toff include delay time of the internal control circuit. Min. — — 0.3 — — — — Ratings Typ. — — 0.6 0.5 1.6 0.5 0.12 Max. 2.9 2.9 1.5 1.0 2.5 1.2 — Unit V V µs µs µs µs µs Switching times FWDi reverse recovery time Short circuit endurance @VCC ≤ 400V, Input = 5V → 0V (One-Shot) (Output, Arm, and Load, Short Circuit Modes) –20°C ≤ Tj (start) ≤ 125°C, 13.5V ≤ VD = VDB ≤ 16.5V Switching SOA @VCC ≤ 400V, Input = 5V ↔ 0V, Tj ≤ 125°C IC < OC trip level, 13.5V ≤ VD = VDB ≤ 16.5V • No destruction • FO output by protection operation • No destruction • No protecting operation • No FO output Jan. 2000 MITSUBISHI SEMICONDUCTOR . ation nge. pecific ct to cha bje final s not a its are su is is ic lim e: Th tr Notice parame Som PR INA ELIM RY PS11037 FLAT-BASE TYPE INSULATED TYPE ELECTRICAL CHARACTERISTICS (Tj = 25°C, VD = 15V, V DB = 15V unless otherwise noted) Symbol ID IDB Vth(on) Vth(off) Ri fPWM tdead tint Vamp(100%) Vamp(200%) Vamp(250%) Vamp(0) OC tOC SC tSC UVD UVDr UVDB UVDBr tdV tFO IFo(H) IFo(L) Item Circuit current (Average) Circuit current (Average) Input on threshold voltage Input off threshold voltage Input pull-up resistor PWM input frequency Arm shoot-through blocking time Input interlock sensing Inverter DC-Link IGBT current sense voltage output signal Inverter DC-Link IGBT current sense voltage output limit Over current trip level Over current delay time Short circuit trip level Short circuit delay time Trip level Reset level Supply circuit under Trip level voltage protection Reset level Delay time Fault output pulse width Fault output current Condition Tj = 25°C, VD = 15V, Vin = 5V Tj = 25°C, VD = VDB = 15V, Vin = 5V Min. — — 0.8 2.5 — — 2.2 — 1.5 3.0 5.0 — 86.7 — — — 11.0 11.5 10.1 10.6 — 1.0 — — Ratings Typ. — — 1.4 3.0 50 10 — 100 2.0 4.0 — 50 102 10 181 2 12.0 12.5 10.8 11.3 10 1.8 — — Max. 50 5 2.0 4.0 — 15 — — 2.5 5.0 — 100 117 — — — 12.75 13.25 11.6 12.1 — — 1 15 Unit mA mA V V kΩ kHz µs ns V V V mV A µs A µs V V V V µs ms µA mA Applied between input terminal-inside power supply T C ≤ 100°C, Tj ≤ 125°C Relates to corresponding inputs (Note 3) T C = –20°C ~ +100°C Relates to corresponding input (Fig. 6) IC = IOP(100%) VD = 15V Tj = 25°C (Fig. 4) IC = IOP(200%) VD = 15V IC = IOP(250%) (Fig. 4) IC = 0A Tj = 25°C (Fig. 5) Tj = 25°C (Fig. 5) Tj = 25°C (Fig. 5) Tj = 25°C (Fig. 5) –20°C~100°C T C = Tj = 25°C Tj = 25°C Open collector output (Note 4) (Note 4) (Note 3) : The dead-time has to be set externally by the CPU; it is not part of the ASIPM internal functions. (Note 4) : Fault output signaling is given only when the internal OC, SC, & UV protection circuits are activated. The OC, SC and UV protection (and fault output) operate for the lower arms only. The OC and SC protection Fault output is given in a pulse format while that of UV protection is maintained throughout the duration of the under-voltage condition. RECOMMENDED OPERATING CONDITIONS Symbol VCC VD VDB ∆VD, VDB VCIN(ON) VCIN(OFF) tdead TC fPWM tXX Item Supply voltage Supply voltage Supply voltage Supply voltage ripple Input on voltage Input off voltage Arm shoot-through blocking time Module case operating temperature PWM Input frequency Allowabel input on-pulse width Condition Applied across P-N terminals Applied between VD-GND Applied between CBU+ & CBU–, CBV+ & CBV–, CBW+ & CBW– Applied between UP • VP • WP • UN • VN • WN and GND Relates to corresponding inputs TC ≤ 100°C, Tj ≤ 125°C Ratings Min. — 13.5 13.5 –1 0 4.0 2.2 — — 1 Vamp Typ. 300 15.0 15.0 — — — — — — — Max. 400 16.5 16.5 +1 0.8 5.0 — 100 15 — Unit V V V V/ µs V V µs °C kHz µs 5 INVERTER DC-LINK IGBT CURRENT ANALOGUE SIGNALING OUTPUT (TYPICAL) 4 VD = 15V Tj = 25°C Vamp (200%) Vamp (V) 3 2 Vamp (100%) 1 0 0 (Fig. 4) 200 300 100 DC-LINK IGBT Current (%), (IC = IO! 2) Jan. 2000 MITSUBISHI SEMICONDUCTOR . ation nge. pecific ct to cha bje final s not a its are su is is ic lim e: Th tr Notice parame Som P MIN RELI ARY PS11037 FLAT-BASE TYPE INSULATED TYPE CURRENT ABNORMALITY PROTECTIVE FUNCTIONS Ic(A) Short circuit trip level SC Over current trip level Protection is achieved by monitoring and filtering the N-side DC-Bus current. When a current trip-level is exceeded, all the Nside IGBTs are intercepted (turned OFF) and a fault-signal is output. After the fault-signal output duration (1.8msec (typ.)@ 25°C), the interception is Reset at the following OFF input signal level (more than 4.0V). OC Collector current 0 2 10 tw (µs) (Fig. 5) ARM-SHOOT-THROUGH INTER-LOCK PROTECTIVE FUNCTION P-Side Input Signal : VCIN(p) ON N-Side Input Signal : VCIN(n) ON a3 P-Side IGBT Gate : VGE(p) 0 a2 b3 0 a1 a4 b1 b4 b2 N-Side IGBT Gate : VGE(n) (Fig. 6) Description: (1) During the ON-State of either of the upper-arm or the lower-arm IGBT, the inter-lock protection circuit blocks any erroneous ON pulses (resulting from input noise) from triggering the other arm IGBT and thus it prevents the arm-shoot-through situation. (2) When two ON-signals are received for both the upper and the lower arms, the signal received first will be passed to the IGBT and the second signal will be blocked. The second signal will be passed to its corresponding IGBT immediately after the first signal is OFF. Note: This protective function provides no fault signaling output. Operation: a1. P-side normal ON-signal ⇒ P-side IGBT gate turns ON. a2. N-side erroneous ON-signal ⇒ N-side IGBT gate remains OFF. a3. While P-side ON-signal remains ⇒ P-side IGBT gate remains ON. a4. N-side normal ON-signal ⇒ N-side IGBT gate turns ON. N-side normal ON-signal ⇒ N-side IGBT gate turns ON. Simultaneous ON-signals ⇒ P-side IGBT gate remains OFF. N-side receives OFF-signal ⇒ N-side IGBT gate turns OFF. Immediately after (b3) ⇒ P-side IGBT gate turns ON. b1. b2. b3. b4. RECOMMENDED I/O INTERFACE CIRCUIT 5V 5V 5.1kΩ VD(15V) R ASIPM Note : The parts shown dotted are to be used if noise filtering is required. UP,VP,WP,UN,VN,WN Fo V(amp) CPU R 10kΩ 0.1nF (Fig. 7) 0.1nF GND(Logic) Jan. 2000