PS21205

MITSUBISHI SEMICONDUCTOR MITSUBISHI SEMICONDUCTOR PS21205 PS21205 TRANSFER-MOLD TYPE TRANSFER-MOLD TYPE INSULATED TYPE INSULATED TYPE PS21205 INTEGRATED POWER FUNCTIONS 600V/20A low-loss 3rd generation IGBT inverter bridge for 3 phase DC-to-AC power conversion (Fig. 2) Application Motor Ratings : Power : 1.5kW, sinusoidal, PWM Frequency=5kHz 100% load current : 8.0A (rms)* 150% load current : 12.0A (rms)*, 1 minute. *(Note) : The motor current is assumed to be sinusoidal and the peak current value is defined as : lO ! √ 2 INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS • For upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting, Control circuit under-voltage (UV) protection. Note : Bootstrap supply scheme can be applied (Fig. 2). • For lower-leg IGBTS : Drive circuit, Control curcuit under-voltage protection (UV), Short circuit protection (SC). (Fig. 3) • Fault signaling : Corresponding to a SC fault (Low-side IGBT) or a UV fault (Low-side supply). • Input interface : 5V line CMOS/TTL compatible, Schmitt Trigger receiver circuit. APPLICATION AC100V~200V three-phase inverter drive for small power (1.5 kW) motor control. Fig. 1 PACKAGE OUTLINES 2.8 12 34 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 11.5 31 2-φ4.5 22 23 24 25 26 10 10 10 67 79 20 13.4 21.4 3.8 TERMINALS CODE 1. UP 4. VUFS 2. VP1 5. VP 3. VUFB 6. VP1 7. VVFB 8. VVFS 9. WP 10. VP1 13. VWFS 16. CIN 19. UN 11. VPC 14. VN1 17. CFO 20. VN 12. VWFB 15. VNC 18. Fo 21. WN 8 12.8 22. P 23. U 24. V 25. W 26. N Aug. 1999 MITSUBISHI SEMICONDUCTOR PS21205 TRANSFER-MOLD TYPE INSULATED TYPE Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE) CBW+ CBW– CBV+ CBV– CBU– CBU+ C3 : Tight tolerance, temp-compensated electrolytic type (Note : The capacitance value depends on the PWM control scheme used in the applied system). C4 : 0.22~2µF R-category ceramic capacitor for noise filtering. High-side input (PWM) (5V line) Note 1,2) Input signal Input signal Input signal coditioning coditioning coditioning Level shifter Level shifter Level shifter Protection circuit (UV) Bootstrap circuit For detailed description of the boot-strap circuit construction, please contact Mitsubishi Electric C4 C3 Protection circuit (UV) Protection circuit (UV) (Note 6) DIP-IPM Inrush current limiter circuit Drive circuit Drive circuit Drive circuit P AC line input H-side IGBTS (Note 4) U V W M AC line output C Z Fig. 3 N1 VNC N CIN Drive circuit L-side IGBTS Z : ZNR (Surge absorber) C : AC filter (Ceramic capacitor 2.2~6.5nF) (Note : Additionally, an appropriate line-to line surge absorber circuit may become necessary depending on the application environment). Input signal conditioning Fo logic Protection circuit Control supply Under-Voltage protection FO CFO Low-side input (PWM) (5V line) (Note 1, 2) Fault output (5V line) (Note 3, 5) Note1: 2: 3: 4: 5: 6: To prevent the input signals oscillation, an RC coupling at each input is recommended. (see also Fig. 7) By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. (see also Fig. 7) This output is open collector type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 5.1kΩ resistance. (see also Fig. 7) The wiring between the power DC link capacitor and the P/N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P and N1 DC power input pins. Fo output pulse width should be decided by putting external capacitor between CFO and VNC terminals. (Example : CFO=22nF tFO=1.8ms (Typ.)) High voltage diodes (600V or more) should be used in the bootstrap circuit. VNC VD (15V line) Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT DIP-IPM Drive circuit P Short Circuit Protective Function (SC) : SC protection is achieved by sensing the L-side DC-Bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the RC circuit). When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is recommended to stop the system when the Fo signal is received and check the fault. IC (A) SC Protection Trip Level H-side IGBTS U V W L-side IGBTS External protection circuit N1 Shunt Resistor A N VNC CIN B Drive circuit Collector current waveform CR C Protection circuit 0 2 tw (µs) Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs. 2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible. Aug. 1999 MITSUBISHI SEMICONDUCTOR PS21205 TRANSFER-MOLD TYPE INSULATED TYPE MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol VCC VCC(surge) VCES ±IC ±ICP PC Tj Parameter Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature Condition Applied between P-N Applied between P-N TC = 25°C TC = 25°C, instantaneous value (pulse) TC = 25°C, per 1 chip (Note 1) Ratings 450 500 600 20 40 56 –20~+150 Unit V V V A A W °C Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ TC ≤ 100°C) however, to insure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ TC ≤ 100°C). CONTROL (PROTECTION) PART Symbol VD VDB VCIN VFO IFO VSC Parameter Control supply voltage Control supply voltage Input voltage Fault output supply voltage Fault output current Current sensing input voltage Condition Applied between V P1-VPC, VN1-VNC Applied between VUFB-VUFS, VVFB -VVFS , VWFB-VWFS Applied between UP, VP, WP-VPC, UN, VN, W N-VNC Applied between F O-VNC Sink current at FO terminal Applied between CIN-V NC Ratings 20 20 –0.5~+5.5 –0.5~VD+0.5 15 –0.5~VD+0.5 Unit V V V V mA V TOTAL SYSTEM Symbol Parameter VCC(PROT) Self protection supply voltage limit (short circuit protection capability) Module case operation temperature TC Tstg Viso Storage temperature Isolation voltage 60Hz, Sinusoidal, AC 1 minute, connection pins to heat-sink plate Condition VD = VDB = 13.5~16.5V, Inverter part Tj = 125°C, non-repetitive, less than 2 µs (Note 2) Ratings 400 –20~+100 –40~+125 1500 Unit V °C °C Vrms Note 2 : TC MEASUREMENT POINT Control pins DIP-IPM Heat sink boundary Tc Power pins Aug. 1999 MITSUBISHI SEMICONDUCTOR PS21205 TRANSFER-MOLD TYPE INSULATED TYPE THERMAL RESISTANCE Symbol Rth(j-c)Q Rth(j-c)F Rth(c-f) Parameter Junction to case thermal resistance Contact thermal resistance Condition Inverter IGBT part (per 1/6 module) Inverter FWDi part (per 1/6 module) Case to fin, (per 1 module) thermal grease applied Limits Min. — — — Typ. — — — Max. 2.2 4.5 0.067 Unit °C/W ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol VCE(sat) VEC ton trr tc(on) toff tc(off) ICES Parameter Collector-emitter saturation voltage FWDi forward voltage Condition IC = 20A, Tj = 25°C VD = VDB = 15V VCIN = 0V IC = 20A, Tj = 125°C Tj = 25°C, –IC = 20A, VCIN = 5V VCC = 300V, VD = VDB = 15V IC = 20A, T j = 125°C, VCIN = 5V → 0V Switching times Inductive load (upper-lower arm) Note: t on, t off include delay time of the internal control circuit Tj = 25°C VCE = VCES Tj = 125°C Min. — — — — — — — — — — Limits Typ. 1.8 2.0 2.2 0.8 0.1 0.5 2.0 1.0 — — Max. — — — — — — — — 1.0 10 Unit V V µs Collector-emitter cut-off current mA CONTROL (PROTECTION) PART Symbol VD VDB ID Parameter Control supply voltage Control supply voltage Condition Applied between VP1-VPC, VN1-VNC Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS VP1-VPC, VN1-VNC VD = VDB= 15V, VUFB-VUFS, VVFB -VVFS , VWFB-VWFS input = OFF VD = VDB= 15V, VP1-VPC, VN1-VNC input = ON VUFB-VUFS, VVFB -VVFS , VWFB-VWFS VSC = 0V, FO circuit : 10kΩ to 5V pull-up VSC = 1V, FO circuit : 10kΩ to 5V pull-up VSC = 1V, IFO = 15mA TC ≤ 100°C, Tj ≤ 125°C Relates to corresponding input signal for blocking arm shoot-through. –20°C ≤ TC ≤ 100°C (Note 2) Tj = 25°C, VD = 15°C Tj ≤ 125°C Trip level Reset level Trip level Reset level Min. 13.5 13.5 — — — — 4.9 — 0.8 — 3.0 0.45 10.0 10.5 10.3 10.8 1.0 0.8 2.5 0.8 2.5 Limits Typ. 15.0 15.0 4.25 0.50 4.95 0.50 — 1.0 1.2 5.0 — 0.5 — — — — 1.8 1.4 3.0 1.4 3.0 Max. 16.5 16.5 8.50 1.00 9.70 1.00 — 2.0 1.8 — — 0.55 12.0 12.5 12.5 13.0 — 2.0 4.0 2.0 4.0 Unit V V mA mA mA mA V V V kHz µs V V V V V ms V V Circuit current VFOH VFOL VFOsat fPWM tdead VSC(ref) UVDBt UVDBr UVDt UVDr tFO Vth(on) Vth(off) Vth(on) Vth(off) Fault output voltage PWM input frequency Allowable deadtime Short circuit trip level Supply circuit under-voltage protection Fault output pulse width (Note 3) ON threshold voltage OFF threshold voltage ON threshold voltage OFF threshold voltage CFO = 22nF (connected between CFO–VNC) Applied between: H-side UP, VP, WP-VPC Applied between: L-side UN, VN, WN-VNC Note 2 : Short circuit protection is functioning only at the low-arms. Please select the value of the external shunt resistor such that the SC triplevel is less than 34.0 A. 3 : Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulsewidth tFO depends on the capacitance value of CFO according to the following approximate equation : CFO = 12.2 ! 10-6 ! tFO [F]. Aug. 1999 MITSUBISHI SEMICONDUCTOR PS21205 TRANSFER-MOLD TYPE INSULATED TYPE MECHANICAL CHARACTERISTICS AND RATINGS Parameter Mounting torque Weight Mounting screw : M4 Condition Recommended 12kg·cm Recommended 1.18N·m Min. 10 0.98 — Limits Typ. — — 54 Max. 15 1.47 — Unit kg·cm N·m g RECOMMENDED OPERATION CONDITIONS Symbol VCC VD VDB ∆VD, ∆VDB tdead fPWM VCIN(ON) VCIN(OFF) Parameter Supply voltage Control supply voltage Control supply voltage Control supply variation Arm shoot-through blocking time PWM input frequency Input ON threshold voltage Input OFF threshold voltage Condition Applied between P-N Applied between VP1-VPC, VN1-VNC Applied between VUFB-VUFS, VVFB -VVFS, VWFB-VWFS For each input signal TC ≤ 100°C, Tj ≤ 125°C Applied between UP, VP, WP-VPC Applied between UN, VN, W N-VNC Min. 0 13.5 13.5 –1 3 — Limits Typ. 300 15.0 15.0 — — 5 0~0.65 4.0~5.5 Max. 400 16.5 16.5 1.0 — — Unit V V V V/ µs µs kHz V V Fig. 4 THE DIP-IPM INTERNAL CIRCUIT VWFS VWFB VUFS HVIC 1 P VVFB WN Fo WN VN UN GND VCC Fo VCC VCC COM COM COM HVIC 3 HO HO HVIC 2 LVIC HO VS VB VS VB VS WOUT CIN CFO UOUT VOUT CFO CIN VNO VB VCC IN IN IN N W V U Aug. 1999 DIP-IPM VUFB VVFS VNC VPC VN1 VP1 VP1 VP1 WP UN UP VN VP MITSUBISHI SEMICONDUCTOR PS21205 TRANSFER-MOLD TYPE INSULATED TYPE Fig. 5 TIMING CHARTS OF THE DIP-IPM PROTECTIVE FUNCTIONS [A] Short-Circuit Protection (Lower-arms only) (For the external shunt resistance and CR connection, please refer to Fig. 3.) a1. Normal operation : IGBT ON and carrying current. a2. Short circuit current detection (SC trigger). a3. Hard IGBT gate interrupt. a4. IGBT turns OFF. a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor CFO. a6. Input “H” : IGBT OFF state. a7. Input “L” : IGBT ON state, but during the FO active signal the IGBT doesn’t turn ON. a8. IGBT OFF state. Lower-arms control input Protection circuit state a6 a7 SET RESET Internal IGBT gate a2 SC a1 a3 a4 a8 SC reference voltage Output current Ic(A) Sense voltage of the shunt resistance CR circuit time constant DELAY (*Note) Error output Fo a5 Note : The CR time constant safe guards against erroneous SC fault signals resulting from di/dt generated voltages when the IGBT turns ON. The optimum setting for the CR circuit time constant is 1.5~2.0µs. [B] Under-Voltage Protection (N-side, UVD) a1. Normal operation : IGBT ON and carrying current. a2. Under voltage trip (UVDt). a3. IGBT OFF inspite of control input condition. a4. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor CFO. a5. Under voltage reset (UVDr). a6. Normal operation : IGBT ON and carrying current. Control input Protection circuit state SET UVDr UVDt a2 RESET Control supply voltage VD a5 a1 Output current Ic(A) a3 a6 Error output Fo (N-side only) a4 Aug. 1999 MITSUBISHI SEMICONDUCTOR PS21205 TRANSFER-MOLD TYPE INSULATED TYPE [C] Under-Voltage Protection (P-side, UVDB) a1. Control supply voltage rises : After the voltage level reachs UVDBr, the circuits start to operate when the next input is applied. a2. Normal operation : IGBT ON and carrying current. a3. Under voltage trip (UVDBt). a4. IGBT OFF inspite of control input condition, but there is no FO signal output. a5. Under-voltage reset (UVDBr). a6. Normal operation : IGBT ON and carrying current. Control input Protection circuit state UVDBr Control supply voltage VDB RESET SET RESET a1 UVDBt a2 a5 a3 a4 a6 Output current Ic(A) High-level (no fault output) Error output Fo Fig. 7 RECOMMENDED CPU I/O INTERFACE CIRCUIT 5V line 4.7kΩ 5.1kΩ DIP-IPM UP,VP,WP,UN,VN,WN CPU Fo 1nF 1nF VNC(Logic) Note : RC coupling at each input (parts shown dotted) may change depending on the PWM control scheme used in the application and on the wiring impedances of the application’s printed circuit board. Aug. 1999 MITSUBISHI SEMICONDUCTOR PS21205 TRANSFER-MOLD TYPE INSULATED TYPE Fig. 8 TYPICAL DIP-IPM APPLICATION CIRCUIT EXAMPLE For detailed description of the boot - strap circuit construction, please contact Mitsubishi Electric C1: Tight to lerance temp - compensated electrolytic type; C2,C3: 0.22~2 µ F R -category ceramic capacitor for noise filtering (Note : The capacitance value depends on the PWM control used in the applied system) 5V line C2 C1 VUFB VUFS VP1 VCC VB HO VS DIP-IPM P C3 UP IN COM C2 U VVFB C1 VVFS VP1 VCC IN VB HO VS C3 VP C2 COM V VWFB C1 M C P U U N I T VWFS VP1 VCC VB HO VS C3 WP IN VPC COM W UOUT C3 VN1 VCC 5V line VOUT UN VN WN Fo VNC 15V line UN VN WN Fo GND VNO CIN CFO WOUT N C CFO C4(CFO ) C5 CIN B R1 Shunt Resistor RSh N1 A Note 1 : To prevent the input signals oscillation, an RC coupling at each input is recommended, and the wiring of each input should be as short as possible. (Less than 2cm) 2 : By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. 3 : FO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 5.1kΩ resistance. 4 : FO output pulse width should be decided by connecting an external capacitor between CFO and V NC terminals (CFO). (Example : CFO = 22 nF → tFO = 1.8 ms (typ.)) 5 : Each input signal line should be pulled up to the 5V power supply with approximately 4.7kΩ resistance (other RC coupling circuits at each input may be needed depending on the PWM control scheme used and on the wiring impedances of the system’s printed circuit board). Approximately a 0.22~2µF by-pass capacitor should be used across each power supply connection terminals. 6 : To prevent errors of the protection function, the wiring of A, B, C should be as short as possible. 7 : In the recommended protection circuit, please select the R1C5 time constant in the range 1.5~2 µs. 8 : Each capacitor should be put as nearby the pins of the DIP-IPM as possible. 9 : To prevent surge destruction, the wiring between the smoothing capacitor and the P&N1 pins should be as short as possible. Approximately a 0.1~0.22µF snubber capacitor between the P&N1 pins is recommended. Aug. 1999