PS21869-P

MITSUBISHI SEMICONDUCTOR MITSUBISHI SEMICONDUCTOR PS21869-P/AP PS21869-P/AP TRANSFER-MOLD TYPE TRANSFER-MOLD TYPE INSULATED TYPE INSULATED TYPE PS21869 INTEGRATED POWER FUNCTIONS 600V/50A CSTBT inverter bridge for three phase DC-to-AC power conversion INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS • • • • • For upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting, Control supply under-voltage (UV) protection. For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC). Fault signaling : Corresponding to an SC fault (Lower-leg IGBT) or a UV fault (Lower-side supply). Input interface : 3, 5V line CMOS/TTL compatible. (High Active) UL Approved : Yellow Card No. E80276 APPLICATION AC100V~200V inverter drive for small power motor control. Fig. 1 PACKAGE OUTLINES (Short-pin type : PS21869-P) Refer Fig. 6 for long-pin type : PS21869-AP. Dimensions in mm TERMINAL CODE 27×2.8(=75.6) 2.8±0.3 (8.5)(2.4) (14.4) (2.5) (4.5) (3.1) 1 2 3 4 56 7 8 9 10 (17.6) 11 12 13 (2.4) 14 15 16 17 18 19 20 21 C (2.2) (1) D 27 28 29 30 31 32 33 34 35 36 (4.65) (3.5) (2.9) (10) (4.65) Type name , Lot No. 41 40 11.5±0.5 31±0.5 13.4±0.5 (1.5) (10) 37 38 39 (11) (1.5) 2-φ4.5±0.2 34.9±0.5 21.4±0.5 HEAT SINK SIDE 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. UP VP1 VUFB VUFS VP VP1 VVFB VVFS WP VP1 VPC VWFB VWFS 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. VN1 VNC CIN CFO FO UN VN WN P U V W N (3.5) (1.5) DUMMY TERMINAL CODE 27. 28. 29. 30. 31. 32. 33. 34. Irregular solder remains 0.5MAX 0.8±0.2 0.45±0.2 0.8±0.2 0.45±0.2 0.45±0.2 1.6±0.5 (0.6) (2) (1.5) 22 23 24 25 26 (0.6) (2) 1 MIN 2.5 D 3.8±0.2 (1.5) 8.5±0.3 10±0.3 10±0.3 10±0.3 67±0.3 79±0.5 A 20±0.3 VPC UPG P VPC VPG U WPG V 35. 36. 37. 38. 39. 40. 41. UNG VNC VNO WNG VNG W P B 7±0.5 12.8±0.5 1±0.2 Irregular solder remains 0.5MAX 1 0.7±0.2 0.8±0.2 0.7±0.2 ±0.2 (3.8) 1MIN C0 .2 C 0. 2 (0 ~ 5°) (2.5) TERMINAL 22, 26 OTHER TERMINAL DETAIL A (5 pins t = 0.7) OTHER TERMINAL TERMINAL 1-2, 20-21 DETAIL B (21 pins t = 0.7) DETAIL D (5 parts) DETAIL C (2 parts) All outer lead terminals are with Pb-free solder (Sn-Cu) plating. Jul. 2005 0.7MIN D HEAT SINK SIDE D 1.6±0.5 MITSUBISHI SEMICONDUCTOR PS21869-P/AP TRANSFER-MOLD TYPE INSULATED TYPE Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE) CBW+ CBW– CBV+ CBV– CBU– CBU+ C1 : Tight tolerance, temp-compensated electrolytic type (Note : The capacitance value depends on the PWM control scheme used in the applied system). C2 : 0.22~2µF R-category ceramic capacitor for noise filtering. High-side input (PWM) (3, 5V line) (Note 1, 2) Input signal Input signal Input signal conditioning conditioning conditioning Level shifter Level shifter Level shifter Protection circuit (UV) Protection circuit (UV) Protection circuit (UV) C2 (Note 7) C1 (Note 6) DIP-IPM Inrush current limiter circuit P Drive circuit Drive circuit Drive circuit AC line input H-side IGBTS (Note 4) U V W M AC line output C Z Fig. 3 N1 VNC N CIN L-side IGBTS Drive circuit Z : ZNR (Surge absorber) C : AC filter (Ceramic capacitor 2.2~6.5nF) (Note : Additionally, an appropriate line-to line surge absorber circuit may become necessary depending on the application environment). Input signal conditioning Fo logic Protection circuit Control supply Under-Voltage protection FO CFO Low-side input (PWM) (3, 5V line) (Note 1, 2) Fault output (5V line) (Note 3, 5) (Note 7) VNC VD (15V line) Note1: 2: 3: 4: 5: 6: 7: Input logic is high-active. There is a 2.5kΩ (min) pull-down resistor built-in each input circuit. When using an external CR filter, please make it satisfy the input threshold voltage. By virtue of integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer isolation is possible. (see also Fig. 10) This output is open drain type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 10kΩ resistance. (see also Fig. 10) The wiring between the power DC link capacitor and the P, N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P-N1 DC power input pins. Fo output pulse width should be decided by putting external capacitor between CFO and VNC terminals. (Example : CFO=22nF → tFO=1.8ms (Typ.)) High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit. It is recommended to insert a Zener diode (24V/1W) nearby each pair of supply terminals to prevent surge destruction. Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT DIP-IPM Drive circuit P Short Circuit Protective Function (SC) : SC protection is achieved by sensing the L-side DC-Bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the RC circuit). When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is recommended to stop the system when the Fo signal is received and check the fault. IC (A) SC Protection Trip Level H-side IGBTS U V W L-side IGBTS External protection circuit N1 Shunt Resistor (Note 1) A N VNC CIN B Drive circuit Collector current waveform CR C Protection circuit (Note 2) 0 2 tw (µs) Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs. 2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible. Jul. 2005 MITSUBISHI SEMICONDUCTOR PS21869-P/AP TRANSFER-MOLD TYPE INSULATED TYPE MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol VCC VCC(surge) VCES ±I C ±ICP PC Tj Parameter Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature Condition Applied between P-N Applied between P-N Tf = 25°C Tf = 25°C, less than 1ms Tf = 25°C, per 1 chip (Note 1) Ratings 450 500 600 50 100 70.4 –20~+125 Unit V V V A A W °C Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ Tf ≤ 100°C) however, to ensure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ Tf ≤ 100°C). CONTROL (PROTECTION) PART Symbol VD VDB VIN VFO IFO VSC Parameter Control supply voltage Control supply voltage Input voltage Fault output supply voltage Fault output current Current sensing input voltage Condition Applied between VP1-VPC, VN1-VNC Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS Applied between UP, VP, WP-VPC, UN, VN, WN-VNC Applied between FO-VNC Sink current at FO terminal Applied between CIN-VNC Ratings 20 20 –0.5~VD+0.5 –0.5~VD+0.5 1 –0.5~VD+0.5 Unit V V V V mA V TOTAL SYSTEM Parameter VCC(PROT) Self protection supply voltage limit (short circuit protection capability) Module case operation temperature Tf Tstg Storage temperature Viso Isolation voltage Symbol Condition VD = 13.5~16.5V, Inverter part Tj = 125°C, non-repetitive, less than 2 µs (Note 2) 60Hz, Sinusoidal, AC 1 minute, connection pins to heat-sink plate Ratings 400 –20~+100 –40~+125 2500 Unit V °C °C Vrms Note 2 : Tf measurement point Al Board Specification : Dimensions : 100✕100✕10mm, Finishing : 12s, Warp : –50~100µm Control Terminals Groove DIP-IPM 18mm 13.5mm P U V W N AI board Power Terminals FWDi Chip IGBT Chip Temp. measurement point (inside the AI board) Temp. measurement point (inside the AI board) Silicon-grease should be applied evenly with a thickness of 100~200µm Jul. 2005 MITSUBISHI SEMICONDUCTOR PS21869-P/AP TRANSFER-MOLD TYPE INSULATED TYPE THERMAL RESISTANCE Symbol Rth(j-f)Q Rth(j-f)F Parameter Junction to case thermal resistance (Note 3) Condition Inverter IGBT part (per 1/6 module) Inverter FWDi part (per 1/6 module) Min. — — Limits Typ. — — Max. 1.42 2.00 Unit °C/W °C/W Note 3 : Grease with good thermal conductivity should be applied evenly with about +100µm~+200µm on the contacting surface of DIP-IPM and heat-sink. ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol VCE(sat) VEC ton trr tc(on) toff tc(off) ICES Parameter Collector-emitter saturation voltage FWDi forward voltage Condition VD = VDB = 15V IC = 50A, Tj = 25°C VIN = 5V IC = 50A, Tj = 125°C Tj = 25°C, –IC = 50A, VIN = 0V VCC = 300V, VD = VDB = 15V IC = 50A, Tj = 125°C, VIN = 0 ↔ 5V Inductive load (upper-lower arm) Tj = 25°C Tj = 125°C Min. — — — 0.70 — — — — — — Limits Typ. 1.50 1.60 1.70 1.30 0.30 0.40 2.00 0.65 — — Max. 2.00 2.10 2.20 1.90 — 0.60 2.60 0.90 1 10 Unit V V µs µs µs µs µs mA Switching times Collector-emitter cut-off current VCE = VCES CONTROL (PROTECTION) PART Symbol Parameter Condition VD = VDB = 15V Total of VP1-VPC, VN1-VNC VIN = 5V VUFB-VUFS, VVFB-VVFS, VWFB-VWFS VD = VDB = 15V Total of VP1-VPC, VN1-VNC VIN = 0V VUFB-VUFS, VVFB-VVFS, VWFB-VWFS VSC = 0V, FO circuit pull-up to 5V with 10kΩ VSC = 1V, IFO = 1mA Tf = –20~100°C, VD = 15V (Note 4) VIN = 5V Trip level Reset level Tj ≤ 125°C Trip level Reset level CFO = 22nF (Note 5) Min. — — — — 4.9 — 0.45 1.0 10.0 10.5 10.3 10.8 1.0 2.1 0.8 Limits Typ. — — — — — — — 1.5 — — — — 1.8 2.3 1.4 Max. 7.00 0.55 7.00 0.55 — 0.95 0.52 2.0 12.0 12.5 12.5 13.0 — 2.6 2.1 Unit mA mA mA mA V V V mA V V V V ms V V ID Circuit current VFOH Fault output voltage VFOL VSC(ref) Short circuit trip level Input current IIN UVDBt Control supply under-voltage UVDBr protection UVDt UVDr Fault output pulse width tFO ON threshold voltage Vth(on) Applied between UP, VP, WP-VPC, UN, VN, WN-VNC OFF threshold voltage Vth(off) Note 4 : Short circuit protection is functioning only for the low-arms. Please select the external shunt resistor such that the SC trip-level is less than 2.0 times of the current ratings. 5 : Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulse width tFO depends on the capacitance value of CFO according to the following approximate equation : CFO = 12.2 ✕ 10-6 ✕ tFO [F]. Jul. 2005 MITSUBISHI SEMICONDUCTOR PS21869-P/AP TRANSFER-MOLD TYPE INSULATED TYPE MECHANICAL CHARACTERISTICS AND RATINGS Parameter Mounting torque Weight Heat-sink flatness Mounting screw : M4 Condition Recommended : 1.18 N·m (Note 6) Min. 0.98 — –50 Limits Typ. — 65 — Max. 1.47 — 100 Unit N·m g µm Note 6 : Measurement point of heat-sink flatness +– Measurement location 3mm Heat-sink side – + Heat-sink side RECOMMENDED OPERATION CONDITIONS Symbol VCC VD VDB ∆VD, ∆VDB tdead fPWM IO PWIN(on) Parameter Supply voltage Control supply voltage Control supply voltage Control supply variation Arm shoot-through blocking time PWM input frequency Allowable r.m.s. current Condition Applied between P-N Applied between VP1-VPC, VN1-VNC Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS For each input signal, Tf ≤ 100°C Tf ≤ 100°C, Tj ≤ 125°C VCC = 300V, VD = VDB = 15V, fPWM = 5kHz P.F = 0.8, sinusoidal output fPWM = 15kHz Tf ≤ 100°C, Tj ≤ 125°C (Note 7) (Note 8) 200 ≤ VCC ≤ 350V, Below rated current 13.5 ≤ VD ≤ 16.5V, 13.0 ≤ VDB ≤ 18.5V, Between rated current and 1.7 times of rated current –20°C ≤ Tf ≤ 100°C, N-line wiring inductance less Between 1.7 times and than 10nH (Note 9) 2.0 times of rated current Recommended value Min. Typ. Max. 0 13.5 13.0 –1 2 — — — 0.3 3.0 5.0 5.9 300 15.0 15.0 — — — — — — — — — 400 16.5 18.5 1 — 20 23.6 Arms 13.8 — — — — µs Unit V V V V/µs µs kHz Allowable minimum input PWIN(off) pulse width — VNC VNC variation –5.0 V between VNC-N (including surge) 5.0 Note 7 : The allowable r.m.s. current value depends on the actual application conditions. 8 : The input pulse width less than PWIN(on) might make no response. 9 : IPM might make delayed response (less than 2µsec) or no response for the input signal with off pulse width less than PWIN(off). Please refer Fig. 4 for details. Jul. 2005 MITSUBISHI SEMICONDUCTOR PS21869-P/AP TRANSFER-MOLD TYPE INSULATED TYPE Fig. 4 CURRENT OUTPUT WHEN INPUT SIGNAL IS LESS THAN ALLOWABLE MINIMUM INPUT PULSE WITH PWIN(off) (P-side only) P-side control input Internal IGBT gate Output current Ic t2 t1 Real line ... off pulse width > PWIN(off) : turn on time t1 Broken line ... off pulse width < PWIN(off) : turn on time t2 Fig. 5 THE DIP-IPM INTERNAL CIRCUIT VUFB VUFS VP1 UP HVIC1 VCC VB HO VS DIP-IPM P IGBT1 Di1 IN COM U VVFB VVFS VP1 VP HVIC2 VCC VB HO VS IGBT2 Di2 IN COM V VWFB VWFS VP1 WP VPC HVIC3 VCC VB HO VS IGBT3 Di3 IN COM W IGBT4 Di4 LVIC UOUT VN1 VCC IGBT5 VOUT Di5 UN VN WN Fo UN VN WN Fo GND VNO CIN WOUT IGBT6 Di6 VNC CFO N CFO CIN Jul. 2005 TERMINAL CODE 27×2.8(=75.6) (2.5) (17.6) (2.2) D (1) 11 12 13 14 15 16 17 18 19 20 21 2.8±0.3 (2.4) C (8.5) (2.4) 7 8 9 10 (14.4) (4.5) (3.1) 1 2 3 4 56 27 32 34 36 28 30 31 33 35 29 21.4±0.5 (11) (4.65) 31±0.5 Type name , Lot No. 11.5±0.5 13.4±0.5 35±0.6 37 38 39 (10) (1.5) 2-φ4.5±0.2 HEAT SINK SIDE 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. DUMMY TERMINAL CODE UP VP1 VUFB VUFS VP VP1 VVFB VVFS WP VP1 VPC VWFB VWFS 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. VN1 VNC CIN CFO FO UN VN WN P U V W N (3.5) (4.65) (3.5) (2.9) (10) (0.6) 24 25 26 22 23 (0.6) (2) 1 MIN 2.5 3.8±0.2 D (2) 10±0.3 20 (1.5) ±0.3 Fig. 6 PACKAGE OUTLINES (Long-pin type : PS21869-AP) (1.5) 67±0.3 79±0.5 8.5±0.3 10±0.3 10±0.3 (1.5) 40 (1.5) 41 27. 28. 29. 30. 31. 32. 33. 34. VPC UPG P VPC VPG U WPG V 35. 36. 37. 38. 39. 40. 41. UNG VNC VNO WNG VNG W P A (1) B 1±0.2 0.7±0.2 0.7±0.2 (1) 1±0.2 (0.7) 0.8±0.2 (0.6) 0.8±0.2 0.45±0.2 0.8±0.2 0.45±0.2 0.45±0.2 (3.8) 1MIN 16±0.5 7±0.5 Irregular solder remains 0.5MAX 1.6±0.5 Irregular solder remains 0.5MAX 1.6±0.5 C0 .2 (0 ~ 5°) D (2.5) HEAT SINK SIDE D TERMINAL 22, 26 OTHER TERMINAL TERMINAL 1-2, 20-21 DETAIL B (21 pins t = 0.7) DETAIL D (5 parts) OTHER TERMINAL DETAIL A (5 pins t = 0.7) PS21869-P/AP DETAIL C (2 parts) 0.7MIN C 0. 2 MITSUBISHI SEMICONDUCTOR TRANSFER-MOLD TYPE INSULATED TYPE Jul. 2005 MITSUBISHI SEMICONDUCTOR PS21869-P/AP TRANSFER-MOLD TYPE INSULATED TYPE Fig. 7 TIMING CHARTS OF THE DIP-IPM PROTECTIVE FUNCTIONS [A] Short-Circuit Protection (Lower-arms only with the external shunt resistor and CR filter) a1. Normal operation : IGBT ON and carrying current. a2. Short circuit current detection (SC trigger). a3. IGBT gate hard interruption. a4. IGBT turns OFF. a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor CFO. a6. Input “L” : IGBT OFF. a7. Input “H” : IGBT ON. a8. IGBT OFF in spite of input “H”. Lower-arms control input Protection circuit state SET a6 a7 RESET Internal IGBT gate a2 a1 Output current Ic Sense voltage of the shunt resistor SC a3 a4 a8 SC reference voltage CR circuit time constant DELAY Error output Fo a5 [B] Under-Voltage Protection (Lower-arm, UVD) b1. Control supply voltage rises : After the voltage level reaches UVDr, the circuits start to operate when next input is applied. b2. Normal operation : IGBT ON and carrying current. b3. Under voltage trip (UVDt). b4. IGBT OFF in spite of control input condition. b5. FO operation starts. b6. Under voltage reset (UVDr). b7. Normal operation : IGBT ON and carrying current. Control input Protection circuit state UVDr RESET SET RESET b6 Control supply voltage VD b1 UVDt b3 b4 b2 Output current Ic b7 Error output Fo b5 Jul. 2005 MITSUBISHI SEMICONDUCTOR PS21869-P/AP TRANSFER-MOLD TYPE INSULATED TYPE [C] Under-Voltage Protection (Upper-arm, UVDB) c1. Control supply voltage rises : Operation starts soon after UVDBr. c2. Protection circuit state reset : IGBT ON : Currents output. c3. Normal operation : IGBT ON and carrying current. c4. Under voltage trip (UVDBt). c5. IGBT OFF in spite of control input condition, but there is no FO signal output. c6. Under voltage reset (UVDBr). c7. Normal operation : IGBT ON and carrying current. Control input Protection circuit state Control supply voltage VDB RESET UVDBr c1 c2 UVDBt c3 SET RESET c6 c4 c5 c7 Output current Ic Error output Fo High-level (no fault output) Fig. 8 RECOMMENDED CPU I/O INTERFACE CIRCUIT 5V line 10kΩ DIP-IPM UP,VP,WP,UN,VN,WN MCU Fo VNC(Logic) Note : RC coupling at each input (parts shown dotted) may change depending on the PWM control scheme used in the application and the wiring impedance of the application’s printed circuit board. The DIP-IPM input signal section integrates a 2.5kΩ(min) pull-down resistor. Therefore, when using a external filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement. Fig. 9 WIRING CONNECTION OF SHUNT RESISTOR DIP-IPM Wiring inductance should be less than 10nH. Equivalent to the inductance of a copper pattern with length=17mm, width=3mm, and thickness=100µm VNC N Shunt resistor Please make the GND wiring connection of shunt resistor to the VNC terminal as close as possible. Jul. 2005 MITSUBISHI SEMICONDUCTOR PS21869-P/AP TRANSFER-MOLD TYPE INSULATED TYPE Fig. 10 TYPICAL DIP-IPM APPLICATION CIRCUIT EXAMPLE C1:Tight tolerance temp-compensated electrolytic type C2,C3: 0.22~2µF R-category ceramic capacitor for noise filtering. C2 C1 VUFB VUFS VP1 HVIC1 VCC VB HO VS DIP-IPM P C3 UP IN COM U C2 C1 VVFB VVFS VP1 HVIC2 VCC IN COM VB HO VS C3 VP V C2 C1 VWFB VWFS VP1 HVIC3 VCC VB HO VS M Note 1 : To prevent the input signals oscillation, the wiring of each input should be as short as possible. (Less than 2cm) 2 : By virtue of integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer isolation is possible. 3 : FO output is open drain type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 10kΩ resistor. 4 : FO output pulse width is determined by the external capacitor between CFO and VNC terminals (CFO). (Example : CFO = 22nF → tFO = 1.8ms (typ.)) 5 : The logic of input signal is high-active. The DIP-IPM input signal section integrates a 2.5kΩ (min) pull-down resistor. Therefore, when using external filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement. 6 : To prevent malfunction of protection, the wiring of A, B, C should be as short as possible. 7 : Please set the R1C5 time constant in the range 1.5~2µs. 8 : Each capacitor should be located as nearby the pins of the DIP-IPM as possible. 9 : To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 pins should be as short as possible. Approximately a 0.1~0.22µF snubber capacitor between the P-N1 pins is recommended. 10 : It is recommended to insert a Zener diode (24V/1W) nearby each pair of supply terminals to prevent surge destruction. CONTROLLER 5V line 15V line C3 WP IN VPC COM W LVIC UOUT VN1 VCC C3 VOUT UN VN WN Fo VNC UN VN WN Fo GND VNO CIN CFO WOUT Too long wiring here might cause short-circuit. N C CFO C4(CFO ) C5 CIN B R1 Shunt Resistor A Long GND wiring here might generate noise to input and cause IGBT malfunction. If this wiring is too long, the SC level fluctuation might be larger and cause SC malfunction. N1 Jul. 2005