1715653003

ZQSFP+ STACKED CONNECTOR BOARD ROUTING RECOMMENDATIONS TABLE OF CONTENTS 1.0 SCOPE 2.0 PC BOARD REQUIREMENTS 2.1 MATERIAL THICKNESS 2.2 TOLERANCE 2.3 HOLE DIMENSIONS 2.4 LAYOUT 3.0 HIGHSPEED ROUTING 3.1 GENERAL ROUTING EXAMPLE 3.2 HIGH-SPEED TRANSMISSION LINE PLANE 3.3 HIGH-SPEED REFERENCE PLANE ANTI-PAD 3.4 CONNECTOR PRESS-FIT INTERFACE VIA STUBS 3.5 SKEW COMPENSATION 3.6 TRACE COMPARSION 4.0 PIN ASSIGNMENTS Routing Guideline Views .bdl REVISION: 2 ECR/ECN INFORMATION: EC No: UCP2013-5477 DATE: 2013/06/19 DOCUMENT NUMBER: AS-171565-0002 TITLE: SHEET No. SI ROUTING GUIDELINES FOR ZQSFP+ STACKED CONNECTORS CREATED / REVISED BY: CHECKED BY: 1 of 13 APPROVED BY: Jkachlic TEMPLATE FILENAME: AS1712080002.DOC ZQSFP+ STACKED CONNECTOR BOARD ROUTING RECOMMENDATIONS 1.0 SCOPE This specification covers the high-speed PCB routing recommendations for the 0.80mm centerline Stacked zQSFP+ Connector series products listed below. The connector is a stacked dual port assembly and is available in a 2x1,2x2, 2X3 configuration. Eight differential pairs are assigned per port. The connector has 38 contacts per port of which 26 can be assigned to signals and 12 are for ground terminals. The connector is a right angle press-fit compliant pin type designed for use with 0.37mm finished vias for the signal pins. The connector has compliant pin contacts for mechanical retention to the PC board. The connector provides inner electromagnetic interference (EMI) suppression ground spring-fingers that contact the mating plug and is available with either an outer Elastomeric or Metal EMI gasket that contacts the panel. The connector assembly is designed to be inserted through a standard bezel after being seated onto the PC board. Disclaimer: Molex does not guarantee the performance of the final product to match the information provided in this document. All information in this report is considered proprietary, confidential and the property of Molex Inc. This guide is not intended as a substitute for engineering analysis. Product Series 171208-**** 171262-**** 171565-**** 171722-**** 170879-**** 171233-**** Description 2X1 Connector with Elastomeric EMI Gasket 2X3 Connector with Elastomeric EMI Gasket 2X1 thru 2X3 Connector with Elastomeric EMI Gasket and Enhanced EMI cage 2X1 thru 2X3 Connector with Metal EMI Gasket and Enhanced EMI cage 2X1 Connector with Thermal Management Component 2X3 Connector with Thermal Management Component 2.0 PC BOARD REQUIREMENTS 2.1 MATERIAL THICKNESS The recommended minimum pc board thickness shall be 1.57 mm. Suitable pc board material shall be glass epoxy (FR-4 or G-10). 2.2 TOLERANCE Maximum allowable bow of the pc board shall be 0.08 mm over the length of the connector assembly. 2.3 HOLE DIMENSIONS The holes for the connector assembly must be drilled and plated through to dimensions specified in Figure 2. 2.4 LAYOUT The holes for the connector assembly must be precisely located to ensure proper placement and optimum performance of the connector assembly. Recommended hole pattern, dimensions, and tolerances are provided in Figure 3. REVISION: 2 ECR/ECN INFORMATION: EC No: UCP2013-5477 DATE: 2013/06/19 DOCUMENT NUMBER: AS-171565-0002 TITLE: SHEET No. SI ROUTING GUIDELINES FOR ZQSFP+ STACKED CONNECTORS CREATED / REVISED BY: CHECKED BY: 2 of 13 APPROVED BY: Jkachlic TEMPLATE FILENAME: AS1712080002.DOC ZQSFP+ STACKED CONNECTOR BOARD ROUTING RECOMMENDATIONS Recommended Hole Dimensions DIM. “A” DIM. “B” DIM. “C” MM / (INCH) MM / (INCH) - # DRILL MM / (INCH) 1.05+/-0.05 (.0413+/-.002) 1.181 (.0465) - # 56 1.40 (.055) 0.81+/-0.05 (.032+/-.002) 0.914 (.036) - # 64 1.16 (.046) 0.56+/-0.05 (.022+/-.002) 0.660 (.026) - # 71 0.91 (.036) 0.46+/-0.05 (.0181+/-.002) 0.572 (.022) - # 74 0.81 (.032) 0.37+/-0.05 (.0146+/-.002) 0.457 (.018) - # 77 0.72 (.028) Note: Refer to appropriate sales drawing for recommended pcb holes and pcb thickness. PLATING DETAIL FOR COMPLIANT PIN HOLES Figure 2 REVISION: 2 ECR/ECN INFORMATION: EC No: UCP2013-5477 DATE: 2013/06/19 DOCUMENT NUMBER: AS-171565-0002 TITLE: SHEET No. SI ROUTING GUIDELINES FOR ZQSFP+ STACKED CONNECTORS CREATED / REVISED BY: CHECKED BY: 3 of 13 APPROVED BY: Jkachlic TEMPLATE FILENAME: AS1712080002.DOC ZQSFP+ STACKED CONNECTOR BOARD ROUTING RECOMMENDATIONS Recommended PC Board Layout for the Connector Assembly Connector Pattern Detail Figure 3 REVISION: 2 ECR/ECN INFORMATION: EC No: UCP2013-5477 DATE: 2013/06/19 DOCUMENT NUMBER: AS-171565-0002 TITLE: SHEET No. SI ROUTING GUIDELINES FOR ZQSFP+ STACKED CONNECTORS CREATED / REVISED BY: CHECKED BY: 4 of 13 APPROVED BY: Jkachlic TEMPLATE FILENAME: AS1712080002.DOC ZQSFP+ STACKED CONNECTOR BOARD ROUTING RECOMMENDATIONS Recommended Keep-out Zone Area Layout on PC Board for Connector Assembly Notes: 1. The entire area under the connector cage is a component keep-out zone. The area under the connector module is a trace keep-out area 2. Cross hatched areas indicate places where the plastic housing and metal cage may be in contact with the PCB surface. These areas are trace keep-out zones. 3. These rectangular zones are for LED placement. LED height should not exceed 0.8 and placement should be centered within this LED keep-in zone. 4. Recommended LED chip package size is 0805. REVISION: 2 ECR/ECN INFORMATION: EC No: UCP2013-5477 DATE: 2013/06/19 DOCUMENT NUMBER: AS-171565-0002 TITLE: SHEET No. SI ROUTING GUIDELINES FOR ZQSFP+ STACKED CONNECTORS CREATED / REVISED BY: CHECKED BY: 5 of 13 APPROVED BY: Jkachlic TEMPLATE FILENAME: AS1712080002.DOC ZQSFP+ STACKED CONNECTOR BOARD ROUTING RECOMMENDATIONS 3.0 HIGH-SPEED ROUTING 3.1 GENERAL 2X3 ROUTING EXAMPLE Showing 6 layers overlaid for a 2X3 side by side configuration with EMI pin field Routing example shown for reference only. Shown with 0.127mm (0.005”) traces and 0.254mm (0.010”) spaces 0.75mm (0.0295”) spaces between pair traces. REVISION: 2 1ST LAYER 2ND LAYER 3RD LAYER 4TH LAYER 5TH LAYER 6TH LAYER ECR/ECN INFORMATION: EC No: UCP2013-5477 DATE: 2013/06/19 DOCUMENT NUMBER: AS-171565-0002 TITLE: SHEET No. SI ROUTING GUIDELINES FOR ZQSFP+ STACKED CONNECTORS CREATED / REVISED BY: CHECKED BY: 6 of 13 APPROVED BY: Jkachlic TEMPLATE FILENAME: AS1712080002.DOC ZQSFP+ STACKED CONNECTOR BOARD ROUTING RECOMMENDATIONS Showing 4 layers overlaid for a 2X3 side by side configuration with EMI pin field Routing example shown for reference only. Shown with 0.127mm (0.005”) traces and 0.254mm (0.010”) spaces 0.75mm (0.0295”) spaces between pair traces. 1ST LAYER 2ND LAYER 3RD LAYER REVISION: 2 ECR/ECN INFORMATION: EC No: UCP2013-5477 DATE: 2013/06/19 DOCUMENT NUMBER: AS-171565-0002 4TH LAYER TITLE: SHEET No. SI ROUTING GUIDELINES FOR ZQSFP+ STACKED CONNECTORS CREATED / REVISED BY: CHECKED BY: 7 of 13 APPROVED BY: Jkachlic TEMPLATE FILENAME: AS1712080002.DOC ZQSFP+ STACKED CONNECTOR BOARD ROUTING RECOMMENDATIONS 3.2 HIGH-SPEED TRANSMISSION LINE PLANE Reference ground layer shown and spacing between trace pairs Routing example shown for reference only REVISION: 2 ECR/ECN INFORMATION: EC No: UCP2013-5477 DATE: 2013/06/19 DOCUMENT NUMBER: AS-171565-0002 TITLE: SHEET No. SI ROUTING GUIDELINES FOR ZQSFP+ STACKED CONNECTORS CREATED / REVISED BY: CHECKED BY: 8 of 13 APPROVED BY: Jkachlic TEMPLATE FILENAME: AS1712080002.DOC ZQSFP+ STACKED CONNECTOR BOARD ROUTING RECOMMENDATIONS Trace detail typical for all trace positions Note: Option pinning VIA within connector footprint for additional electrical performance, location and size can vary from recommendation to meet board thickness, routing and electrical performance requirements. REVISION: 2 ECR/ECN INFORMATION: EC No: UCP2013-5477 DATE: 2013/06/19 DOCUMENT NUMBER: AS-171565-0002 TITLE: SHEET No. SI ROUTING GUIDELINES FOR ZQSFP+ STACKED CONNECTORS CREATED / REVISED BY: CHECKED BY: 9 of 13 APPROVED BY: Jkachlic TEMPLATE FILENAME: AS1712080002.DOC ZQSFP+ STACKED CONNECTOR BOARD ROUTING RECOMMENDATIONS 3.3 HIGH-SPEED REFERENCE PLANE ANTI-PAD Signal Ground Planes REVISION: 2 ECR/ECN INFORMATION: EC No: UCP2013-5477 DATE: 2013/06/19 DOCUMENT NUMBER: AS-171565-0002 Non-Signal Planes TITLE: SHEET No. SI ROUTING GUIDELINES FOR ZQSFP+ STACKED CONNECTORS CREATED / REVISED BY: CHECKED BY: 10 of 13 APPROVED BY: Jkachlic TEMPLATE FILENAME: AS1712080002.DOC ZQSFP+ STACKED CONNECTOR BOARD ROUTING RECOMMENDATIONS 3.4 CONNECTOR PRESS-FIT INTERFACE VIA STUBS BOTTOM LAUNCH DRIVEN VIA (PREFERRED) TOP LAUNCH STUB VIA (WORSE CASE) BACK DRILL DEPTH NOT TO EXCEED 1.00mm FROM TOP STANDARD VIA CONFIGURATION Only two annular rings are required for retention of the press-fit via within the printed circuit consequently annular rings on the bottom layer are not needed. Removing the bottom layer annular ring helps minimize the parasitic stub capacitance created by the via. The anti-pad can be used on other ground layers not shown above. Alternatively, the anti-pad can be made larger with a broader keep-out region on these other ground layers to minimize parasitic capacitance. For the connector press-fit vias, specify not only the 0.37mm (0.014") finished hole size but also the 0.45715mm (0.018") drill size for the board fabrication. REVISION: 2 ECR/ECN INFORMATION: EC No: UCP2013-5477 DATE: 2013/06/19 DOCUMENT NUMBER: AS-171565-0002 TITLE: SHEET No. SI ROUTING GUIDELINES FOR ZQSFP+ STACKED CONNECTORS CREATED / REVISED BY: CHECKED BY: 11 of 13 APPROVED BY: Jkachlic TEMPLATE FILENAME: AS1712080002.DOC ZQSFP+ STACKED CONNECTOR BOARD ROUTING RECOMMENDATIONS 3.5 SKEW COMPENSATION PREFERRED NOT RECOMMENDED It is recommended that skew compensation be distributed verses grouped in one or more locations. 3.6 TRACE COMPARISON TRANSITION SHOULD BE SYMETRIC REVISION: 2 ECR/ECN INFORMATION: EC No: UCP2013-5477 DATE: 2013/06/19 DOCUMENT NUMBER: AS-171565-0002 TITLE: SHEET No. SI ROUTING GUIDELINES FOR ZQSFP+ STACKED CONNECTORS CREATED / REVISED BY: CHECKED BY: 12 of 13 APPROVED BY: Jkachlic TEMPLATE FILENAME: AS1712080002.DOC ZQSFP+ STACKED CONNECTOR BOARD ROUTING RECOMMENDATIONS 4.0 Pin Assignments Notes: 1. See sheet no. 4 for physical locations of pin assignments 2. Reference SFF-8436 for further details Lower Port Pin L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 Symbol GND Tx2n Tx2p GND Tx4n Tx4p GND ModSelL ResetL Vcc Rx SCL SDA GND Rx3p Rx3n GND Rx1p RX1n GND Description Ground Transmitter Inverted Data Input Transmitter Non-Inverted Data Input Ground Transmitter Inverted Data Input Transmitter Non-Inverted Data Input Ground Module Select Module Reset +3.3V Power Supply Receiver 2-wire serial interface clock 2-wire serial interface data Ground Receiver Non-Inverted Data Input Receiver Inverted Data Input Ground Receiver Non-Inverted Data Input Receiver Inverted Data Input Ground Pin L38 L37 L36 L35 L34 L33 L32 L31 L30 L29 L28 L27 L26 L25 L24 L23 L22 L21 L20 Symbol GND Tx1n Tx1p GND Tx3n Tx3p GND LPMode Vcc1 Vcc Tx IntL ModPrsL GND Rx4p Rx4n GND Rx2p RX2n GND Description Ground Transmitter Inverted Data Input Transmitter Non-Inverted Data Input Ground Transmitter Inverted Data Input Transmitter Non-Inverted Data Input Ground Low Power Mode +3.3V Power Supply +3.3V Power Supply Transmitter Interrupt Module Present Ground Receiver Non-Inverted Data Input Receiver Inverted Data Input Ground Receiver Non-Inverted Data Input Receiver Inverted Data Input Ground Description Ground Transmitter Inverted Data Input Transmitter Non-Inverted Data Input Ground Transmitter Inverted Data Input Transmitter Non-Inverted Data Input Ground Module Select Module Reset +3.3V Power Supply Receiver 2-wire serial interface clock 2-wire serial interface data Ground Receiver Non-Inverted Data Input Receiver Inverted Data Input Ground Receiver Non-Inverted Data Input Receiver Inverted Data Input Ground Pin U38 U37 U36 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 U25 U24 U23 U22 U21 U20 Symbol GND Tx1n Tx1p GND Tx3n Tx3p GND LPMode Vcc1 Vcc Tx IntL ModPrsL GND Rx4p Rx4n GND Rx2p RX2n GND Description Ground Transmitter Inverted Data Input Transmitter Non-Inverted Data Input Ground Transmitter Inverted Data Input Transmitter Non-Inverted Data Input Ground Low Power Mode +3.3V Power Supply +3.3V Power Supply Transmitter Interrupt Module Present Ground Receiver Non-Inverted Data Input Receiver Inverted Data Input Ground Receiver Non-Inverted Data Input Receiver Inverted Data Input Ground Pin C8 C9 C10 C11 C12 Symbol GND GND GND GND GND C13 GND Upper Port Pin U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 Symbol GND Tx2n Tx2p GND Tx4n Tx4p GND ModSelL ResetL Vcc Rx SCL SDA GND Rx3p Rx3n GND Rx1p RX1n GND Cage Pin C1 C2 C3 C4 C5 C6 C7 REVISION: 2 Symbol GND GND GND GND GND GND GND Description Ground Ground Ground Ground Ground Ground Ground ECR/ECN INFORMATION: EC No: UCP2013-5477 DATE: 2013/06/19 DOCUMENT NUMBER: AS-171565-0002 Description Ground Ground Ground Ground Ground Ground TITLE: SHEET No. SI ROUTING GUIDELINES FOR ZQSFP+ STACKED CONNECTORS CREATED / REVISED BY: CHECKED BY: 13 of 13 APPROVED BY: Jkachlic TEMPLATE FILENAME: AS1712080002.DOC