MS6821

MOSA MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control 4 Stereo Inputs, 2W BTL Stereo Output 16-bit Stereo DAC and Volume Control FEATURES ‧Operation range: 2.4V ~ 6.5V ‧Volume control range Gain: 0 to 21dB, 3dB/step Attenuation: 0 to –77.5dB, 1.25dB/step ‧4 stereo inputs (mixed with an audio DAC) ‧Output mode : Speaker( BTL)/Headphone(SE) ‧BTL Output power, THD+N=1%, Stereo Input RL=4Ω, 2W at 5V, 0.8W at 3.3V, 360mW at 2.4V RL=8Ω, 1.3W at 5V, 0.53W at 3.3V, 250mW at 2.4V ‧BTL Output power, DAC Input RL=4Ω, 1.6W at 5V, 0.70W at 3.3V, 340mW at 2.4V RL=8Ω, 0.83W at 5V, 0.35W at 3.3V, 170mW at 2.4V ‧Built-in 16-bit Audio DAC ‧Audio format : I2S, Right justified, Left justified ‧Control interface : I2C ‧Excellent Power Supply Rejection Ratio(PSRR) ‧Flexibility power management ‧Component less ‧Reduce pop noise circuit ‧ Housed in SOP28, TSSOP28 package, enhanced thermal PAD APPLICATIONS Multimedia system, Portable Digital Audio. DESCRIPTION The MS6821 is a 16-bits voltage-output Digital-to-Analog Converter (DAC) integrated class AB stereo headphone driver and stereo speaker power amplifier. It can drive 2W of continuous average power into a dual 4Ω bridged-tied (BTL) speaker or 2 * 90mW into stereo 32Ω single ended (SE) headphone. The 16-bit DAC supports general and popular formats as I2S, Right justified. The volume control offers wide range of gain and attenuation for 4-set stereo input. All of the functions are set by I2C interface. The MS6821 has good feature for portable equipment, including wide voltage operation 2.4V ~ 6.5V, low power consumption, flexible power management, component less and small package TSSOP28, make the MS6821 ideally suitable for use in the portable digital audio equipments. BLOCK DIAGRAM REV 3 1/29 www.mosanalog.com MOSA PIN CONFIGURATION Symbol WS BCK CAP RIN1 RIN2 RIN3 RIN4 VSS PVDDR OUTROUTR+ GND PVSSR DACR DACL PVSSL GND OUTL+ OUTLPVDDL VDD LIN4 LIN3 LIN2 LIN1 SDA SCL DATA Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control Description Audio word select input Audio bit clock input Capacitor connected Right channel input 1 Right channel input 2 Right channel input 3 Right channel input 4 Negative supply voltage Positive supply voltage for right channel of power amplifier SE right channel output or negative output of BTL right channel Positive output of BTL right channel Connected to ground Negative supply voltage for right channel of power amplifier DAC right channel output DAC Left channel output Negative supply voltage for left channel of power amplifier Connected to ground Positive output of BTL left channel SE left channel output or negative output of BTL left channel Positive supply voltage for left channel of power amplifier Positive supply voltage Left channel input 4 Left channel input 3 Left channel input 2 Left channel input 1 I2C data input I2C clock input Audio data input WS 1 BCK 2 CAP 3 RIN1 4 RIN2 5 RIN3 6 RIN4 7 VSS 8 PVDDR 9 OUTR- 10 OUTR+ 11 GND 12 PVSSR 13 DACR 14 28 DATA 27 SCL 26 SDA 25 LIN1 24 LIN2 23 LIN3 22 LIN4 21 VDD 20 PVDDL 19 OUTL18 OUTL+ 17 GND 16 PVSSL 15 DACL Note: 1. SE: Single Ended. BTL: Bridged-Tied Load REV 3 2/29 www.mosanalog.com MOSA ORDERING INFORMATION Package 28Pin SOP (lead free) 28Pin SOP (lead free) 28Pin TSSOP (lead free) 28Pin TSSOP (lead free) RoHS Compliance MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control Part number MS6821GTR MS6821GU MS6821TGTR MS6821TGU Packaging Marking MS6821G MS6821G MS6821G MS6821G Transport Media 1k Units Tape and Reel 25 Units Tube 2.5k Units Tape and Reel 50 Units Tube ABSOLUTE MAXIMUM RATINGS Symbol VDD VESD TSTG TA TJ TS RTHJA Supply voltage Electrostatic handling Storage temperature range Operating ambient temperature range Maximum junction temperature Soldering temperature, 10 seconds Thermal resistance from junction to ambient in free air SOP28 TSSOP28 (enhance thermal pad) Parameter Rating 6.5 2000 -65 to 150 -40 to 85 150 260 210 51 Unit V V ℃ ℃ ℃ ℃ ℃/W OPERATING RATINGS Symbol VDD Supply voltage Parameter Min 2.4 Typ 5 Max 6.5 Unit V REV 3 3/29 www.mosanalog.com MOSA Symbol DC Characteristics VCAP VDC Voltage at CAP Output DC level Parameter MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control 5V ELECTRICAL CHARACTERISTICS (Ta=25℃, VDD=5V, VSS=0V, f=1kHz; unless otherwise specified) Conditions Min 0.5VDD -0.05 0.5VDD -0.05 Typ 0.5VDD 0.5VDD 13.0 9.8 9.9 6.7 8.2 6.6 3.2 12 -90 Gain Attenuation 0 -77.5 2 0.8 BTL Mode , RL=8Ω CAP=1uF, f=200Hz SE Mode , RL=32Ω CAP=1uF, f=200Hz BTL Mode, RL=8Ω Po=1W SE Mode, RL=32Ω Po=60mW SE mode, RL=32Ω, 60mW SE mode, A-weighting, 75mW BTL Mode, RL = 4Ω THD+N = 1% BTL Mode, RL = 8Ω THD+N = 1% SE Mode, RL = 32Ω THD+N = 0.1% 61 65 78 81 -65 0.0562 93 2 1.3 93m 3 1.25 0.3 21 0 Max 0.5VDD +0.05 0.5VDD +0.05 0.3 uA dB dB dB dB dB dB V V dB dB dB dB dB % dB W W W mA Unit V V All devices are active, BTL All devices are active, SE DAC PD, BTL IQ Quiescent current DAC PD, SE L-ch (R-ch) PD, BTL DAC active L-ch (R-ch) PD, SE DAC active Only DAC is active All devices power down All devices power down, except CAP=1/2 VDD IPD ATT GARAN GSTEP ASTEP EGA VI2CH VI2CL Power down current Mute attenuation Gain/Attenuation range Gain step Attenuation step Gain/Attenuation step error Serial interface high input level Serial interface low input level AC Characteristics (Stereo input) PSRR Power supply rejection ratio CS Channel separation Total harmonic distortion plus Noise Signal-to-noise ratio THD+N S/N Po Maximum output power PD: Power Down REV 3 4/29 www.mosanalog.com MOSA Symbol Res VFSDAC PSRR CS THD+N S/N Resolution Parameter Audio DAC Characteristics MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control Conditions Min - Typ VFS 66 67 88 Max 16 VFS+1.5% -62 0.079 - Unit bits V dB dB dB % dB W W W (sampling rate=4fs, fs= 44.1kHz, f=1kHz) VFS=0.72 * VDD CAP=1uF (200Hz) CAP=10uF (200Hz) 86 1.44 0.75 41.4m VFS-1.5% Full scale output voltage of DAC Power supply rejection ratio Channel separation Total harmonic distortion plus noise Signal-to-noise ratio DAC output, RL=1kΩ, VFS DAC output, RL=1kΩ, VFS A-weighting BTL Mode, RL = 4Ω THD+N = 0.33% BTL Mode, RL = 8Ω THD+N = 0.15 % SE Mode, RL = 32Ω THD+N = 0.042% -67 0.0447 90 1.6 0.83 46m DACPo Maximum output power using DAC 3.3V ELECTRICAL CHARACTERISTICS (Ta=25℃, VDD=3.3V, VSS=0V, f=1kHz; unless otherwise specified) Symbol DC Characteristics All devices are active, BTL All devices are active, SE DAC PD, BTL IQ Quiescent current DAC PD, SE L-ch (R-ch) PD, BTL DAC active L-ch (R-ch) PD, SE DAC active Only DAC is active 0.63 0.32 18m 11.5 8.5 9 6 7.1 5.6 2.6 -67 0.0447 0.8 0.53 35m -66 0.05 0.70 0.35 20m 60 0.1 60 0.1 dB % W W W dB % W W W mA Parameter Conditions Min Typ Max Unit AC Characteristics (Stereo input) THD+N Total harmonic distortion plus Noise SE mode, RL=32Ω, 35mW BTL Mode, RL = 4Ω THD+N = 1% BTL Mode, RL = 8Ω Po Maximum output power THD+N = 1% SE Mode, RL = 32Ω THD+N = 0.1% Audio DAC Characteristics (sampling rate=4fs, fs= 44.1kHz, f=1kHz) THD+N Total harmonic distortion plus noise DAC output, RL=1kΩ, VFS BTL Mode, RL = 4Ω THD+N = 0.25% BTL Mode, RL = 8Ω THD+N = 0.14 % SE Mode, RL = 32Ω THD+N = 0.052% 5/29 DACPo Maximum output power using DAC REV 3 www.mosanalog.com MOSA Symbol DC Characteristics Parameter MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control 2.4V ELECTRICAL CHARACTERISTICS (Ta=25℃, VDD=2.4V, VSS=0V, f=1kHz; unless otherwise specified) Conditions All devices are active, BTL All devices are active, SE DAC PD, BTL IQ Quiescent current DAC PD, SE L-ch (R-ch) PD, BTL DAC active L-ch (R-ch) PD, SE DAC active Only DAC is active Min 0.31 0.15 9m Typ 9.9 7.1 7.8 5.1 6 4.7 2.2 -65 0.0562 0.36 0.25 15m -63 0.071 0.34 0.17 10m Max -60 0.1 -58 0.126 dB % W W W dB % W W W mA Unit AC Characteristics (Stereo input) THD+N Total harmonic distortion plus Noise SE mode, RL=32Ω, 15mW BTL Mode, RL = 4Ω THD+N = 1% BTL Mode, RL = 8Ω Po Maximum output power THD+N = 1% SE Mode, RL = 32Ω THD+N = 0.1% Audio DAC Characteristics (sampling rate=4fs, fs= 44.1kHz, f=1kHz) THD+N Total harmonic distortion plus noise DAC output, RL=1kΩ, VFS BTL Mode, RL = 4Ω THD+N = 0.85% BTL Mode, RL = 8Ω THD+N = 0.17 % SE Mode, RL = 32Ω THD+N = 0.07% DACPo Maximum output power using DAC REV 3 6/29 www.mosanalog.com MOSA (Ta=25℃; unless otherwise specified) BTL MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control TYPICAL PERFORMANCE CHARACTERISTICS QUIESCENT CURRENT (mA) QUIESCENT CURRENT (mA) BTL SE QUIESCENT CURRENT (mA) BTL SE SE All Devices activate. All Devices activate except DAC LPD or RPD DAC activates. SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Quiescent current vs. supply voltage Quiescent current vs. supply voltage Quiescent current vs. supply voltage QUIESCENT CURRENT (mA) DAC activates only SUPPLY VOLTAGE (V) Quiescent current vs. supply voltage REV 3 7/29 www.mosanalog.com MOSA MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control Stereo inputs signal (Ta=25℃, stereo inputs signal, f=1kHz, DAC is Power Down mode; unless otherwise specified) THD+N (%) VDD=5V, Po=2W BTL mode, RL=4Ω VDD=3.3V, Po=0.8W BTL mode, RL=4Ω THD+N (%) THD+N (%) VDD=2.4V, Po=330mW BTL mode, RL=4Ω FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) THD+N vs. frequency THD+N vs. frequency THD+N vs. frequency THD+N (%) VDD=5V, Po=1.2W BTL mode, RL=8Ω VDD=3.3V, Po=0.53W BTL mode, RL=8Ω THD+N (%) THD+N (%) VDD=2.4V, Po=250mW BTL mode, RL=8Ω FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) THD+N vs. frequency THD+N vs. frequency THD+N vs. frequency THD+N (%) VDD=5V, Po=90mW SE mode, RL=32Ω VDD=3.3V, Po=35mW SE mode, RL=32Ω THD+N (%) THD+N (%) VDD=2.4, Po=15mW SE mode, RL=32Ω FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) THD+N vs. frequency THD+N vs. frequency THD+N vs. frequency REV 3 8/29 www.mosanalog.com MOSA MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control f=20kHz f=20kHz f=20kHz THD+N (%) THD+N (%) f=1kHz f=1kHz THD+N (%) f=1kHz f=20Hz f=20Hz VDD=5V BTL mode RL=4Ω VDD=3.3V BTL mode RL=4Ω f=20Hz VDD=2.4V BTL mode RL=4Ω OUTPUT POWER (W) OUTPUT POWER (W) OUTPUT POWER (W) THD+N vs. output power THD+N vs. output power THD+N vs. output power f=20kHz f=20kHz f=20kHz THD+N (%) THD+N (%) f=1kHz f=20Hz THD+N (%) f=1kHz f=1kHz f=20Hz f=20Hz VDD=5V BTL mode RL=8Ω VDD=3.3V BTL mode RL=8Ω VDD=2.4V BTL mode RL=8Ω OUTPUT POWER (W) OUTPUT POWER (W) OUTPUT POWER (W) THD+N vs. output power THD+N vs. output power THD+N vs. output power f=20kHz f=20kHz f=20kHz f=20Hz THD+N (%) THD+N (%) f=20Hz f=1kHz f=20Hz f=1kHz THD+N (%) f=1kHz VDD=5V SE mode RL=32Ω VDD=3.3V SE mode RL=32Ω VDD=2.4V SE mode RL=32Ω OUTPUT POWER (W) OUTPUT POWER (W) OUTPUT POWER (W) THD+N vs. output power THD+N vs. output power THD+N vs. output power REV 3 9/29 www.mosanalog.com MOSA MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control CHANNEL SEPARATION (dB) VDD=5V, Po=1W BTL, RL=8Ω CHANNEL SEPARATION (dB) VDD=5V, Po=60mW SE, RL=32Ω FREQUENCY (Hz) FREQUENCY (Hz) Channel separation vs. frequency Channel separation vs. frequency CAP=10uF CAP=10uF CAP=1uF CAP=1uF PSRR (dB) VDD=5V, VRR=200mVrms, BTL RL=8Ω PSRR (dB) VDD=5V, VRR=200mVrms, SE RL=32Ω FREQUENCY (Hz) FREQUENCY (Hz) PSRR vs. frequency PSRR vs. frequency REV 3 10/29 www.mosanalog.com MOSA MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control DAC inputs signal (Ta=25℃, sampling rate=4fs, fs= 44.1kHz, f=1kHz, PA is Power Down mode; unless otherwise specified) THD+N (%) THD+N (%) VDD=5V DAC VFS VDD=3.3V, VFS DAC VFS THD+N (%) VDD=2.4V, VFS DAC VFS FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) THD+N vs. frequency THD+N vs. frequency THD+N vs. frequency CAP=10uF CHANNEL SEPARATION (dB) CAP=1uF PSRR (dB) VDD=5V DAC VFS VDD=5V VRR=0.2Vrms SUPPLY VOLTAGE (V) FREQUENCY (Hz) Channel separation vs. supply voltage PSRR vs. frequency REV 3 11/29 www.mosanalog.com MOSA AUDIO TIMING AND FORMAT MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control The MS6821 accepts input serial data formats of 16-bit word length. Left and right data words are time multiplexed. The MSB must always be first. LEFT RIGHT tr tHB tf tLB tHW tSW WS BCK tcr LSB tSD MSB tHD DATA Audio data format (BCK, WS, DATA) Symbol Parameter VIL VIH Input LOW level Input HIGH level Input Clock Frequency Bit Rate Data Input Word Select Input Rise Time Fall Time Bit Clock Cycle Time Bit Clock High Time Bit Clock Low Time Data Set-up Time Data Hold Time to Bit Clock Word Select Hold Time Word Select Set-up Time Conditions Min 2 54 15 15 12 2 2 12 Typ - Max 0.8 18.4 18.4 384 12 12 - Unit V V MHz Mbits/s kHz ns ns ns ns ns ns ns ns ns f BCK BR fWS tr tf t Cr t HB t LB t SD t HD t HW t SW REV 3 12/29 www.mosanalog.com MOSA Right justified format WS MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control LEFT RIGHT BCK DATA 2 1 0 15 MSB 14 13 2 1 0 LSB 15 MSB 14 13 2 1 0 LSB Left justified format WS LEFT RIGHT BCK DATA 15 MSB 14 13 2 1 0 LSB 15 MSB 14 13 2 1 0 LSB 15 MSB I2S format WS LEFT RIGHT BCK 1 BCK 1 BCK DATA 15 MSB 14 13 2 1 0 LSB 15 MSB 14 13 2 1 0 LSB REV 3 13/29 www.mosanalog.com MOSA I2C BUS DESCRIPTION Start and Stop Conditions MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control A start condition is activated when the SCL is set to HIGH and SDA shifts from HIGH to LOW state. The stop condition is activated when SCL is set to HIGH and SDA shifts from LOW to HIGH state. Please refer to the timing diagram below. SCL SDA Start Stop SCL : Serial Clock Line, SDA : Serial Data Line Data Validity A data on the SDA line is considered valid and stable only when the SCL signal is in HIGH state. The HIGH and LOW states of the SDA line can only change when the SCL signal is LOW. Please refer to the figure below. SDA SCL Data line stable, Data valid Data change allowed Byte Format Every byte transmitted to the SDA line consists of 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transmitted first. Acknowledge During the Acknowledge clock pulse, the master (up) put a resistive HIGH level on the SDA line. The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during the Acknowledge clock pulse so that the SDA line is in a stable LOW state during this clock pulse. Please refer to the diagram below. SCL 1 2 3 7 8 9 SDA MSB Start Acknowledge The audio processor that has been addressed has to generate an Acknowledge after receiving each byte, otherwise, the SDA line will remain at the HIGH level during the ninth (9th) clock pulse. In this case, the master transmitter can generate the STOP information in order to abort the transfer. REV 3 14/29 www.mosanalog.com MOSA Timing of SDA and SCL Bus Lines SDA tf SCL MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control tLOW tr tSU;DAT tf tHD;STA tSP tr tBUF S tHD;STA tHD;DAT tHIGH tSU;STA Sr tSU;STO P S Standard Mode Symbol fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tr tf tSU:STO tBUF Cb VnL VnH Parameter Min 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 - Max 100 3.45 1000 300 400 - Unit kHz us us us us us ns ns ns us us pF V V SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time: For I2C-bus devices Data-set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START condition Capacitive load for each bus line Noise margin at the LOW level for each connected device (including 0.1VDD hysteresis) Noise margin at the HIGH level for each connected device (including 0.2VDD hysteresis) REV 3 15/29 www.mosanalog.com MOSA BUS INTERFACE MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control Data are transmitted to and from the MCU to the MS6821 via the SDA and SCL. The SDA and SCL make up the BUS interface. It should be noted that pull-up resistors must be connected to the positive supply voltage. VDD Rp Rp Pull up resistors SDA (Serial Data Line) SCL (Serial Clock Line) MCU MS6821 I2C interface protocol The format consists of the following: ‧A START condition ‧A chip address byte including the chip address. (7bits) ‧The 8th bit of the byte must be “0”.(write=0, read=1) ‧The chip must always acknowledge the end of each transmitted byte. ‧A data sequence (N-bytes + Acknowledge) ‧A STOP condition SDA SCL S START CONDITION 1-7 8 9 1-7 8 9 1-7 8 9 P ADDRESS R/W ACK DATA ACK DATA ACK STOP CONDITION I2C chip address 88H 1 0 0 0 1 0 0 0 W 7 bits address REV 3 16/29 www.mosanalog.com MOSA I2C data bytes description MSB 0 0 1 1 1 1 0 1 0 0 1 1 B2 B2 0 1 0 1 B1 B1 G2 G2 DAC PD S/B MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control LSB B0 B0 G1 G1 RPD MixL Function L-ch, Attenuation and Mute R-ch, Attenuation and Mute L-ch, Input Gain and line Selection R-ch, Input Gain and line Selection Power Down Mode Output mode (SE/BTL), Mixer control and Audio format A2 A2 G0 G0 LPD MixR A1 A1 S1 S1 PDPR AF1 A0 A0 S0 S0 CAP PD AF0 Where Ax = 1.25dB/step; Bx = 10dB/step; Gx = 3dB/step Attenuation and Mute MSB 0 0 0 1 B2 B1 B0 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 A1 0 0 1 1 0 0 1 1 LSB A0 0 1 0 1 0 1 0 1 Function L-ch, Attenuation and Mute R-ch, Attenuation and Mute 0 dB -1.25 dB -2.5 dB -3.75 dB -5 dB -6.25 dB -7.5 dB -8.75 dB 0 dB -10 dB -20 dB -30 dB -40 dB -50 dB -60 dB -70 dB Mute 1 1 1 1 Initial state: Both L-ch and R-ch are mute-on. REV 3 17/29 www.mosanalog.com MOSA Input Selector and Input Gain MSB 1 1 0 0 0 1 G2 G1 G0 MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control LSB S1 0 0 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 S0 0 1 0 1 Function L-ch, Input Gain and line Selection R-ch, Input Gain and line Selection Line 1 (L-ch or R-ch) Line 2 (L-ch or R-ch) Line 3 (L-ch or R-ch) Line 4 (L-ch or R-ch) 0 dB 3 dB 6 dB 9 dB 12 dB 15 dB 18 dB 21 dB 1 1 1 Initial state: L-ch1, R-ch1, Input gain is 0dB. Power Down Mode MSB 1 1 0 DAC PD 0 1 0 1 0 1 0 1 0 1 RPD LSB CAP LPD PDPR PD Function Power mode selection and power management DAC is active mode DAC is power down mode R-ch PA output is active mode R-ch PA output is power down mode L-ch PA output is active mode L-ch PA output is power down mode Disable preparation for power off Enable preparation for power off Set the voltage of CAP to middle of supply voltage Pull down CAP pin to ground Initial state: All are the power down modes. Enable the power down preparation before the chip will be shut down. REV 3 18/29 www.mosanalog.com MOSA MSB 1 1 1 S/B MixL MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control Output mode (SE/BTL), Mixer control and Audio format LSB MixR AF1 AF0 Function Output mode, mixer control and audio format Output mode is BTL Output mode is SE 0 1 0 1 0 1 0 1 0 0 0 1 L-ch of input selector is the only signal Mix L-ch of input selector and L-ch of DAC R-ch of input selector is the only signal Mix R-ch of input selector and R-ch of DAC Right justified format Left justified format I2S format 1 1 Initial state: Output mode is BTL mode, unmixed mode and Right justified format I2C Initial code and status MSB 0 0 1 1 1 1 0 1 0 0 1 1 1 1 0 1 0 1 1 1 0 0 1 0 LSB 1 1 0 0 1 0 Function L-ch, Attenuation and Mute R-ch, Attenuation and Mute L-ch, Input Gain and line Selection R-ch, Input Gain and line Selection Power Down Mode Output mode (SE/BTL), Mixer control and Audio format Initial status Mute On Mute On Line1, 0dB Line1, 0dB All devices power down BTL, Unmixed, Right justified 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0 0 1 0 REV 3 19/29 www.mosanalog.com MOSA I2C CODE EXAMPLE Input selector and input gain MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control Set left channel to be line-4 and input gain to be 3dB. Set right channel to be line-4 and input gain to be 3dB. Gain Start MS6821 Address ACK 1 0 0 0 0 1 1 1 ACK 1 0 1 0 0 1 Line 1 1 ACK Stop L-ch = Line4, G = 3dB R-ch = Line4, G = 3dB The left and right input channel are independent. Volume control Set left channel to be -15dB and right channel to be 30dB. Gain Start MS6821 Address ACK 1 0 0 0 0 1 1 1 ACK 1 0 1 0 0 1 Line 1 1 ACK Stop L-ch = Line4, G = 3dB R-ch = Line4, G = 3dB Power down mode Set built-in DAC to be power down mode. DACPD Start MS6821 Address ACK 1 1 0 1 0 0 0 0 ACK Stop DAC power down Output mode, mixer control and audio format Set output mode to be SE mode, audio format is I2S, and both input channel to be mixed. Output mode Start MS6821 Address ACK 1 1 1 1 Mixer 1 1 0 1 Audio format ACK Stop SE mode, All mix, I2S REV 3 20/29 www.mosanalog.com MOSA OPERATION PROCEDURE MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control The sequence of operation: power on→ activating → power down → activating → power off. The basic flowcharts are as follows: For HP mode and HP/BTL mode REV 3 21/29 www.mosanalog.com MOSA For BTL mode only Power On MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control Activating Power Down (Shut Down) Power Off All the Digital Interface Signals Pull Low I2C pull low Audio inputs pull low (BCK, WS, DATA) VDD = GND Setting Input Gain Is Fixed [ Input Gain ] Code: Lch 100xxx00 Rch 101xxx00 Volume Down To Mute Input Channels Mute On [ Attenuation and Mute ] Code: Lch 00111111 (3Fh) Rch 01111111 (7Fh) Volume Down To Mute Input Channels Mute On [ Attenuation and Mute ] Code: Lch 00111111 (3Fh) Rch 01111111 (7Fh) Disable Power Down Power On VDD = Supply voltage Pull Down CAP Pin To Ground [ Power Down Mode ] Code: 11000000 (C0h) Wait 0.5 sec [ Power Down Mode ] Code: 11000001 (C1h) Wait 0.1 sec Pull Down CAP Pin To Ground [ Power Down Mode ] Code: 11000001 (C1h) Wait 0.1 sec Default Status [Attenuation & Mute] Mute on (max attenuation) [ Input Selector & Input Gain ] L-ch1, R-ch1 0dB [ Power Down Mode ] All power down status [ Output Mode & Mixer & Format ] BTL mode Inputs not mixed with DAC signal RJF format Keep All The Digital Interface Signals Unchanged All the Digital Interface Signals Pull Low I2C pull low Audio inputs pull low (BCK, WS, DATA) Mute Off And Volume Up/Down Step By Step [ Attenuation and Mute ] Code: Lch 00xxxxxx Rch 01xxxxxx Power Down All The Devices [ Power Down Mode ] Code: 11011111 (DFh) Power Down All The Devices [ Power Down Mode ] Code: 11011111 (DFh) Power Off Disconnect VDD VDD will be fell down to 0V REV 3 22/29 www.mosanalog.com MOSA APPLICATION INFORMATION A base application circuit MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control MCU HP_sense 100k VDD 100k 10uF 10uF 10uF 10uF RIN1 RIN2 RIN3 RIN4 Input selector & Gain control 1uF Attenuation & Mute Mixer -1 OUTR100uF 1k -1 OUTR+ Attenuation & Mute RL 8Ω Headphone Jack 10uF 10uF 10uF 10uF LIN1 LIN2 LIN3 LIN4 BCK Mixer -1 OUTL100uF 1k -1 16-bit DAC OUTL+ Audio Decoder WS DATA RL 8Ω Supply VDD Vss 2.4 ~ 6.5V 1uF Supply 0.1uF CAP 1uF DACR DACL SCL I2C Interface SDA Power Amplifier Supply PVDDL PVSSL PVDDR PVSSR 1uF 1uF MCU 2.4 ~ 6.5V Power Amplifier Supply MCU HP_sense 100k VDD 100k 10uF 10uF 10uF 10uF RIN1 RIN2 RIN3 RIN4 Input selector & Gain control 1uF Attenuation & Mute Mixer off -1 OUTR- 100uF 1k -1 10uF 10uF 10uF 10uF OUTR+ RL 8Ω Headphone Jack LIN1 LIN2 LIN3 LIN4 BCK Attenuation & Mute Mixer off -1 OUTL- 100uF 1k -1 16-bit DAC Audio Decoder WS DATA OUTL+ RL 8Ω Supply VDD Vss 2.4 ~ 6.5V 1uF Supply 0.1uF 10nF 10nF I2C Interface DACL 1k Power Amplifier Supply PVDDL PVSSL PVDDR PVSSR 1uF 1uF CAP 1uF DACR 1k SCL SDA MCU 2.4 ~ 6.5V Power Amplifier Supply REV 3 23/29 www.mosanalog.com MOSA MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control Output mode operation -- SE mode and BTL mode The output mode has two modes, SE mode and BTL mode. The mode is selected by I2C code via a MCU. In BTL mode, the outputs of A1(B1) and A2(B2) are then used to drive the bridged-tied load A1 -1 A2 -1 B1 -1 B2 -1 OUTL+ OUTLRL 4Ω / 8Ω OUTR+ OUTRRL 4Ω / 8Ω I2C Interface SCL SDA In the SE mode, the amplifiers A2 and B2 are shutdown, and then the amplifiers will be a high output impedance state. A1 -1 A2 -1 Shutdown B1 -1 B2 -1 Shutdown OUTLOUTR- 100uF 1k Headphone Jack RL 16Ω / 32Ω 100uF 1k I2 C Interface SCL SDA Headphone sense The output mode is SE or BTL that is decided by a headphone. It has to be set SE mode when a headphone is plug-in status. The output mode is selected by I2C command code by a MCU. Please note that the MS6821 don’t detect a headphone automatically. Thus a detect function is executed via a MCU. An operation diagram is as follows: The HP_sense pin is high when a headphone is plug-in. The HP_sense pin is low when a headphone is not plug-in. REV 3 24/29 www.mosanalog.com MOSA EXTERNAL DIMENSIONS SOP28 (300mil) D MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control Detail A EH h x45 C A e B A1 0.25 mm θ Detail A L Symbol A A1 B C e E H L D h θ Dimension in mm Min 2.35 0.10 0.33 0.23 7.40 10.00 0.40 17.70 0.25 0 o Dimension in inch Min 0.0926 0.0040 0.013 0.0091 0.2914 0.394 0.016 0.6969 0.010 0 o Max 2.65 0.30 0.51 0.32 7.60 10.65 1.27 18.10 0.75 8 o Max 0.1043 0.0118 0.020 0.0125 0.2992 0.419 0.050 0.7125 0.029 8 o 1.27 BASIC 0.050 BASIC REV 3 25/29 www.mosanalog.com MOSA TSSOP28 (Thermal Pad) MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control D D2 Detail A E2 E1 E C A2 A θ A1 B L L1 e y Symbol A A1 A2 b C D D2 E E1 E2 Dimension in mm Min 0.00 0.80 0.19 0.09 9.60 3.70 6.20 4.30 2.70 0.45 0.90 0o - Dimension in inches Min 0.000 0.031 0.007 0.004 0.378 0.146 0.244 0.169 0.106 0.018 0.035 0o - Nom 1.00 9.70 3.80 6.40 4.40 2.80 0.65 0.60 1.00 - Max 1.15 0.10 1.05 0.30 0.20 9.80 3.90 6.60 4.50 2.90 0.75 1.10 8o 0.10 Nom 0.039 0.382 0.150 0.252 0.173 0.110 0.026 0.024 0.039 - Max 0.045 0.004 0.041 0.012 0.008 0.386 0.154 0.260 0.177 0.114 0.030 0.043 8o 0.004 e L L1 θ y REV 3 26/29 www.mosanalog.com MOSA DEMO BOARD MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control 1 2 3 8 7 4 5 6 Function description Label 1: Supply Input Supply voltage range is 2.4V to 6.5V. Label 2: Headphone Jack Used 3.5mm diameter of headphone with 32ohm Label 3: DAC output Connected to a post-power-amplifier, as active speaker. In addition, using volume control for DAC, this output can connected to input section (label 6) as feedback. Label 4: Speaker Output Connected to speaker with 8ohm or 4 ohm Label 5: Digital Signal Input Connected to digital audio formats as I2S, Right Justified and Left Justified. Label 6: Signal Input There are four stereo inputs in the section. Please input stereo audio signal, as music or sine wave. Label 7: Reset All I/O pins are reset to default values. Label 8: LED Indicator The LEDs indicate the chip status and IR received status. It keeps on a light state when the MS6821 is active. The other hand, keeps on a dark state when the MS6821 is power-off. It is red-dark blink once when the MCU has received the function code correctly. REV 3 27/29 www.mosanalog.com MOSA MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control SE mode and BTL mode operation The headphone controls operational mode. System enters SE mode when headphone jack is empty. When a set of headphone plugged into the jack, the system switched to BTL mode. IR Controller Power ON/OFF : The power key. Press the key once to set power-on or power-off for MS6821. IN1~IN4 : Analog input channel. Press the key once to select input channel. The default state is IN1. VOL+, VOL- : The volume control keys. The volume control in 1.25dB/step as the switch is pressed once, the range is –77.5dB to 0dB. The default value is -20dB. Gain+, Gain- : The gain control keys. The gain control in 3dB/step as the switch is pressed once, the range is 0dB to 21dB. The initial value is 0dB. Mute : The mute key Press the key once to set mute-on or mute-off. The default state is mute-off. PD/Active : The power down key. Press the key once to set power-down or activation for MS6821. Mix_LR ON/OFF : The mixing DAC signal keys. Mix_L ON, mixed the left channel of DAC with the left channel of input signal. Mix_R OFF, unmixed the right channel of DAC with the right channel of input signal. I2S, LJF, RJF: The digital input format keys. There are three formats can be selected that is I2S, Left justified and Right justified. REV 3 28/29 www.mosanalog.com MOSA Circuit J1 1 2 DVDD DVDD + C3 0.1u + C4 1u R3 10K C6 20P 2 + MS6821 4 Stereo inputs / 2W PA output integrated Audio DAC and Volume Control R1 S1 R2 10K IR_IN IN1 D1 IN2 D2 IN3 D3 IN4 D4 220 C1 + 47u Q1 1 2 3 VS GND IR IR + C5 470P + C2 10u U1 1 2 RX 3 TX 4 5 IR_IN 6 SCL 7 SDA 8 HP_IN 9 10 3 Q2 NMOS 2 1 RST P3.0 P3.1 XTAL2 XTAL1 P3.2 P3.3 P3.4 P3.5 GND Vcc P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P3.7 20 19 18 17 16 15 14 13 12 11 J13 1 2 3 LCD W2 JUMP DGND 1 2 AVCC AVCC + C8 0.1u J3 1 2 3 4 DAC_IN J4 R L G R L G R L G R L G 1 2 3 1 2 3 1 2 3 1 2 3 C11 R10 R11 1K 1K C13 C14 R12 R13 1K 1K C15 C16 R14 R15 1K 1K C20 C22 R16 R17 1K 1K C23 R5 R6 R7 + C9 1u 1K 1K 1K C10 1u + RX TX RST R18 R19 R20 R21 1K 1K 1K 1K Y1 24M C7 20P + 1 DGND J2 AT89C4051 C12 1u + R22 100K R4 100K 10u + 10u + 10u + SP1 SPK_R C19 100u + + C21 1u + R8 J10 1K 1 2 3 DAC_OUT 10u + 10u + 10u + 10u + 10u + IN1 J5 IN2 J6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 U2 WS BCK REF R1 R2 R3 R4 Vss PVDDR -OUTR +OUTR GND PVSSR DAC_R MS6821 DATA SCL SDA L1 L2 L3 L4 VDD PVDDL -OUTL +OUTL GND PVSSL DAC_L 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SCL SDA AVCC SP2 SPK_L + C18 100u + C17 1u IN3 J8 1 2 3 4 5 6 IN4 C24 10u C25 10u + R9 1K HP-IN HP-R R HP-L L G HEADPHONE J9 1 2 3 OUT W1 Jumper AGND AGND DGND J12 1 R 2 L 3 G DAC_OUT REV 3 29/29 www.mosanalog.com