V29LC51002

MOSEL VITELIC V29LC51002 2 MEGABIT (262,144 x 8 BIT) 5 VOLT CMOS FLASH MEMORY Description PRELIMINARY Features s s s s s 256Kx8-bit Organization Address Access Time: 90 ns Single 5V ± 10% Power Supply Sector Erase Mode Operation 512 bytes per Sector, 512 Sectors – Sector-Erase Cycle Time: 10ms (Max) – Byte-Write Cycle Time: 30µs (Max) Minimum 1,000 Erase-Program Cycles Low power dissipation – Active Read Current: 20mA (Typ) – Active Program Current: 30mA (Typ) – Standby Current: 100µA (Max) Low VCC Program Inhibit Below 3.5V CMOS and TTL Interface Packages: – 32-pin Plastic DIP – 32-pin PLCC s s The V29LC51002 is a high speed 262,144 x 8 bit CMOS flash memory. Writing or erasing the device is done with a single 5 Volt power supply. The device has separate chip enable CE, write enable WE, and output enable OE controls to eliminate bus contention. The V29LC51002 features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. The device also supports full chip erase. s s s Device Usage Chart Operating Temperature Range 0°C to 70°C Package Outline P • J • Access Time (ns) 90 • Temperature Mark Blank V29LC51002 Rev. 0.5 October 2000 1 MOSEL VITELIC V 29 LC 51 002 – V29LC51002 OPERATING VOLTAGE 51: 5V DEVICE 90: 90ns SPEED PKG. P = PDIP J = PLCC C51002-01 Pin Configurations VCC WE A12 A15 A16 NC N/C A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 32-Pin PDIP 26 Top View 25 24 23 22 21 20 19 18 17 51002-02 VCC WE A17 A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A17 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A14 A13 A8 A9 A11 OE A10 CE I/O7 32 Pin PLCC Top View I/O1 I/O2 I/O3 I/O4 I/O5 GND I/O6 51002-03 Pin Names A0–A17 I/O0–I/O7 CE OE WE VCC GND NC Address Inputs Data Input/Output Chip Enable Output Enable Write Enable 5V ± 10% Power Supply Ground No Connect V29LC51002 Rev. 0.5 October 2000 2 MOSEL VITELIC Functional Block Diagram 2,097,152 Bit Memory Cell Array V29LC51002 X-Decoder A0–A17 Address buffer & latches Y-Decoder CE OE WE Control Logic I/O Buffer & Data Latches I/O0–I/O7 51002-07 Capacitance (1,2) Symbol CIN COUT CIN2 Parameter Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ. 6 8 8 Max. 8 12 10 Units pF pF pF NOTE: 1. Capacitance is sampled and not 100% tested. 2. TA = 25°C, VCC = 5V ± 10%, f = 1 MHz. Latch Up Characteristics(1) Parameter Input Voltage with Respect to GND on A9, OE Input Voltage with Respect to GND on I/O, address or control pins VCC Current NOTE: 1. Includes all pins except VCC. Test conditions: VCC = 5V, one pin at a time. Min. -1 -1 -100 Max. +13 VCC + 1 +100 Unit V V mA AC Test Load +5.0 V IN3064 or Equivalent Device Under Test IN3064 or Equivalent CL = 100 pF 6.2 kΩ IN3064 or Equivalent IN3064 or Equivalent 51002-08 2.7 kΩ V29LC51002 Rev. 0.5 October 2000 3 MOSEL VITELIC Absolute Maximum Ratings(1) Symbol VIN VIN VCC TSTG TOPR IOUT V29LC51002 Parameter Input Voltage (input or I/O pins) Input Voltage (A9 pin, OE) Power Supply Voltage Storage Temerpature (Plastic) Operating Temperature Short Circuit Current(2) Commercial -2 to +7 -2 to +13 -0.5 to +5.5 -65 to +125 0 to +70 200 (Max.) Unit V V V °C °C mA NOTE: 1. Stress greater than those listed unders “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. No more than one output maybe shorted at a time and not exceeding one second long. DC Electrical Characteristics (over the commercial operating range) Parameter Name VIL VIH IIL IOL VOL VOH ICC1 Parameter Input LOW Voltage Input HIGH Voltage Input Leakage Current Output Leakage Current Output LOW Voltage Output HIGH Voltage Read Current Test Conditions VCC = VCC Min. VCC = VCC Max. VIN = GND to VCC, VCC = VCC Max. VOUT = GND to VCC, VCC = VCC Max. VCC = VCC Min., IOL = 2.1mA VCC = VCC Min, IOH = -400µA CE = OE = VIL, WE = VIH, all I/Os open, Address input = VIL/VIH, at f = 1/tRC Min., VCC = VCC Max. CE = WE = VIL, OE = VIH, VCC = VCC Max. CE = OE = WE = VIH, VCC = VCC Max. CE = OE = WE = VCC – 0.3V, VCC = VCC Max. CE = OE = VIL, WE = VIH CE = OE = VIL, WE = VIH, A9 = VH Max. Min. — 2 — — — 2.4 — Max. 0.8 — ±1 ±10 0.4 — 40 Unit V V µA µA V V mA ICC2 ISB ISB1 VH IH Write Current TTL Standby Current CMOS Standby Current Device ID Voltage for A9 Device ID Current for A9 — — — 11.5 — 50 2 100 12.5 50 mA mA µA V µA V29LC51002 Rev. 0.5 October 2000 4 MOSEL VITELIC AC Electrical Characteristics (over all temperature ranges) Read Cycle Parameter Name tRC tAA tACS tOE tCLZ tOLZ tDF tOH V29LC51002 -90 Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time CE Low to Output Active OE Low to Output Active OE or CE High to Output in High Z Output Hold from Address Change Min. 90 — — — 0 0 0 0 Max. — 90 90 45 — — 40 — Unit ns ns ns ns ns ns ns ns Program (Erase/Program) Cycle Parameter Name Parameter tWC tAS tAH tCS tCH tOES tOEH tWP tWPH tDS tDH tWHWH1 tWHWH2 tWHWH3 Write Cycle Time Address Setup Time Address Hold Time CE Setup Time CE Hold Time OE Setup Time OE High Hold Time WE Pulse Width WE Pulse Width High Data Setup Time Data Hold Time Programming Cycle Sector Erase Cycle Chip Erase Cycle -90 Min. 90 0 45 0 0 0 0 45 30 30 0 — — — Typ. — — — — — — — — — — — — — 3 Max. — — — — — — — — — — — 30 10 — Unit ns ns ns ns ns ns ns ns ns ns ns µs ms sec V29LC51002 Rev. 0.5 October 2000 5 MOSEL VITELIC Waveforms of Read Cycle tRC ADDRESS tAA CE tCE tOE OE tOLZ WE tCLZ I/O HIGH-Z tOH VALID DATA OUT tAA VALID DATA OUT tDF V29LC51002 HIGH-Z 51002-09 Waveforms of WE Controlled-Program Cycle 3rd bus cycle tWC tAS ADDRESS 5555H tCH CE PA tAH tRC OE tOES WE tCS tWPH tDS tDH I/O A0H PD(3) Valid Data tOE tDF tOH tWP tWHWH1 C51002-10 NOTES: 1. PA: The address of the memory location to be programmed. 2. PD: The data at the byte address to be programmed. V29LC51002 Rev. 0.5 October 2000 6 MOSEL VITELIC Waveforms of Erase Cycle(1) tWC ADDRESS 5555H tAS 2AAAH 5555H tAH CE 5555H 2AAAH V29LC51002 (5555H for Chip Erase) SA OE tWP WE tCS tDS tDH I/O AAH 55H 80H AAH 55H tWPH tWHWH 2 3 (10H for Chip Erase) 30H 51002-12 NOTES: 1. PA: The address of the memory location to be programmed. 2. PD: The data at the byte address to be programmed. 3. SA: The sector address for Sector Erase. V29LC51002 Rev. 0.5 October 2000 7 MOSEL VITELIC FUNCTIONAL DESCRIPTION Read Cycle A read cycle is performed by holding both CE and OE signals LOW. Data Out becomes valid only when these conditions are met. During a read cycle WE must be HIGH prior to CE and OE going LOW. WE must remain HIGH during the read operation for the read to complete (see Table 1). V29LC51002 512 512 • • • 512 V29LC51002 Output Disable Returning OE or CE HIGH, whichever occurs first will terminate the read operation and place the l/O pins in the HIGH-Z state. 512 00000H C51002-15 Standby The device will enter standby mode when the CE signal is HIGH. The l/O pins are placed in the HIGH-Z, independent of the OE input state. During the byte write cycle, addresses are latched on the falling edge of either CE o r WE, whichever is last. Data is latched on the rising edge of CE or WE, whichever is first. The byte write cycle can be CE controlled or WE controlled. Command Sequence The V29LC51002 does not provide the “reset” feature to return the chip to its normal state when an incomplete command sequence or an interruption has happened. In this case, normal operation (Read Mode) can be restored by issuing a “non-existent” command sequence, for example Address: 5555H, Data FFH. Sector Erase Cycle T he V29LC51002 features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. Sector erase operation is initiated by using a specific six-bus-cycle sequence: Two unlock program cycles, a setup command, two additional unlock program cycles, and the sector erase command (see Table 2). A sector must be first erased before it can be re-written. While in the internal erase mode, the device ignores any program attempt into the device. Sector erase is completed in 10ms max. The V29LC51002 is shipped fully erased (all bits = 1). Byte Write Cycle The V29LC51002 is programmed on a byte-bybyte basis. The byte write operation is initiated by using a specific four-bus-cycle sequence: two unlock program cycles, a program setup command and program data program cycles (see Table 2). Table 1. Operation Modes Decoding Decoding Mode Read Byte Write Standby Output Disable CE VIL VIL VIH VIL OE VIL VIH X VIH WE VIH VIL X VIH A0 A0 A0 X X A1 A1 A1 X X A9 A9 A9 X X I/O READ PD HIGH-Z HIGH-Z NOTES: 1. X = Don’t Care, VIH = HIGH, VIL = LOW, VH = 12.5V Max. 2. PD: The data at the byte address to be programmed. V29LC51002 Rev. 0.5 October 2000 8 MOSEL VITELIC Table 2. Command Codes First Bus Program Cycle Command Sequence Read Read Autoselect Address XXXXH 5555H 5555H Data F0H AAH AAH 2AAAH 2AAAH 55H 55H 5555H 5555H F0H 90H RA(1) 00H 01H Byte Program Chip Erase 5555H AAH 2AAAH 55H 5555H A0H PA RD(2) 40H(6) 82H(7) PD(4) Second Bus Program Cycle Address Data Third Bus Program Cycle Address Data Fourth Bus Program Cycle Address Data Fifth Bus Program Cycle Address Data V29LC51002 Six Bus Program Cycle Address Data 5555H AAH AAH 2AAAH 2AAAH 55H 55H 5555H 5555H 80H 80H 5555H 5555H AAH AAH 2AAAH 2AAAH 55H 55H 5555H SA(5) 10H 30H Sector Erase 5555H NOTES: 1. RA: Read Address 2. RD: Read Data 3. PA: The address of the memory location to be programmed. 4. PD: The data at the byte address to be programmed. 5. SA(5): Sector Address 6. 40H: Manufacturing ID 7. 82H: Device ID Chip Erase Cycle The V29LC51002 features a chip-erase operation. The chip erase operation is initiated by using a specific six-bus-cycle sequence: two unlock program cycles, a setup command, two additional unlock program cycles, and the chip erase command (see Table 2). The automatic erase begins on the rising edge of the last WE or CE pulse in the command sequence and is completed in 3 sec max. V29LC51002 Rev. 0.5 October 2000 9 MOSEL VITELIC Byte Program Algorithm Write Byte-Write Command Sequence V29LC51002 Chip/Sector Erase Algorithm Write Erase Command Sequence Add/Data 5555H/AAH Add/Data 5555H/AAH 2AAAH/55H Four Bus Cycle Sequence 5555H/A0H 2AAAH/55H 5555H/80H Six Bus Cycle Sequence PA/PD 5555H/AAH Time Out 30µS 2AAAH/55H Writing Complete 5555H/10H (Chip Erase) SA/30H (Sector Erase) Time Out for Sector or Chip Erase Erase Complete C51002-16 V29LC51002 Rev. 0.5 October 2000 10 MOSEL VITELIC Package Diagrams 32-pin Plastic DIP 1.660 MAX. 15° MAX V29LC51002 INDEX-1 EJECTOR MARK 0.545/0.555 INDEX-2 .600 TYP +.004 .010 – .0004 .050 MAX 0.210 MAX 0.120 MIN .100 TYP +.012 .047 – 0 +.006 .018 – .002 0.010 MIN .032 +.012 –0 32-pin PLCC 20 19 18 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 17 16 15 14 13 12 11 10 9 8 7 6 5 .550 ± .003 .590 ± .005 .045X45° .450 ± .003 .490 ± .005 .050 TYP .110 .136 ± .003 .046 ± .003 .025 30° .017 3° - 6° .420 ± .003 3° - 6° 3° - 6° V29LC51002 Rev. 0.5 October 2000 11 MOSEL VITELIC U.S.A. 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 WORLDWIDE OFFICES TAIWAN 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888 V29LC51002 UK & IRELAND SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516 SINGAPORE 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 HONG KONG 19 DAI FU STREET TAIPO INDUSTRIAL ESTATE TAIPO, NT, HONG KONG PHONE: 852-2666-3307 FAX: 852-2770-8011 JAPAN ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402 GERMANY (CONTINENTAL EUROPE & ISRAEL) BENZSTRASSE 32 71083 HERRENBERG GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22 U.S. SALES OFFICES NORTHWESTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 SOUTHWESTERN 302 N. EL CAMINO REAL #200 SAN CLEMENTE, CA 92672 PHONE: 949-361-7873 FAX: 949-361-7807 CENTRAL, NORTHEASTERN & SOUTHEASTERN 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 972-690-1402 FAX: 972-690-0341 © Copyright 2000, MOSEL VITELIC Inc. 10/00 Printed in U.S.A. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461