V43644Y04VCTG-10PC

MOSEL VITELIC V43644Y04V(C)TG-10PC 3.3 VOLT 4M x 64 HIGH PERFORMANCE 100 MHZ SDRAM UNBUFFERED SODIMM Description PRELIMINARY Features s JEDEC-standard 144 pin, Small-Outline, Dual in line Memory Module (SODIMM) s Serial Presence Detect with E2PROM s Nonbuffered s Fully Synchronous, All Signals Registered on Positive Edge of System Clock s Single +3.3V (± 0.3V) Power Supply s All Device Pins are LVTTL Compatible s 4096 Refresh Cycles every 64 ms s Self-Refresh Mode s Internal Pipelined Operation; Column Address can be changed every System Clock s Programmable Burst Lengths: 1, 2, 4, 8 or Full Page s Auto Precharge and Piecharge all Banks by A10 s Data Mask Function by DQM s Mode Register Set Programming s Programmable (CAS Latency: 2, 3 Clocks) The V43644Y04V(C)TG-10PC memory module is organized 4,194,304 x 64 bits in a 144 pin SODIMM. The 4M x 64 memory module uses 4 Mosel-Vitelic 4M x 16 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. Speed Grade -10PC 100 MHz) Part Number V43644Y04V(C)TG-10PC Configuration 4M x 64 4M x 16 4M x 16 1 59 61 143 Pin 2 on Backside Pin 144 on Backside V43644Y04V(C)TG-10PC Rev. 1.6 October 2000 1 MOSEL VITELIC Pin Configurations (Front Side/Back Side) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Front VSS VSS DQ0 DQ32 DQ1 DQ33 DQ2 DQ34 DQ3 DQ35 VDD VDD DQ4 DQ36 DQ5 DQ37 DQ6 DQ38 DQ7 DQ39 VSS VSS DQMB0 DQMB4 Pin 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Front DQMB1 DQMB5 VDD VDD A0 A3 A1 A4 A2 A5 VSS VSS DQ8 DQ40 DQ9 DQ41 DQ10 DQ42 DQ11 DQ43 VDD VDD DQ12 DQ44 Pin 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Front DQ13 DQ45 DQ14 DQ46 DQ15 DQ47 VSS VSS NC NC NC NC CLK0 CKE0 VDD VDD RAS CAS WE NC CS0 NC NC NC Pin 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Back NC CLK1 VSS VSS NC NC NC NC VDD VDD DQ16 DQ48 DQ17 DQ49 DQ18 DQ50 DQ19 DQ51 VSS VSS DQ20 DQ52 DQ21 DQ53 V43644Y04V(C)TG-10PC Pin 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Back DQ22 DQ54 DQ23 DQ55 VDD VDD A6 A7 A8 BA0 VSS VSS A9 BA1 A10 A11 VDD VDD DQMB2 DQMB6 DQMB3 DQMB7 VSS VSS Pin 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Back DQ24 DQ56 DQ25 DQ57 DQ26 DQ58 DQ27 DQ59 VDD VDD DQ28 DQ60 DQ29 DQ61 DQ30 DQ62 DQ31 DQ63 VSS VSS SDA SCL VDD VDD Note: 1. RAS, CAS, WE CASx, CSx are active low signals. Pin Names A0–A11, BA0, BA1 DQ0–DQ63 RAS CAS WE CS0 DQMB0–DQMB7 CKE0 CLK0–CLK1 SDA SCL VDD VSS NC Address, Bank Select Data Inputs/Outputs Row Address Strobes Column Address Strobes Write Enable Chip Select Output Enable Clock Enable Clock Serial Input/Output Serial Clock Power Supply Ground No Connect (Open) V43644Y04V(C)TG-10PC Rev. 1.6 October 2000 2 MOSEL VITELIC Part Number Information V MOSEL-VITELIC MANUFACTURED SDRAM V43644Y04V(C)TG-10PC 4 3 64 4 Y 0 4 V C T G - 10PC -10PC PC100 2-2-2 GOLD TSOP COMPONENT REVISION LEVEL BLANK = B REV. C = C REV. WIDTH DEPTH 144 PIN UNBUFFERED SODIMM x16 COMPONENT LVTTL 4 BANKS REFRESH RATE 4K V43644Y04V(C)TG-10PC-02 3.3V Block Diagram CS0 WE RAS CAS DQMB0 UDQMB DQ0–7 DQ32–39 UDQMB DQMB4 U0 DQMB1 LDQMB DQ8–15 DQ40–47 U2 LDQMB DQMB5 DQMB2 UDQMB DQ16–23 DQ48–54 UDQMB DQMB6 U1 DQMB3 LDQMB DQ24–31 DQ55–63 U3 LDQMB DQMB7 VDD VSS A0–A11, BA0, BA1 CKE0 U0–U3 CLK0 U0–U3 U0–U3 CLK1 10Ω 10Ω 10Ω 10 pF SPD SCL A0 A1 A2 SDA U0–U3 U0–U3 V43644YO4V(C)TG-10PC-03 V43644Y04V(C)TG-10PC Rev. 1.6 October 2000 3 MOSEL VITELIC Serial Presence Detect Information A serial presence detect storage device – E PROM – is assembled onto the module. Information about the module configuration, speed, etc. is 2 V43644Y04V(C)TG-10PC written into the E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus) SPD-Table for -10 PC modules: Hex Value Byte Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function Described Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for x16 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (continued) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access Time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM Data Width Minimum Clock Delay from Back to Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Minimum Clock Cycle Time at CAS Latency = 2 Maximum Data Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL = 1 Minimum Row Precharge Time tRP Minimum Row Active to Row Active Delay tRRD Minimum RAS to CAS Delay tRCD SPD Entry Value 128 256 SDRAM 12 8 1 64 0 LVTTL 10.0 ns 6.0 ns none Self-Refresh, 15.6µs x16 n/a / x8 tccd = 1 CLK 1, 2, 4, 8 & full Page 4 CL = 2 & 3 CS Latency = 0 WL = 0 Non Buffered/Non Reg. Vcc tol ± 10% 10.0 ns 6.0 ns Not Supported Not Supported 20 ns 16 ns 20 ns 100 MHz -10PC 80 08 04 0C 08 01 40 00 01 A0 60 00 80 10 00 01 16 17 18 19 20 21 22 23 24 25 26 27 28 29 8F 04 06 01 01 00 0E A0 60 00 00 14 10 14 V43644Y04V(C)TG-10PC Rev. 1.6 October 2000 4 MOSEL VITELIC SPD-Table for -10 PC modules: (Continued) V43644Y04V(C)TG-10PC Hex Value Byte Number 30 31 32 33 34 35 36-61 62 63 64-125 Function Described Minimum RAS Pulse Width tRAS Module Bank Density (Per Bank) SDRAM Input Setup Time SDRAM Input Hold Time SDRAM Data Input Setup Time SDRAM Data Input Hold Time Superset Information (May be used in Future) SPD Revision Checksum for Bytes 0 - 62 Manufacturers’s Information (Optional) (FFh if not used) Max. Frequency Specification 100 MHz Support Details Unused Storage Location SPD Entry Value 45 ns 32 MByte 2.0 ns 1 ns 2.0 ns 1 ns 100 MHz -10PC 2D 08 20 10 20 10 00 Revision 1 12 FD XX 126 127 128+ 100 MHz 64 AF 00 Absolute Maximum Ratings Parameter Voltage on VDD Supply Relative to VSS Voltage on Input Relative to VSS Operating Temperature Storage Temperature Power Dissipation Max. -1 to 4.6 -1 to 4.6 0 to +70 -55 to 125 4 Units V V °C °C W TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V Limit Values Symbol VIH VIL VOH VOL II(L) IO(L) DC Characteristics Parameter Input High Voltage Input Low Voltage Output High Voltage (IOUT = –2.0 mA) Output Low Voltage (IOUT = 2.0 mA) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) Output leakage current (DQ is disabled, 0V < VOUT < VCC) Min. 2.0 –0.5 2.4 — –20 Max. VCC+0.3 0.8 — 0.4 20 Unit V V V V µA µA –20 20 V43644Y04V(C)TG-10PC Rev. 1.6 October 2000 5 MOSEL VITELIC Capacitance Symbol CI1 CI2 CICL CI3 CI4 CSC CIO V43644Y04V(C)TG-10PC TA = 0°C to 70°C; VDD = 3.3V ± 0.3V, f = 1 MHz Parameter Input Capacitance (A0 to A11, RAS, CAS, WE) Input Capacitance (CS0) Input Capacitance (CLK0-CLK1) Input Capacitance (CKE0) Input Capacitance (DQMB0-DQMB7) Input Capacitance (SCL, SA0-2) Input/Output Capacitance Limit Values 18 18 25 18 8 8 10 Unit pF pF pF pF pF pF pF Standby and Refresh Currents1 TA = 0°C to 70°C, VCC = 3.3V ± 0.3V Symbol Parameter ICC1 Operating Current Test Conditions Burst length = 4, CL = 3 tRC> = tRC(min), tCK> = tCK(min), IO = 0 mA 2 Bank Interleave Operation CKE< = VIL(max), tCK> = tCK(min) CKE> = VIH(min), tCK> = tCK(min), Input changed once in 3 cycles 4M x 64 440 Unit mA Note 1,2 ICC2P ICC2N Precharged Standby Current in Power Down Mode Precharged Standby Current in Non-Power Down Mode 16 mA 85 mA CS = High ICC3P ICC3N ICC4 Active Standby Current in Power Down Mode Active Standby Current in Non-Power Down Mode Burst Operating Current CKE< = VIL(max), tCK> = tCK(min) CKE> = VIH(min), tCK> = tCK(min), Input changed one time Burst length = Full Page, tRC = Infinite, CL = 3, tCK> = tCK(min), IO = 0 mA 2 Banks Activated tRC>= tRC(min) CKE =