V436516R04VATG-10PC

MOSEL VITELIC V436516R04VATG-10PC 3.3 VOLT 16M x 64 (using 8M x 16) PC100 UNBUFFERED SDRAM MODULE Description PRELIMINARY Features s 168 Pin Unbuffered 16, 777, 216 x 64 bit Oganization SDRAM DIMM s Utilizes High Performance 128 Mbit, 8M x 16 SDRAM in TSOPII-54 Packages s Fully PC Board Layout Compatible to INTEL’S Rev 1.0 Module Specification s Single +3.3V (± 0.3V) Power Supply s Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) s Auto Refresh (CBR) and Self Refresh s All Inputs, Outputs are LVTTL Compatible s 4096 Refresh Cycles every 64 ms s Serial Present Detect (SPD) s SDRAM Performance The V436516R04VATG-10PC memory module is organized 16, 777, 216 x 64 bits in a 168 pin dual in line memory module (DIMM). The 16M x 64 memory module uses 8 Mosel-Vitelic 8M x 16 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. Key Component Timing Parameters tCK tAC tAC Clock Frequency (max.) Clock Access Time CAS Latency = 3 Latency = 2 -8PC 125 6 Units MHz ns 6 ns s Module Frequency vs AC Parameter Frequency V436516R04VATG-10PC 100 MHz (PC) CL (CAS Latency) 3 2 tRCD 2 2 tRP 2 2 tRC 7 7 Unit CLK CLK V436516R04VATG-10PC Rev. 1.1 February 2001 1 MOSEL VITELIC Pin Configurations (Front Side/Back Side) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front VSS I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 I/O9 VSS I/O10 I/O11 I/O12 I/O13 I/O14 VCC I/O15 I/O16 CBO* CB1* VSS NC NC VCC WE DQM0 Pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Front DQM1 CS0 DU VSS A0 A2 A4 A6 A8 A10(AP) BA1 VCC VCC CLK0 VSS DU CS2 DQM2 DQM3 DU VCC NC NC CB2* CB3* VSS I/O17 I/O18 Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front I/O19 I/O20 VCC I/O21 NC DU CKE1 VSS I/O22 I/O23 I/O24 VSS I/O25 I/O26 I/O27 I/O28 VCC I/O29 I/O30 I/O31 I/O32 VSS CLK2 NC WP SDA SCL VCC Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS I/O33 I/O34 I/O35 I/O36 VCC I/O37 I/O38 I/O39 I/O40 I/O41 VSS I/O42 I/O43 I/O44 I/O45 I/O46 VCC I/O47 I/O48 CB4* CB5* VSS NC NC VCC CAS DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 V436516R04VATG-10PC Back DQM5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VCC CLK1 NC VSS CKE0 CS3 DQM6 DQM7 DU VCC NC NC CB6* CB7* VSS I/O49 I/O50 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back I/O51 I/O52 VCC I/O53 NC DU NC VSS I/O54 I/O55 I/O56 VSS I/O57 I/O58 I/O59 I/O60 VCC I/O61 I/O62 I/O63 I/O64 VSS CLK3 NC SA0 SA1 SA2 VCC Notes: * These pins are not used in this module. Pin Names A0–A11 I/O1–I/O64 RAS CAS WE BA0, BA1 CKE0, CKE1 CS0–CS3 CLK0–CLK3 DQM0–DQM7 VCC VSS SCL Address Inputs Data Inputs/Outputs Row Address Strobe Column Address Strobe Read/Write Input Bank Selects Clock Enable Chip Select Clock Input Data Mask Power (+3.3 Volts) Ground Clock for Presence Detect SDA SA0–A2 CB0–CB7 NC DU Serial Data OUT for Presence Detect Serial Data IN for Presence Detect Check Bits (x72 Organization) No Connection Don’t Use V436516R04VATG-10PC Rev. 1.1 February 2001 2 MOSEL VITELIC Part Number Information V MOSEL-VITELIC MANUFACTURED SDRAM V436516R04VATG-10PC 4 3 65 16 R 0 4 V A T G - 10PC 100 MHz (PC 100 2-2-2) GOLD TSOP 3.3V WIDTH DEPTH 168 PIN UNBUFFERED DIMM X 16 COMPONENT LVTTL 4 BANKS REFRESH RATE 4K A = A VERSION Functional Block Diagram CS1 CS0 DQM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS3 CS2 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 • LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 • CS LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 • DQM4 CS LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 • DQM6 CS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 • LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Serial PD VDD 10KΩ CKE1 • SDRAM U4 ~ U7 SCL SDA A0 A1 A2 • WP 47KΩ CS LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 • • LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS U0 U4 U2 U6 • LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 U1 U5 U3 U7 A0 ~ An, BA0 & 1 RAS CAS WE CKE0 10Ω SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U3 SA0 SA1 SA2 DQn VDD Vss • • • • Every DQpin of SDRAM CLK0/1/2/3 Two 0.1uF Capacitors per each SDRAM 10Ω 15pF • • U0/U4/U2/U6 U1/U5/U3/U7 To all SDRAMs V436516R04VATG-10PC Rev. 1.1 February 2001 3 MOSEL VITELIC Serial Presence Detect Information A serial presence detect storage device - is assembled onto the module. Information about the module configuration, speed, etc. is E2PROM V436516R04VATG-10PC written into the E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus) SPD-Table for PC100 modules: Hex Value Byte Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function Described Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for x16 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (continued) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access Time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM Data Width Minimum Clock Delay from Back to Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Minimum Clock Cycle Time at CAS Latency = 2 Maximum Data Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL = 1 Minimum Row Precharge Time Minimum Row Active to Row Active Delay tRRD Minimum RAS to CAS Delay tRCD Minimum RAS Pulse Width tRAS SPD Entry Value 128 256 SDRAM 12 9 2 64 0 LVTTL 10.0 ns 6.0 ns none Self-Refresh, 15.6µs x16 n/a / x8 tccd = 1 CLK 1, 2, 4, 8 4 CL = 3, 2 CS Latency = 0 WL = 0 Non Buffered/Non Reg. Vcc tol ± 10% 10.0 ns 6.0 ns Not Supported Not Supported 20 ns 16 ns 20 ns 45 ns 16Mx64 80 08 04 0C 09 02 40 00 01 A0 60 00 80 10 00 01 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0F 04 06 01 01 00 0E A0 60 00 00 14 10 14 2D V436516R04VATG-10PC Rev. 1.1 February 2001 4 MOSEL VITELIC SPD-Table for PC100 modules: (Continued) V436516R04VATG-10PC Hex Value Byte Number 31 32 33 34 35 62-61 62 63 64 65-71 72 73-90 91-92 93 94 95-98 99-125 126 127 128+ Function Described Module Bank Density (Per Bank) SDRAM Input Setup Time SDRAM Input Hold Time SDRAM Data Input Setup Time SDRAM Data Input Hold Time Superset Information (May be used in Future) SPD Revision Checksum for Bytes 0 - 62 Manufacturer’s JEDEC ID Code Manufacturer’s JEDEC ID Code (cont.) Manufacturing Location Module Part Number (ASCII) PCB Identification Code Assembly Manufacturing Date (Year) Assembly Manufacturing Date (Week) Assembly Serial Number Reserved Intel Specification for Frequency Reserved Unused Storage Location SPD Entry Value 128 MByte 2.0 ns 1.0 ns 2.0 ns 1.0 ns 16Mx64 20 20 10 20 10 00 Revision 1.2 12 95 Mosel Vitelic 40 00 V436516R04VATG-10PC 00 100 MHz 64 00 00 TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V Limit Values Symbol VIH VIL VOH VOL II(L) IO(L) DC Characteristics Parameter Input High Voltage Input Low Voltage Output High Voltage (IOUT = –2.0 mA) Output Low Voltage (IOUT = 2.0 mA) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) Output leakage current (DQ is disabled, 0V < VOUT < VCC) Min. 2.0 –0.5 2.4 — –40 Max. VCC+0.3 0.8 — 0.4 40 Unit V V V V µA µA –40 40 V436516R04VATG-10PC Rev. 1.1 February 2001 5 MOSEL VITELIC TA = 0°C to 70°C; VDD = 3.3V ± 0.3V, f = 1 MHz V436516R04VATG-10PC Capacitance Limit Values Symbol CI1 CI2 CICL CI3 CI4 CIO CSC CSD Parameter Input Capacitance (A0 to A11, RAS, CAS, WE) Input Capacitance (CS0-CS3) Input Capacitance (CLK0-CLK3) Input Capacitance (CKE0, CKE1) Input Capacitance (DQM0-DQM7) Input/Output Capacitance (I/O1-I/064) Input Capacitance (SCL, SA0-2) Input/Output Capacitance (SA0-SA2) Max. 16M x 64 60 30 22 50 15 15 8 10 Unit pF pF pF pF pF pF pF pF Absolute Maximum Ratings Parameter Voltage on VDD Supply Relative to VSS Voltage on Input Relative to VSS Operating Temperature Storage Temperature Power Dissipation Max. -1 to 4.6 -1 to 4.6 0 to +70 -55 to 125 4 Units V V °C °C W Operating Currents TA = 0°C to 70°C, VCC = 3.3V ± 0.3V (Recommended operating conditions otherwise noted) Max. Symbol ICC1 Parameter & Test Condition Operating Current tRC = tRCMIN., tCK= tCKMIN. Active-precharge command cycling, without Burst Operation Precharge Standby Current in Power Down Mode CS =VIH, CKE≤ VIL(max) Precharge Standby Current in Non-Power Down Mode CS =VIH, CKE≥ VIL(max) No Operating Current tCK = min, CS = VIH(min) bank ; active state ( 4 banks) Burst Operating Current tCK = min Read/Write command cycling 1 bank operation -10PC 680 Unit mA Note 7 ICC2P ICC2PS ICC2N ICC2NS ICC3 ICC3P tCK = min. tCK = Infinity tCK = min. tCK = Infinity CKE ≥ VIH(MIN.) CKE ≤ VIL(MAX.) (Power down mode) 12 8 180 20 220 80 mA mA mA mA mA mA 7 7 ICC4 440 mA 7,8 V436516R04VATG-10PC Rev. 1.1 February 2001 6 MOSEL VITELIC Operating Currents V436516R04VATG-10PC TA = 0°C to 70°C, VCC = 3.3V ± 0.3V (Recommended operating conditions otherwise noted) (Continued) Max. Symbol ICC5 Parameter & Test Condition Auto Refresh Current tCK = min Auto Refresh command cycling Self Refresh Current Self Refresh Mode, CKE=0.2V -10PC 1000 Unit mA Note 7 ICC6 12 L-version 6.4 mA mA Notes: 1. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t CK and tRC. Input signals are changed one time during tCK. 2. These parameter depend on output loading. Specified values are obtained with output open. AC Characteristics 3,4 TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns Limit Values -10PC # Symbol Parameter Min. Max. Unit Note Clock and Clock Enable 1 tCK Clock Cycle Time CAS Latency = 3 CAS Latency = 2 System frequency CAS Latency = 3 CAS Latency = 2 Clock Access Time CAS Latency = 3 CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Input Setup time Input Hold Time CKE Setup Time (Power down mode) CKE Setup Time (Self Refresh Exit) Transition time (rise and fall) 10 10 – – – – 3 3 2 1 2.5 8 1 100 100 6 6 – – – – – – – ns ns MHz MHz 4,5 ns ns ns ns ns ns ns ns ns 6 6 7 7 8 9 2 fCK 3 tAC 4 5 6 7 8 9 10 tCH tCL tCS tCH tCKSP tCKSR tT Common Parameters 11 12 13 14 15 16 tRCD tRC tRAS tRP tRRD tCCD RAS to CAS delay Cycle Time Active Command Period Precharge Time Bank to Bank Delay Time CAS to CAS delay time (same bank) 20 70 45 20 16 1 – 120k – – – – ns ns ns ns ns CLK V436516R04VATG-10PC Rev. 1.1 February 2001 7 MOSEL VITELIC AC Characteristics 3,4 TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns (Continued) V436516R04VATG-10PC Limit Values -10PC # Symbol Parameter Min. Max. Unit Note Refresh Cycle 17 18 tSREX tREF Self Refresh Exit Time Refresh Period (4096 cycles) 10 64 – – ns ms 9 8 Read Cycle 19 20 21 22 tOH tLZ tHZ tDQZ Data Out Hold Time Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency 3 0 3 2 – – 9 – ns ns ns CLK 10 4 Write Cycle 23 24 25 tDPL tDAL tDQW Data input to Precharge (write recovery) Data In to Active/refresh DQM Write Mask Latency 2 5 0 – – – CLK CLK CLK 11 Notes: 1. The specified values are valid when addresses are changed no more than once during tCK(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.). 3. All AC characteristics are shown for device level. An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have VIL = 0.4V and VIH = 2.4V with the timing referenced to the 1.4V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V V436516R04VATG-10PC Rev. 1.1 February 2001 8 MOSEL VITELIC . tCH 2.4V CLOCK 0.4V V436516R04VATG-10PC + 1.4 V 50 Ohm Z=50 Ohm I/O 50 pF tCL tSETUP tHOLD tT INPUT 1.4V tAC tLZ tOH tAC I/O 50 pF 1.4V OUTPUT Measurement conditions for tac and toh tHZ 5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10. 11. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. tDAL is equivalent to tDPL + tRP. V436516R04VATG-10PC Rev. 1.1 February 2001 9 MOSEL VITELIC Package Diagram SDRAM DIMM Module Package V436516R04VATG-10PC All measurements in mm 133.35 127.35 (3.81 max) 1 3.0 10 11 40 41 84 42.18 66.68 A B C 17.78 35.00 1.27 ± 0.100 85 94 95 124 125 168 D 6.35 6.35 1.27 1.0 + 0.5 3.125 3.125 2.4 min. 0.2 ± 0.15 2.0 Detail A 2.26 Detail B 2.0 Detail C 8.25 4.45 RADIUS 1.27 + 0.10 Tolerances: ± (0.13) unless otherwise specified. V436516R04VATG-10PC Rev. 1.1 February 2001 10 MOSEL VITELIC Label Information MOSEL VITELIC Part Number Criteria of PC100 or PC133 (refer to MVI datasheet) V436516R04VATG-10PC V436516R04VATG-10PC PC100U-222-612-A Taiwan XXXX-XXXXXXX DIMM manufacture date code Trace Code PC100 U - 222 - 6 12 - A UNBUFFERED DIMM CL = 2 (CLK) tRCD = 2 (CLK) tRP = 2 (CLK) Gerber file Intel® PC100 x 16 Based JEDEC SPD Revision 1.2 tAC = 6 ns V436516R04VATG-10PC Rev. 1.1 February 2001 11 MOSEL VITELIC U.S.A. 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 WORLDWIDE OFFICES TAIWAN 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888 V436516R04VATG-10PC UK & IRELAND SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516 SINGAPORE 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 JAPAN ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402 GERMANY (CONTINENTAL EUROPE & ISRAEL) BENZSTRASSE 32 71083 HERRENBERG GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22 U.S. SALES OFFICES NORTHWESTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 SOUTHWESTERN 302 N. EL CAMINO REAL #200 SAN CLEMENTE, CA 92672 PHONE: 949-361-7873 FAX: 949-361-7807 CENTRAL, NORTHEASTERN & SOUTHEASTERN 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 214-826-6176 FAX: 214-828-9754 © Copyright 2001, MOSEL VITELIC Inc. 2/01 Printed in U.S.A. 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