V436532S04VATG-10PC

MOSEL VITELIC V436532S04VATG-10PC 3.3 VOLT 32M x 64 HIGH PERFORMANCE PC100 UNBUFFERED SDRAM MODULE PRELIMINARY Features s 168 Pin Unbuffered 33,554,432 x 64 bit Oganization SDRAM Modules s Utilizes High Performance 128 Mbit, 16M x 8 SDRAM in TSOPII-54 Packages s Fully PC Board Layout Compatible to INTEL’S Rev 1.0 Module Specification s Single +3.3V (± 0.3V) Power Supply s Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) s Auto Refresh (CBR) and Self Refresh s All Inputs, Outputs are LVTTL Compatible s 4096 Refresh Cycles every 64 ms s Serial Present Detect (SPD) s SDRAM Performance Description The V436532S04VATG-10PC memory module is organized 33,554,432 x 64 bits in a 168 pin dual in line memory module (DIMM). The 32M x 64 unbuffered DIMM uses 16 Mosel-Vitelic 128 Mbit, 16M x 8 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. Key Component Timing Parameters tCK tAC tAC Clock Frequency (max.) Clock Access Time CAS Latency = 3 Latency = 2 -8PC 125 6 Units MHz ns 6 ns s Module Frequency vs AC Parameter Frequency V436532S04VATG-10PC 100 MHz (PC) CL (CAS Latency) 3 2 tRCD 2 2 tRP 2 2 tRC 7 7 Unit CLK CLK V436532S04VATG-10PC-01 V436532S04VATG-10PC Rev. 1.0 February 2001 1 MOSEL VITELIC Pin Configurations (Front Side/Back Side) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front VSS I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 I/O9 VSS I/O10 I/O11 I/O12 I/O13 I/O14 VCC I/O15 I/O16 CBO* CB1* VSS NC NC VCC WE DQM0 Pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Front DQM1 CS0 DU VSS A0 A2 A4 A6 A8 A10(AP) BA1 VCC VCC CLK0 VSS DU CS2 DQM2 DQM3 DU VCC NC NC CB2* CB3* VSS I/O17 I/O18 Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front I/O19 I/O20 VCC I/O21 NC DU CKE1 VSS I/O22 I/O23 I/O24 VSS I/O25 I/O26 I/O27 I/O28 VCC I/O29 I/O30 I/O31 I/O32 VSS CLK2 NC WP SDA SCL VCC Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS I/O33 I/O34 I/O35 I/O36 VCC I/O37 I/O38 I/O39 I/O40 I/O41 VSS I/O42 I/O43 I/O44 I/O45 I/O46 VCC I/O47 I/O48 CB4* CB5* VSS NC NC VCC CAS DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 V436532S04VATG-10PC Back DQM5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VCC CLK1 NC VSS CKE0 CS3 DQM6 DQM7 DU VCC NC NC CB6* CB7* VSS I/O49 I/O50 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back I/O51 I/O52 VCC I/O53 NC DU NC VSS I/O54 I/O55 I/O56 VSS I/O57 I/O58 I/O59 I/O60 VCC I/O61 I/O62 I/O63 I/O64 VSS CLK3 NC SA0 SA1 SA2 VCC Notes: * These pins are not used in this module. Pin Names A0–A11 I/O1–I/O64 RAS CAS WE BA0, BA1 CKE0, CKE1 CS0–CS3 CLK0–CLK3 DQM0–DQM7 VCC VSS SCL Address Inputs Data Inputs/Outputs Row Address Strobe Column Address Strobe Read/Write Input Bank Selects Clock Enable Chip Select Clock Input Data Mask Power (+3.3 Volts) Ground Clock for Presence Detect CB0–CB7 NC DU SA0–A2 SDA Serial Data OUT for Presence Detect Serial Data IN for Presence Detect Check Bits (x72 Organization) No Connection Don’t Use V436532S04VATG-10PC Rev. 1.0 February 2001 2 MOSEL VITELIC Module Part Number Information V MOSEL-VITELIC MANUFACTURED SDRAM 3.3V WIDTH (x64 using 128 Mbit) DEPTH 168 PIN UNBUFFERED DIMM X 8 COMPONENT LVTTL 4 BANKS V436532S04VATG-10PC 4 3 65 32 S 0 4 V A T G GOLD 10PC -10PC PC100 2-2-2 TSOP A VERSION V436532S04VATG-10PC-02 REFRESH RATE 4K Block Diagram CS1 CS0 DQM0 I/O1–I/O8 DQM1 I/O9–I/O16 DQM CS I/O1–I/O8 D0 DQM CS I/O1–I/O8 D1 DQM CS I/O1–I/O8 D8 DQM CS I/O1–I/O8 D9 DQM4 I/O33–I/O40 DQM5 I/O41–I/O48 DQM CS I/O1–I/O8 D4 DQM CS I/O1–I/O8 D5 DQM CS I/O1–I/O8 D12 DQM CS I/O1–I/O8 D13 10Ω 10Ω 10Ω 10Ω CS3 CS2 DQM2 I/O17–I/O24 DQM3 I/O25–I/O32 CS DQM I/O1–I/O8 D2 DQM I/O1–I/O8 CS D3 CS DQM I/O1–I/O8 D10 DQM I/O1–I/O8 D11 CS DQM6 I/O49–I/O56 DQM7 I/O57–I/O64 CS DQM I/O1–I/O8 D6 CS DQM I/O1–I/O8 D7 CS DQM I/O1–I/O8 D14 CS DQM I/O1–I/O8 D15 10Ω 10Ω 10Ω 10Ω E2PROM SPD (256 WORD X 8 BIT) SA0 SA1 SA2 SCL SA0 SA1 SA2 SCL SDA A11-A0, BA0, BA1 VDD C0-C31 D0-D15 D0-D15 D0-D7 D0-D15 D0-D7 VCC 10K WP 47K VSS RAS, CAS, WE CKE0 CLOCK WIRING 32M X 64 CLK0 CLK1 CLK2 CLK3 4 SDRAM +3.3pF 4 SDRAM +3.3pF 4 SDRAM +3.3pF 4 SDRAM +3.3pF CKE1 D9-D15 V436532S04VATG-10PC-03 V436532S04VATG-10PC Rev. 1.0 February 2001 3 MOSEL VITELIC Serial Presence Detect Information A serial presence detect storage device - is assembled onto the module. Information about the module configuration, speed, etc. is E2PROM V436532S04VATG-10PC written into the E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus) SPD-Table: Hex Value Byte Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function Described Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for x8 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (continued) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access Time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM Data Width Minimum Clock Delay from Back to Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Minimum Clock Cycle Time at CAS Latency = 2 Maximum Data Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL = 1 Minimum Row Precharge Time tRP Minimum Row Active to Row Active Delay tRRD Minimum RAS to CAS Delay tRCD SPD Entry Value 128 256 SDRAM 12 10 2 64 0 LVTTL 10.0 ns 6.0 ns none Self-Refresh, 15.6µs x8 n/a / x8 tccd = 1 CLK 1, 2, 4, 8 & full Page 4 CL = 2 & 3 CS Latency = 0 WL = 0 Non Buffered/Non Reg. Vcc tol ± 10% 10.0 ns 6.0 ns Not Supported Not Supported 20 ns 16 ns 20 ns 100 MHz -10PC 80 08 04 0C 0A 02 40 00 01 A0 60 00 80 08 00 01 16 17 18 19 20 21 22 23 24 25 26 27 28 29 8F 04 06 01 01 00 0E A0 60 00 00 14 10 14 V436532S04VATG-10PC Rev. 1.0 February 2001 4 MOSEL VITELIC SPD-Table: (Continued) V436532S04VATG-10PC Hex Value Byte Number 30 31 32 33 34 35 36-61 62 63 64-125 Function Described Minimum RAS Pulse Width tRAS Module Bank Density (Per Bank) SDRAM Input Setup Time SDRAM Input Hold Time SDRAM Data Input Setup Time SDRAM Data Input Hold Time Superset Information (May be used in Future) SPD Revision Checksum for Bytes 0 - 62 Manufacturers’s Information (Optional) (FFh if not used) Max. Frequency Specification 100 MHz Support Details Unused Storage Location SPD Entry Value 45 ns 128 MByte 2 ns 1 ns 2 ns 1 ns 100 MHz -10PC 2D 20 20 10 20 10 00 Revision 1.2 12 FD 126 127 128+ 100 MHz 64 FF 00 TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V Limit Values Symbol VIH VIL VOH VOL II(L) IO(L) DC Characteristics Parameter Input High Voltage Input Low Voltage Output High Voltage (IOUT = –2.0 mA) Output Low Voltage (IOUT = 2.0 mA) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) Output leakage current (DQ is disabled, 0V < VOUT < VCC) Min. 2.0 –0.5 2.4 — –40 Max. VCC+0.3 0.8 — 0.4 40 Unit V V V V µA µA –40 40 V436532S04VATG-10PC Rev. 1.0 February 2001 5 MOSEL VITELIC Capacitance Symbol CI1 CI2 CICL CI3 CI4 CIO CSC CSD V436532S04VATG-10PC TA = 0°C to 70°C; VDD = 3.3V ± 0.3V, f = 1 MHz Parameter Input Capacitance (A0 to A11, RAS, CAS, WE) Input Capacitance (CS0-CS3) Input Capacitance (CLK0-CLK3) Input Capacitance (CKE0, CKE1) Input Capacitance (DQM0-DQM7) Input/Output Capacitance (I/O1-I/064) Input Capacitance (SCL, SA0-2) Input/Output Capacitance Limit Values 80 30 22 50 20 20 8 10 Unit pF pF pF pF pF pF pF pF Absolute Maximum Ratings Parameter Voltage on VDD Supply Relative to VSS Voltage on Input Relative to VSS Operating Temperature Storage Temperature Power Dissipation Max. -1 to 4.6 -1 to 4.6 0 to +70 -55 to 125 6 Units V V °C °C W V436532S04VATG-10PC Rev. 1.0 February 2001 6 MOSEL VITELIC Standby and Refresh Currents1 TA = 0°C to 70°C, VCC = 3.3V ± 0.3V Symbol Parameter ICC1 Operating Current V436532S04VATG-10PC Test Conditions Burst length = 4, CL = 3 tRC> = tRC(min), tCK> = tCK(min), IO = 0 mA 2 Bank Interleave Operation CKE< = VIL(max), tCK> = tCK(min) CKE< = VIL(max), tCK = Infinite CKE> = VIH(min), tCK> = tCK(min), Input changed once in 3 cycles CKE> = VIH(min), tCK = Infinite, No Input change 32M x 64 1600 Unit mA Note 1,2 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3N Precharged Standby Current in Power Down Mode Precharged Standby Current in Non-Power Down Mode 60 40 400 mA mA mA CS = High 40 mA Active Standby Current in Power Down Mode Active Standby Current in Non-Power Down Mode CKE< = VIL(max), tCK> = tCK(min) CKE> = VIH(min), tCK> = tCK(min), Input changed one time 50 mA 680 mA CS = High ICC4 Burst Operating Current Burst length = Full Page, tRC = Infinite, CL = 3, tCK> = tCK(min), IO = 0 mA 2 Banks Activated tRC>= tRC(min) CKE =