V53C16258SHT50

MOSEL VITELIC V53C16258SH HIGH PERFORMANCE 256K X 16 EDO PAGE MODE CMOS DYNAMIC RAM SELF REFRESH PRELIMINARY HIGH PERFORMANCE Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Extended Data Out Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC) 50 50 ns 24 ns 19 ns 90 ns Features s 256K x 16-bit organization s EDO Page Mode for a sustained data rate of 53 MHz (-50ns) s RAS access time: 50 ns s Dual CAS Inputs s Low power dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh s Self Refresh s Refresh Interval: 512 cycles/8 ms s Available in 40-pin 400 mil SOJ and 40/44L-pin 400 mil TSOP-II packages s Single +5V ±10% Power Supply s TTL Interface Description The V53C16258SH is a high speed 262,144 x 16 bit high performance CMOS dynamic random access memory. The V53C16258SH offers a combination of unique features including: EDO Page Mode operation for higher sustained bandwidth with Page Mode cycle times as short as 19ns. All inputs are TTL compatible. Input and output capacitance is significantly lowered to increase performance and minimize loading. These features make the V53C16258SH ideally suited for a wide variety of high performance computer systems and peripheral applications. Device Usage Chart Operating Temperature Range 0°C to 70°C Package Outline K • T • Access Time (ns) 50 • Power Std. • Temperature Mark Blank V53C16258SH Rev 0.3 September 1998 1 MOSEL VITELIC Part Name V53C16258SHK50 V53C16258SHT50 V53C16258SH Supply Voltage 5V 5V Self Refresh Standard Self Refresh (8ms) Standard Self Refresh (8ms) Package SOJ TSOP Speed 50 50 V 5 3 C 16 2 5 8 S H 40-Pin SOJ PIN CONFIGURATION Top View Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8 NC NC WE RAS NC A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 16258H-02 FAMILY DEVICE S STANDARD SELF REFRESH) H (5V) PKG SPEED ( t RAC) TEMP. PWR. BLANK (0¡C to 70¡C) BLANK (NORMAL) 50 (50 ns) Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9 NC LCAS UCAS OE A8 A7 A6 A5 A4 Vss K (SOJ) T (TSOP-II) 40/44 Pin Plastic TSOP-II PIN CONFIGURATION Top View Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 Pin Names A0–A8 RAS UCAS LCAS WE OE I/O1–I/O16 VCC VSS NC Address Inputs Row Address Strobe Column Address Strobe/Upper Byte Control Column Address Strobe/Lower Byte Control Write Enable Output Enable Data Input, Output +5V Supply 0V Supply No Connect Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9 NC NC WE RAS NC A0 A1 A2 A3 Vcc 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 16258H-03 NC LCAS UCAS OE A8 A7 A6 A5 A4 Vss V53C16258SH Rev 0.2 Aug. 1998 2 MOSEL VITELIC Absolute Maximum Ratings* Ambient Temperature Under Bias ..................................... –10°C to +80°C Storage Temperature (plastic) ..... –55°C to +125°C Voltage Relative to VSS .................–1.0 V to +7.0 V Data Output Current ..................................... 50 mA Power Dissipation .......................................... 1.0 W *Note: Operation above Absolute Maximum Ratings can adversely affect device reliability. V53C16258SH TA = 25°C, VCC = 5 V ± 10%, VSS = 0 V Symbol CIN1 CIN2 COUT Parameter Address Input RAS, CAS, WE, OE Data Input/Output Typ. 3 4 5 Max. 4 5 7 Unit pF pF pF Capacitance* * Note: Capacitance is sampled and not 100% tested Block Diagram 256K x 16 OE WE UCAS LCAS RAS RAS CLOCK GENERATOR CAS CLOCK GENERATOR WE CLOCK GENERATOR OE CLOCK GENERATOR VCC VSS DATA I/O BUS COLUMN DECODERS Y -Y8 0 I/O 1 I/O 2 I/O 3 SENSE AMPLIFIERS 512 x 16 I/O BUFFER I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 REFRESH COUNTER 9 A0 A1 ADDRESS BUFFERS AND PREDECODERS X0 -X8 ROW DECODERS 512 • • • A7 A8 MEMORY ARRAY 256K x 16 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 16258H-04 V53C16258SH Rev 0.2 Aug. 1998 3 MOSEL VITELIC DC and Operating Characteristics (1-2) TA = 0°C to 70°C, VCC = 5 V ± 10%, VSS = 0 V, unless otherwise specified. V53C16258SH Symbol ILI ILO ICC1 ICC2 ICC3 ICC4 ICC5 V53C16258SH Parameter Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) VCC Supply Current, Operating VCC Supply Current, TTL Standby VCC Supply Current, RAS-Only Refresh VCC Supply Current, EDO Page Mode Operation VCC Supply Current, Standby, Output Enabled other inputs ³ VSS VCC Supply Current, CMOS Standby Min. –10 Typ. Max. 10 Unit mA mA mA Test Conditions VSS £ VIN £ VCC VSS£ VOUT £ VCC RAS, CAS at VIH tRC = tRC (min.) RAS, CAS at VIH other inputs ³ VSS tRC = tRC (min.) Minimum Cycle Notes –10 10 160 1, 2 2 mA 160 mA 2 150 mA 1, 2 2 mA RAS = VIH, CAS = VIL 1 ICC6 1 mA RAS ³ VCC – 0.2 V, CAS ³ VCC– 0.2 V, All other inputs ³ VSS CBR Cycle with tRAS ³ tRASS (Min.) and CAS = VIL ICC7 VCC VIL VIH VOL VOH Self Refresh Current 400 mA V V V V V Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 4.5 –1 2.4 5.0 5.5 0.8 VCC + 1 0.4 3 3 IOL = 2 mA IOH = –2 mA 2.4 V53C16258SH Rev 0.2 Aug. 1998 4 MOSEL VITELIC TA = 0°C to 70°C, VCC = 5 V ± 10%, VSS = 0V unless otherwise noted AC Test conditions, input pulse levels 0 to 3V 50 # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol tRAS tRC tRP tCSH tCAS tRCD tRCS tASR tRAH tASC tCAH tRSH (R) tCRP tRCH tRRH tROH tOAC tCAC tRAC tCAA tLZ tHZ tAR tRAD tRSH (W) tCWL tWCS tWCH tWP Parameter RAS Pulse Width Read or Write Cycle Time RAS Precharge Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Read Command Setup Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time RAS Hold Time (Read Cycle) CAS to RAS Precharge Time Read Command Hold Time Referenced to CAS Read Command Hold Time Referenced to RAS RAS Hold Time Referenced to OE Access Time from OE Access Time from CAS Access Time from RAS Access Time from Column Address OE or CAS to Low-Z Output OE or CAS to High-Z Output Column Address Hold Time from RAS RAS to Column Address Delay Time RAS or CAS Hold Time in Write Cycle Write Command to CAS Lead Time Write Command Setup Time Write Command Hold Time Write Pulse Width 0 0 40 14 Min. 50 90 30 50 9 19 0 0 9 0 7 10 5 0 V53C16258SH AC Characteristics Max. 75K Unit ns ns ns ns ns Notes 36 ns ns ns ns ns ns ns ns ns 5 4 15 0 ns 5 16 10 ns 17 18 19 20 14 14 50 24 ns ns ns ns 12 6, 7, 14 6, 8, 9 6, 7, 10 21 22 23 24 ns 8 ns ns 26 ns 16 16 11 25 10 ns 26 14 ns 27 28 29 0 7 7 ns ns ns 12, 13 V53C16258SH Rev 0.2 Aug. 1998 5 MOSEL VITELIC AC Characteristics (Cont’d) 50 # 30 31 32 33 34 35 36 37 Symbol tWCR tRWL tDS tDH tWOH tOED tRWC tRRW tCWD tRWD tCRW tAWD tPC tCP tCAR tCAP tDHR tCSR tRPC tCHR tPCM tCOH tOES tOEH tOEP tT tREF Parameter Write Command Hold Time from RAS Write Command to RAS Lead Time Data in Setup Time Data in Hold Time Write to OE Hold Time OE to Data Delay Time Read-Modify-Write Cycle Time Read-Modify-Write Cycle RAS Pulse Width CAS to WE Delay RAS to WE Delay in ReadModify-Write Cycle CAS Pulse Width (RMW) Col. Address to WE Delay EDO Fast Page Mode Read or Write Cycle Time CAS Precharge Time Column Address to RAS Setup Time Access Time from Column Precharge Data in Hold Time Referenced to RAS CAS Setup Time CAS-beforeRAS Refresh RAS to CAS Precharge Time CAS Hold Time CAS-beforeRAS Refresh EDO Page Mode Read-Modify-Write Cycle Time Output Hold After CAS Low OE Low to CAS High Setup Time OE Hold Time from WE during Read-Modify Write Cycle OE High Pulse Width Transition Time (Rise and Fall) Refresh Interval (512 Cycles) 40 10 Min. 40 14 0 7 8 8 130 87 V53C16258SH Max. Unit ns ns ns ns ns ns ns ns Notes 14 14 14 14 38 39 34 68 ns ns 12 12 40 41 42 52 42 19 ns ns ns 12 43 44 45 7 24 27 ns ns ns 7 46 47 ns ns 48 49 0 12 ns ns 50 70 ns 51 52 53 5 5 10 ns ns ns 54 55 56 10 1.5 50 8 ns ns ms 15 17 V53C16258SH Rev 0.2 Aug. 1998 6 MOSEL VITELIC AC Characteristics (Cont’d) 50 # Symbol Parameter Min. V53C16258SH Max. Unit Notes Self Refresh 57 tRASS tRPS tCHS tCHD RAS Pulse Width During Self Refresh RAS Precharge Time During Self Refresh CAS Hold Time Width During Self Refresh CAS Low Time During Self Refresh 100 ms ns 18 58 100 18 59 100 ns ms 18 60 100 18 Notes: 1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the output open. 2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two transitions per address cycle in EDO Page Mode. 3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to –1.0 V for a period not to exceed 20 ns. All AC parameters are measured with VIL (min.) ³ VSS and VIH (max.) £ VCC. 4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA (max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC. 5. Either tRRH or tRCH must be satisified for a Read Cycle to occur. 6. Measured with a load equivalent to one TTL input and 50 pF. 7. Access time is determined by the longest of tCAA, tCAC and tCAP. 8. Assumes that tRAD £ tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD exceeds tRAD (max.). 9. Assumes that tRCD £ tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD exceeds tRCD (max.). 10. Assumes that tRAD ³ tRAD (max.). 11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC. 12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 13. tWCS (min.) must be satisfied in an Early Write Cycle. 14. tDS and tDH are referenced to the latter occurrence of CAS or WE. 15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns. 16. Assumes a three-state test load (5 pF and a 500 Ohm Thevenin equivalent). 17. An initial 200 ms pause and 8 RAS-containing cycles are required when exiting an extended period of bias without clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval. 18. One CBR refresh or complete set of row refresh cycles must be completed upon existing Self Refresh Mode. V53C16258SH Rev 0.2 Aug. 1998 7 MOSEL VITELIC Truth Table Function Standby Read: Word Read: Lower Byte V53C16258SH RAS H L L LCAS H L L UCAS H L H WE X H H OE X L L ADDRESS X ROW/COL ROW/COL I/O High-Z Data Out Lower Byte, Data-Out Upper Byte, High-Z Lower Byte, High-Z Upper Byte, Data-Out Data-In Lower Byte, Data-In Upper Byte, High-Z Lower Byte, High-Z Upper Byte, Data-In Data-Out, Data-In Data-Out Data-In Data-Out, Data-In Data-Out High-Z High-Z High-Z Notes Read: Upper Byte L H L H L ROW/COL Write: Word (Early-Write) Write: Lower Byte (Early) L L L L L H L L X X ROW/COL ROW/COL Read: Upper Byte (Early) L H L L H®L H L H®L H X X X X L®H L X L®H L X X X ROW/COL Read-Write EDO Page-Mode Read EDO Page-Mode Write EDO Page-Mode Read-Write Hidden Refresh Read RAS-Only Refresh CBR Refresh Self Refresh L L L L L®H®L L H®L H®L L H®L H®L H®L L H L L L H®L H®L H®L L H L L ROW/COL COL COL COL ROW/COL ROW X X 1, 2 2 2 1, 2 2 3 Notes: 1. Byte Write cycles LCAS or UCAS active. 2. Byte Read cycles LCAS or UCAS active. 3. Only one of the two CAS must be active (LCAS or UCAS). V53C16258SH Rev 0.2 Aug. 1998 8 MOSEL VITELIC Waveforms of Read Cycle t RAS (1) RAS VIH VIL t CRP (13) t RCD (6) t RAD (24) t ASR (8) ADDRESS VIH VIL ROW ADDRESS t RAH (9) t ASC (10) t CAH (11) t CSH (4) t RSH (R)(12) t CAS (5) t AR (23) t RC (2) t RP (3) V53C16258SH t CRP (13) UCAS, LCAS VIH VIL COLUMN ADDRESS t CAR (44) t RCH (14) t RRH (15) t RCS (7) WE VIH VIL t ROH (16) t CAA (20) t OAC (17) t OES (52) OE VIH VIL I/O VOH VOL t RAC (19) t CAC (18) t HZ (22) VALID DATA-OUT t HZ (22) t LZ (21) 16258H-05 Waveforms of Early Write Cycle t RC (2) VIH V IL t CSH (4) tCRP (13) VIH UCAS, LCAS V IL t RAH (9) tASR (8) ADDRESS VIH V IL ROW ADDRESS t RAD (24) t CWL (26) VIH V IL t WCR (30) t RWL (31) OE VIH V IL t DHR (46) tDS (32) I/O VIH V IL tDH (33) VALID DATA-IN HIGH-Z 16258H-06 tAR (23) t RAS (1) t RP (3) RAS t RCD (6) t RSH (W)(25) t CAS (5) t CRP (13) t CAR (44) t CAH (11) tASC (10) COLUMN ADDRESS t WCH (28) t WP(29) tWCS (27) WE Don’t Care V53C16258SH Rev 0.2 Aug. 1998 Undefined 9 MOSEL VITELIC Waveforms of OE-Controlled Write Cycle t RAS (1) t RC (2) t RP (3) V53C16258SH RAS V IH V IL t CRP (13) t AR (23) t RCD (6) t CSH (4) UCAS, LCAS V IH V IL t RAD (24) t RAH (9) t RSH (W)(12) t CAS (5) t CRP (13) t CAR (44) t CAH (11) t ASC (10) t ASR (8) ADDRESS V IH V IL ROW ADDRESS COLUMN ADDRESS t CWL (26) t RWL (31) t WP (29) WE V IH V IL t WOH (34) OE V IH V IL t OED (35) V IH V IL t DH (33) t DS (32) VALID DATA-IN 16258H-07 I/O Waveforms of Read-Modify-Write Cycle t RWC (36) tRRW (37) RAS VIH VIL t CSH (4) t CRP (13) t RCD (6) VIH VIL t RAH (9) t ASR (8) ADDRESS VIH VIL ROW ADDRESS t RAD (24) t ACS VIH VIL VIH VIL t OED (35) t CAC (18) t RAC (19) I/O VIH VIL VOH VOL t LZ (21) VALID DATA-OUT t HZ (22) t DS (32) VALID DATA-IN 16258H-08 t RP (3) t AR (23) t RSH (W)(25) t CRW (40) t t ASC (10) COLUMN ADDRESS t AWD (41) t CWD (38) t RWL (31) t CWL (26) t CRP (13) UCAS, LCAS CAH (11) t RWD (39) t WP (29) WE t CAA (20) t OAC (17) t OEH (53) t DH (33) OE Don’t Care V53C16258SH Rev 0.2 Aug. 1998 Undefined 10 MOSEL VITELIC Waveforms of EDO Page Mode Read Cycle V IH V IL t AR (23) t RCD (6) t CRP (13) UCAS, LCAS V IH V IL t RAH (9) t CSH (4) t ASC (10) t CAH (11) COLUMN ADDRESS t RCH (14) t CAH (11) t CAA (20) t OAC (17) OE V IH V IL t RAC (19) t CAC (18) t LZ (21) V OH V OL t RCS (7) t CAR (44) t PC (42) t CP (43) t RSH (R)(12) t CAS (5) t RAS (1) V53C16258SH t RP (3) RAS t CAS (5) t CRP (13) t CAS (5) t ASR (8) ADDRESS V IH V IL t ASC (10) ROW ADDRESS t RCS (7) t CAH (11) COLUMN ADDRESS t RCS (7) t RCH (14) COLUMN ADDRESS WE V IH V IL t CAP (45) t OES (52) t OEP (54) t CAC (18) t HZ (22) VALID DATA OUT t LZ VALID DATA OUT 16258H-09 t CAA (20) t OAC (17) t RRH (15) t CAC (18) t COH (5) VALID DATA OUT t HZ (22) t HZ (22) t HZ (22) I/O Waveforms of EDO Page Mode Write Cycle t AR (23) RAS V IH V IL t CRP (13) t RCD (6) UCAS, LCAS V IH V IL t RAH (9) t ASR (8) ADDRESS V IH V IL t RAD (24) t WCS (27) t WP (29) WE V IH V IL VIH V IL t DS (32) I/O V IH V IL VALID DATA IN ROW ADD COLUMN ADDRESS t RP (3) t RAS (1) t PC (42) t CP (43) t CAS (5) t RSH (W)(25) t CAS (5) t CAS (5) t CRP (13) t CSH (4) t ASC (10) COLUMN ADDRESS t CAH (11) t CAH (11) t ASC (10) t CAR (44) t CAH (11) COLUMN ADDRESS t CWL (26) t WCH (28) t WCS (27) t CWL (26) t WCH (28) t WP (29) t WCS (27) t CWL (26) t RWL (31) t WCH (28) t WP (29) OE t DH (33) t DS (32) t DH (33) VALID DATA IN t DS (32) t DH (33) VALID DATA IN OPEN OPEN 16258H-10 Don’t Care V53C16258SH Rev 0.2 Aug. 1998 Undefined 11 MOSEL VITELIC Waveforms of EDO Page Mode Read-Write Cycle RAS VIH V IL V53C16258SH t RAS (1) t RCD (6) t CSH (4) t PCM (50) t CAS (5) t RP (3) t RSH (W)(25) t CRP (13) t CAS (5) t CP (43) t CAS (5) V UCAS, LCAS V IH IL t RAD (24) t RAH (9) t ASR (8) t ASC (10) t ASC (10) COLUMN ADDRESS t CAH (11) COLUMN ADDRESS t CAH (11) t ASC (10) t CAR (44) t CAH (11) COLUMN ADDRESS V ADDRESS V IH IL ROW ADD t RWD (39) t CWD (38) V WE V IH IL t CWL (26) t CWD (38) t CWL (26) t CWD (38) t RWL (31) t CWL (26) t CAA (20) t OAC (17) V OE V IH IL t AWD (41) t AWD (41) t WP (29) t OAC (17) t OEH (53) t CAA (20) t CAP (43) t AWD (41) t OAC (17) t WP (29) t WP (29) t OED (35) t CAC (18) t RAC (19) t OED (35) t CAC (18) t DH (33) t CAP (43) t CAA (20) t HZ (22) t HZ (22) t DS (32) I/O V I/OH V I/OL t LZ (21) OUT IN OUT t DH (33) t DS (32) t OED (35) t CAC (18) t HZ (22) t DH (33) t DS (32) OUT IN IN t LZ t LZ 16258H-11 Waveforms of RAS-Only Refresh Cycle t RC (2) V IH V IL t CRP (13) UCAS, LCAS V IH V IL t ASR (8) ADDRESS V IH V IL NOTE: ROW ADD 16258H-12 t RAS (1) t RP (3) RAS t RAH (9) WE, OE = Don’t care Don’t Care V53C16258SH Rev 0.2 Aug. 1998 Undefined 12 MOSEL VITELIC Waveforms of CAS-before-RAS Refresh Counter Test Cycle t RAS (1) RAS V IH V IL t CSR (47) UCAS, LCAS V IH V IL V IH V IL READ CYCLE V IH V IL t LZ (21) I/O V IH V IL WRITE CYCLE V IH V IL V IH V IL t I/O V IH V IL DS (32) V53C16258SH t RP (3) t CHR (49) t CP (43) t RSH (W)(25) t CAS (5) ADDRESS t RCS (7) t RRH (15) t RCH (14) WE t HZ (22) D OUT t RWL (31) t CWL (26) t WCS (27) t WCH (28) WE OE t DH (33) D IN 16258H-13 Waveforms of CAS-before-RAS Refresh Cycle t RP (3) RAS V IH V IL t CP (43) V IH V IL t HZ (22) I/O V OH V OL NOTE: WE, OE, A0–A8 = Don’t care 16258H-14 t RC (2) t RAS (1) t RP (3) t RPC (48) t CSR (47) t CHR (49) UCAS, LCAS Don’t Care V53C16258SH Rev 0.2 Aug. 1998 Undefined 13 MOSEL VITELIC Waveforms of Hidden Refresh Cycle (Read) tRC (2) VIH V IL tRCD (6) t CRP (13) UCAS, LCAS VIH V IL tASR (8) t RAH (9) ADDRESS VIH V IL VIH V IL t CAA (20) t OAC (17) OE VIH V IL t CAC (18) t LZ (21) t RAC (19) I/O VOH VOL VALID DATA ROW ADD V53C16258SH tRC (2) t RP (3) t RAS (1) t RP (3) t RAS (1) tAR (23) RAS tRSH (R)(12) t CHR (49) tCRP (13) tRAD (24) tASC (10) t CAH (11) COLUMN ADDRESS tRCS (7) WE t RRH (15) t HZ (22) t HZ (22) 16258H-15 Waveforms of Hidden Refresh Cycle (Write) t RC (2) VIH V IL t RCD (6) t CRP (13) UCAS, LCAS VIH V IL tASR (8) t RAH (9) ADDRESS VIH V IL VIH V IL VIH V IL t DS (32) VIH I/O V IL tDH (33) VALID DATA-IN ROW ADD t RC (2) tRP (3) t RAS (1) tRP (3) t RAS (1) tAR (23) RAS t RSH (12) t CHR (49) t CRP (13) tRAD (24) tASC (10) t CAH (11) COLUMN ADDRESS t WCS (27) WE t WCH (28) OE t DHR (46) 16258H-16 Don’t Care V53C16258SH Rev 0.2 Aug. 1998 Undefined 14 MOSEL VITELIC V53C16258SH Waveforms of EDO-Page-Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write) tRAS RAS V IH V IL tCSH tPC tCRP V IH V IL tAR tRAD tASR V IH V IL tRAH tASC tCAH tASC tCAH tASC tCAH tCAR tRCD tCAS tCP tCAS tPC tCP tRSH tCAS tCP tRP UCAS, LCAS ADDRESS ROW ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tRCS V IH V IL tRAC tCAC tOE V IH OE V IL tRCH tWCS tWCH WE tCAA tCAP tCAA tCAC tDS tDH tCOH I/O VOH VOL VALID DATA OUT VALID DATA OUT VALID DATA IN 16258H-17 Waveforms of Self Refresh Cycle t RP (3) RAS t RASS (57) t RPS (58) VIH V IL tRPC (48) tCP (43) tCSR (47) tCHD (60) tCHS (59) tRPC (48) UCAS, LCAS VIH V IL ADDRESS VIH V IL I/O VOH VOL OPEN WE VIH V IL OE VIH V IL 16258L 05 Don’t Care V53C16258SH Rev 0.2 Aug. 1998 Undefined 15 MOSEL VITELIC Functional Description The V53C16258SH is a CMOS dynamic RAM optimized for high data bandwidth, low power applications. It is functionally similar to a traditional dynamic RAM. The V53C16258SH reads and writes data by multiplexing an 18-bit address into a 9-bit row and a 9-bit column address. The row address is latched by the Row Address Strobe (RAS). The column address “flows through” an internal address buffer and is latched by the Column Address Strobe (CAS). Because access time is primarily dependent on a valid column address rather than the precise time that the CAS edge occurs, the delay time from RAS to CAS has little effect on the access time. V53C16258SH Extended Data Output Page Mode EDO Page operation permits all 512 columns within a selected row of the device to be randomly accessed at a high data rate. Maintaining RAS low while performing successive CAS cycles retains the row address internally and eliminates the need to reapply it for each cycle. The column address buffer acts as a transparent or flow-through latch while CAS is high. Thus, access begins from the occurrence of a valid column address rather than from the falling edge of CAS, eliminating tASC and tT from the critical timing path. CAS latches the address into the column address buffer. During EDO operation, Read, Write, Read-Modify-Write or Read-Write-Read cycles are possible at random addresses within a row. Following the initial entry cycle into Hyper Page Mode, access is tCAA or tCAP controlled. If the column address is valid prior to the rising edge of CAS, the access time is referenced to the CAS rising edge and is specified by tCAP. If the column address is valid after the rising CAS edge, access is timed from the occurrence of a valid address and is specified by tCAA. In both cases, the falling edge of CAS latches the address and enables the output. EDO provides a sustained data rate of 83 MHz for applications that require high bandwidth such as bitmapped graphics or high-speed signal processing. The following equation can be used to calculate the maximum data rate: 512 Data Rate = ---------------------------------------t RC + 511 ´ t PC Memory Cycle A memory cycle is initiated by bringing RAS low. Any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. This ensures proper device operation and data integrity. A new cycle must not be initiated until the minimum precharge time tRP/tCP has elapsed. Read Cycle A Read cycle is performed by holding the Write Enable (WE) signal High during a RAS/CAS operation. The column address must be held for a minimum specified by tAR. Data Out becomes valid only when tOAC, tRAC, tCAA and tCAC are all satisifed. As a result, the access time is dependent on the timing relationships between these parameters. For example, the access time is limited by tCAA when tRAC, tCAC and tOAC are all satisfied. Write Cycle A Write Cycle is performed by taking WE and CAS low during a RAS operation. The column address is latched by CAS. The Write Cycle can be WE controlled or CAS controlled depending on whether WE or CAS falls later. Consequently, the input data must be valid at or before the falling edge of WE or CAS, whichever occurs last. In the CAScontrolled Write Cycle, when the leading edge of WE occurs prior to the CAS low transition, the I/O data pins will be in the High-Z state at the beginning of the Write function. Ending the Write with RAS or CAS will maintain the output in the High-Z state. In the WE controlled Write Cycle, OE must be in the high state and tOED must be satisfied. Self Refresh Self Refresh mode provides internal refresh control signals to the DRAM during extended periods of inactivity. Device operation in this mode provides additional power savings and design ease by elimination of external refresh control signals. Self Refresh mode is initiated with a CAS before RAS (CBR) Refresh cycle, holding both RAS low (tRASS) and CAS low (tCHD) for a specified period. Both of these parameters are specified with minimum values to guarantee entry into Self Refresh operation. Once the device has been placed in to Self Refresh mode the CAS clock is no longer required to maintain Self Refresh operation. V53C16258SH Rev 0.2 Aug. 1998 16 MOSEL VITELIC The Self Refresh mode is terminated by returning the RAS clock to a high level for a specified (tRPS) minimum time. After termination of the Self Refresh cycle normal accesses to the device may be initiated immediately, providing that subsequent refresh cycles utilize the CAS before RAS (CBR) mode of operation. V53C16258SH Power-On After application of the VCC supply, an initial pause of 200 ms is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a RAS clock). Eight initialization cycles are required after extended periods of bias without clocks (greater than the Refresh Interval). During Power-On, the VCC current requirement of the V53C16258SH is dependent on the input levels of RAS and CAS. If RAS is low during Power-On, the device will go into an active cycle and ICC will exhibit current transients. It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges. Data Output Operation The V53C16258SH Input/Output is controlled by OE, CAS, WE and RAS. A RAS low transition enables the transfer of data to and from the selected row address in the Memory Array. A RAS high transition disables data transfer and latches the output data if the output is enabled. After a memory cycle is initiated with a RAS low transition, a CAS low transition or CAS low level enables the internal I/O path. A CAS high transition or a CAS high level disables the I/O path and the output driver if it is enabled. A CAS low transition while RAS is high has no effect on the I/O data path or on the output drivers. The output drivers, when otherwise enabled, can be disabled by holding OE high. The OE signal has no effect on any data stored in the output latches. A WE low level can also disable the output drivers when CAS is low. During a Write cycle, if WE goes low at a time in relationship to CAS that would normally cause the outputs to be active, it is necessary to use OE to disable the output drivers prior to the WE low transition to allow Data In Setup Time (tDS) to be satisfied. Table 1. V53C16258SH Data Output Operation for Various Cycle Types Cycle Type Read Cycles CAS-Controlled Write Cycle (Early Write) WE-Controlled Write Cycle (Late Write) Read-Modify-Write Cycles EDO Read Cycle EDO Write Cycle (Early Write) EDO Read-ModifyWrite Cycle RAS-only Refresh CAS-before-RAS Refresh Cycle CAS-only Cycles I/O State Data from Addressed Memory Cell High-Z OE Controlled. High OE = High-Z I/Os Data from Addressed Memory Cell Data from Addressed Memory Cell High-Z Data from Addressed Memory Cell High-Z Data remains as in previous cycle High-Z V53C16258SH Rev 0.2 Aug. 1998 17 MOSEL VITELIC Package Outlines 40-Pin Plastic SOJ 1.025 TYP. (1.035 MAX.) [26.04 TYP. (26.29 MAX.)] 40 21 V53C16258SH Unit in inches [mm] 0.400 ±0.005 [10.16 ± 0.127] 0.440 ±0.005 [11.18 ± 0.127] 1 20 0.026 MIN [0.660 MIN] 0.144 MAX [3.66 MAX] 0.010 + 0.004 – 0.002 +0.004 0.025 –0.002 +0.102 0.635 –0.051 +0.102 0.254 –0.051 0.050 ± 0.006 [1.27 ± 0.152] 0.04 [0.1] 0.018 +0.004 –0.002 +0.102 0.457 –0.051 40/44L-Pin TSOP-II 0.0047 – 0.0083 [0.119 – .211] 40 21 Unit in inches [mm] 0.017 – 0.023 [0.432 – 0.584] 0.462 – 0.470 [11.73 – 11.94] 0.396 – 0.404 [10.06 – 10.26] 1 0.0315 BSC [.8001 BSC] 0.039 – 0.047 [0.991 – 1.193] 0.721 – 0.729 [18.31 – 18.52] 0.012 – 0.016 [0.305 – 0.406] 20 0¡–5¡ 0.002 – 0.008 [0.051 – 0.203] BASE PLANE SEATING PLANE V53C16258SH Rev 0.2 Aug. 1998 18 0.368 ± 0.010 [9.35 ± 0.254] MOSEL VITELIC Notes V53C16258SH V53C16258SH Rev 0.2 Aug. 1998 19 MOSEL VITELIC U.S.A. 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 WORLDWIDE OFFICES TAIWAN 7F, NO. 102 MIN-CHUAN E. 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