V53C1664H

MOSEL VITELIC V53C1664H HIGH PERFORMANCE 64K X 16 BIT FAST PAGE MODE DUAL CAS CMOS DYNAMIC RAM HIGH PERFORMANCE Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Fast Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC) 30 30 ns 16 ns 19 ns 65 ns 35 35 ns 18 ns 21 ns 70 ns 40 40 ns 20 ns 23 ns 75 ns 45 45 ns 22 ns 25 ns 80 ns 50 50 ns 24 ns 28 ns 90 ns Features s 64K x 16-bit organization s Fast Page Mode for a sustained data rate of 53 MHz s RAS access time: 30, 35, 40, 45, 50ns s Dual CAS Inputs s Low Power Dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh s Refresh Interval: 256 cycles/4 ms s Available in 40-pin 400 mil SOJ and 40/44L-pin 400 mil TSOP-II packages s Single +5V±10% Power Supply s TTL Interface Description T he V53C1664H is a 65,536 x 16 bit high performance CMOS dynamic random access memory. The V53C1664H offers Fast Page mode with dual CAS i nputs. The V53C1664H has symmetric address, 8-bit row and 8-bit column. All inputs are TTL compatible. Fast Page Mode operation allows random access up to 256 x 16 bits, within a page, with cycle times as short as 19ns. The V53C1664H is ideally suited for a wide variety of high performance computer systems and peripheral applications. Device Usage Chart Operating Temperature Range 0°C to 70°C Package Outline K • Access Time (ns) 30 • Power 50 • T • 35 • 40 • 45 • Std. • Temperature Mark Blank V53C1664H Rev. 1.0 February 1998 1 MOSEL VITELIC 40-Pin Plastic SOJ PIN CONFIGURATION Top View Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8 NC NC WE RAS NC A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 16126H-02 V53C1664H 40/44L-Pin Plastic TSOP-II PIN CONFIGURATION Top View Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9 NC LCAS UCAS OE NC A7 A6 A5 A4 Vss Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9 Pin Names A0–A7 RAS UCAS Address Inputs Row Address Strobe Column Address Strobe/Upper Byte Control Column Address Strobe/Lower Byte Control Write Enable Output Enable Data Input, Output +5V Supply 0V Supply No Connect LCAS NC NC WE RAS NC A0 A1 A2 A3 Vcc 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 16126H-03 NC LCAS UCAS OE NC A7 A6 A5 A4 Vss WE OE I/O1–I/O16 VCC VSS NC Absolute Maximum Ratings* Ambient Temperature Under Bias ................................ –10°C to +80°C Storage Temperature (plastic) ..... –55°C to +125°C Voltage Relative to VSS .................–1.0 V to +7.0 V Data Output Current ..................................... 50 mA Power Dissipation .......................................... 1.0 W *Note: Operation above Absolute Maximum Ratings can adversely affect device reliability. TA = 25°C, VCC = 5 V ± 10%, VSS = 0 V Symbol CIN1 CIN2 COUT Parameter Address Input RAS, CAS, WE, OE Data Input/Output Typ. 3 4 5 Max. 4 5 7 Unit pF pF pF Capacitance* *Note: Capacitance is sampled and not 100% tested V53C1664H Rev. 1.0 February 1998 2 MOSEL VITELIC Block Diagram 64K x 16 OE WE UCAS LCAS RAS V53C1664H RAS CLOCK GENERATOR CAS CLOCK GENERATOR WE CLOCK GENERATOR OE CLOCK GENERATOR VCC VSS DATA I/O BUS COLUMN DECODERS Y0–Y7 I/O 1 I/O2 I/O3 I/O BUFFER SENSE AMPLIFIERS REFRESH COUNTER 256 x 16 9 A0 A1 • • • A7 I/O4 I/O 5 I/O6 I/O7 I/O8 I/O 9 I/O10 I/O11 ADDRESS BUFFERS AND PREDECODERS ROW DECODERS X0– X7 256 MEMORY ARRAY I/O12 I/O 13 I/O14 I/O15 I/O16 256 x 256 x 16 1664H-04 V53C1664H Rev. 1.0 February 1998 3 MOSEL VITELIC DC and Operating Characteristics (1-2) TA = 0°C to 70°C, VCC = 5 V ± 10%, VSS = 0 V, unless otherwise specified. Symbol ILI ILO ICC1 V53C1664H Parameter Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) VCC Supply Current, Operating Access Time V53C1664H Min. –10 Typ. Max. 10 Unit µA µA mA Test Conditions VSS ≤ VIN ≤ VCC VSS ≤ VOUT ≤ VCC RAS, CAS at VIH tRC = tRC (min.) Notes –10 10 30 35 40 45 50 200 190 180 170 160 2 1, 2 ICC2 ICC3 VCC Supply Current, TTL Standby VCC Supply Current, RAS-Only Refresh 30 35 40 45 50 mA RAS, CAS at VIH, other inputs ≥ VSS tRC = tRC (min.) 2 200 190 180 170 160 190 180 170 160 150 2 mA ICC4 VCC Supply Current, Fast Page Mode Operation 30 35 40 45 50 mA Minimum Cycle 1, 2 ICC5 VCC Supply Current, Standby Output Enable other inputs ≥ VSS VCC Supply Current, CMOS Standby mA RAS = VIH CAS = VIL RAS ≥ VCC – 0.2 V, CAS ≥ VCC – 0.2 V, All other inputs ≥ VSS 1 ICC6 1 mA VCC VIL VIH VOL VOH Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 4.5 –1 2.4 5.0 5.5 0.8 VCC + 1 0.4 V V V V V IOL = 4.2 mA IOH = –5 mA 3 3 2.4 V53C1664H Rev. 1.0 February 1998 4 MOSEL VITELIC AC Characteristics TA = 0°C to 70°C, VCC = 5 V ±10%, VSS = 0V unless otherwise noted AC Test conditions, input pulse levels 0 to 3V 30 Symbol tRAS tRC tRP tCSH tCAS tRCD tRCS tASR tRAH tASC tCAH tRSH (R) tCRP tRCH tRRH tROH tOAC tCAC tRAC tCAA tLZ tHZ tAR tRAD tRSH (W) tCWL tWCS tWCH Parameter RAS Pulse Width Read or Write Cycle Time RAS Precharge Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Read Command Setup Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time RAS Hold Time (Read Cycle) CAS to RAS Precharge Time Read Command Hold Time Referenced to CAS Read Command Hold Time Referenced to RAS RAS Hold Time Referenced to OE Access Time from OE Access Time from CAS Access Time from RAS Access Time from Column Address OE or CAS to Low-Z Output OE or CAS to High-Z Output Column Address Hold Time from RAS RAS to Column Address Delay Time RAS or CAS Hold Time in Write Cycle Write Command to CAS Lead Time Write Command Setup Time Write Command Hold Time 0 0 26 5 35 40 45 50 V53C1664H Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes 30 65 25 30 5 15 0 0 5 0 5 10 5 0 20 75K 35 70 25 35 6 16 0 0 6 0 5 10 5 0 24 75K 40 75 25 40 7 17 0 0 7 0 5 10 5 0 28 75K 45 80 25 45 8 18 0 0 8 0 6 10 5 0 32 75K 50 90 30 50 9 19 0 0 9 0 7 10 5 0 36 75K ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 4 0 0 0 0 0 ns 5 6 7 8 9 10 ns 10 10 30 16 11 11 35 18 12 12 40 20 13 13 45 22 14 14 50 24 ns ns ns ns 12 6,7,14 6, 8, 9 6,7,10 0 0 28 6 0 0 30 6 0 0 35 7 0 0 40 8 ns ns ns 16 16 10 14 11 17 12 20 13 23 14 26 ns 11 10 10 10 10 10 ns 10 11 12 13 14 ns 0 5 0 5 0 5 0 6 0 7 ns ns 12, 13 V53C1664H Rev. 1.0 February 1998 5 MOSEL VITELIC AC Characteristics (Cont’d) 30 Symbol tWP tWCR tRWL tDS tDH tWOH tOED tRWC tRRW tCWD tRWD tCRW tAWD tPC tCP tCAR tCAP tDHR tCSR tRPC tCHR tPCM tT tREF Parameter Write Pulse Width Write Command Hold Time from RAS Write Command to RAS Lead Time Data in Setup Time Data in Hold Time Write to OE Hold Time OE to Data Delay Time Read-Modify-Write Cycle Time Read-Modify-Write Cycle RAS Pulse Width CAS to WE Delay RAS to WE Delay in ReadModify-Write Cycle CAS Pulse Width (RMW) Col. Address to WE Delay Fast Page Mode Read or Write Cycle Time CAS Precharge Time Column Address to RAS Setup Time Access Time from Column Precharge Data in Hold Time Referenced to RAS CAS Setup Time CAS- before-RAS Refresh RAS to CAS Precharge Time CAS Hold Time CAS-beforeRAS Refresh Fast Page Mode Read-Modify-Write Cycle Time Transition Time (Rise and Fall) Refresh Interval (256 Cycles) 26 35 40 45 50 V53C1664H Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes 5 26 5 28 5 30 6 35 7 40 ns ns 10 11 12 13 14 ns 0 5 5 5 100 65 0 5 5 5 105 70 0 5 6 6 110 75 0 6 7 7 115 80 0 7 8 8 130 87 ns ns ns ns ns ns 14 14 14 14 26 50 28 54 30 58 32 62 34 68 ns ns 12 12 44 32 19 46 35 21 48 38 23 50 41 25 52 42 28 ns ns ns 12 3 16 4 18 5 20 6 22 7 24 ns ns 19 21 23 25 27 ns 7 28 30 35 40 ns 10 10 10 10 10 ns 0 7 0 8 0 8 0 10 0 12 ns ns 56 58 60 65 70 ns 1.5 50 4 1.5 50 4 1.5 50 4 1.5 50 4 1.5 50 4 ns ms 15 17 Notes: 1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the output open. V53C1664H Rev. 1.0 February 1998 6 MOSEL VITELIC V53C1664H 2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two transitions per address cycle in Fast Page Mode. 3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to –1.0 V for a period not to exceed 20 ns. All AC parameters are measured with VIL (min.) ≥ VSS and VIH (max.) ≤ VCC. 4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA (max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC. 5. Either tRRH or tRCH must be satisified for a Read Cycle to occur. 6. Measured with a load equivalent to one TTL input and 50 pF. 7. Access time is determined by the longest of tCAA, tCAC and tCAP. 8. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD exceeds tRAD (max.). 9. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD exceeds tRCD (max.). 10. Assumes that tRAD ≥ tRAD (max.). 11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC. 12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 13. tWCS (min.) must be satisfied in an Early Write Cycle. 14. tDS and tDH are referenced to the latter occurrence of CAS or WE. 15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns. 16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent). 17. An initial 200 µs pause and 8 RAS-containing cycles are required when exiting an extended period of bias without clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval. V53C1664H Rev. 1.0 February 1998 7 MOSEL VITELIC Truth Table Function Standby Read: Word Read: Lower Byte V53C1664H RAS H L L LCAS H L L UCAS H L H WE X H H OE X L L ADDRESS X ROW/COL ROW/COL High-Z Data Out I/O Notes Lower Byte, Data-Out Upper Byte, High-Z Lower Byte, High-Z Upper Byte, Data-Out Data-In Lower Byte, Data-In Upper Byte, High-Z Lower Byte, High-Z Upper Byte, Data-In Data-Out, Data-In Data-Out Data-In Data-Out, Data-In Data-Out High-Z High-Z 3 1,2 2 2 1,2 2 Read: Upper Byte L H L H L ROW/COL Write: Word (Early-Write) Write: Lower Byte (Early) L L L L L H L L X X ROW/COL ROW/COL Read: Upper Byte (Early) L H L L H→L H L H→L H X X X L→ H L X L→H L X X ROW/COL Read-Write Page-Mode Read Page-Mode Write Page-Mode Read-Write Hidden Refresh Read RAS-Only Refresh CBR Refresh L L L L L→H→L L H→L L H→L H→L H→L L H L L H→L H→L H→L L H L ROW/COL COL COL COL ROW/COL ROW X Notes: 1. Byte Write cycles LCAS or UCAS active. 2. Byte Read cycles LCAS or UCAS active. 3. Only one of the two CAS must be active (LCAS or UCAS). V53C1664H Rev. 1.0 February 1998 8 MOSEL VITELIC Waveforms of Read Cycle t RC t RAS RAS VIH VIL t CSH t CRP UCAS, LCAS VIH VIL t ASR ADDRESS VIH VIL ROW ADDRESS t RAD t RAH t ASC COLUMN ADDRESS t CAR t RCS WE VIH VIL t CAA OE VIH VIL t CAC t RAC I/O VOH VOL t LZ t HZ VALID DATA-OUT t OAC t ROH t RRH t RCH t CAH t RCD t RSH (R) t CAS t AR t RP V53C1664H t CRP t HZ 1664H-05 Waveforms of Early Write Cycle t RC t RAS RAS V IH V IL t CRP UCAS, LCAS V IH V IL t CAR t RAH t ASR ADDRESS V IH V IL ROW ADDRESS t RAD t CWL V IH V IL t WCR t RWL (31) OE V IH V IL t DHR t DS I/O V IH V IL t DH VALID DATA-IN HIGH-Z 1664H-06 t RP t AR t CSH t RCD t RSH (W) t CAS t CRP t CAH t ASC COLUMN ADDRESS t WCH t WP t WCS WE Don’t Care V53C1664H Rev. 1.0 February 1998 Undefined 9 MOSEL VITELIC Waveforms of OE-Controlled Write Cycle tRC t RAS RAS VIH V IL t CRP V IH UCAS, LCAS V IL t RAD t RAH t ASR ADDRESS V IH V IL ROW ADDRESS t ASC COLUMN ADDRESS t CWL t RWL tWP WE V IH V IL t WOH OE V IH V IL t OED t DS I/O V IH V IL VALID DATA-IN t DH t CAR tCAH t CSH tRCD t RSH (W) t CAS t AR t RP V53C1664H t CRP 1664H-07 Waveforms of Read-Modify-Write Cycle tRWC tRRW RAS VIH VIL t CSH t CRP VIH UCAS, LCAS VIL tRAH t ASR ADDRESS VIH VIL ROW ADDRESS tRAD t RWD WE VIH VIL VIH VIL t CAC t RAC I/O VIH VOH VIL VOL tLZ VALID DATA-OUT t OED t HZ t DS VALID DATA-IN 1664H-08 t RP tAR t RCD t RSH (W) t CRW t t ASC COLUMN ADDRESS tAWD t CWD tRWL t CWL t WP t CRP CAH tCAA t OAC OE t DH Don’t Care V53C1664H Rev. 1.0 February 1998 Undefined 10 MOSEL VITELIC Waveforms of Fast Page Mode Read Cycle RAS V IH V IL t CRP UCAS, LCAS V IH V IL t RAH t ASC ROW ADDRESS t RCS WE V IH V IL t CAA t OAC OE V IH V IL t RAC t CAC t LZ t HZ t CAC t HZ t LZ I/O V OH V OL VALID DATA OUT VALID DATA OUT t LZ tCAC t HZ t HZ t CAP t OAC t CAA t OAC t CSH t ASC t CAR t CAH COLUMN ADDRESS t RCS t RCD t PC t CAS t CP t RSH (R) t CAS t CAS tCRP t AR t RASP V53C1664H t RP t ASR ADDRESS V IH V IL t CAH COLUMN ADDRESS t RCH t CAH COLUMN ADDRESS t RCS t RCH t RRH tHZ tHZ VALID DATA OUT 1664H-09 Waveforms of Fast Page Mode Write Cycle t AR RAS V IH V IL t CRP t RCD UCAS, LCAS V IH V IL t RAH tASR ADDRESS V IH V IL t RAD t WCS t WP WE V IH V IL VIH V IL t DS I/O V IH V IL VALID DATA IN ROW ADD COLUMN ADDRESS t RP t RASP t PC t CAS t CP t CAS t RSH (W) t CAS t CRP t CSH t ASC COLUMN ADDRESS t CAH t CAH tASC t CAR t CAH COLUMN ADDRESS t CWL t WCH t WCS t CWL t WCH t WP t WCS t CWL t RWL t WCH t WP OE t DH t DS VALID DATA IN t DS t DH VALID DATA IN t DH OPEN 1664H-10 OPEN Don’t Care V53C1664H Rev. 1.0 February 1998 Undefined 11 MOSEL VITELIC Waveforms of Fast Page Mode Read-Write Cycle RAS VIH V IL V53C1664H t RASP t RCD t CSH t PCM t CAS t RSH (W) t CAS t CAS t RP t CP t CRP V UCAS, LCAS V IH IL t RAD t RAH t ASR t ASC t CAH COLUMN ADDRESS t ASC COLUMN ADDRESS t CAH t ASC t CAR t CAH COLUMN ADDRESS V ADDRESS V IH IL ROW ADD t RCS V WE V IH IL t RWD t CWD t CWL t CWD t CWL t CWD t RWL t CWL t CAA t OAC V OE V IH IL t AWD t WP t OAC t AWD t AWD t OAC t WP t WP t CAP t OED t RAC t CAC t HZ t DS I/O V I/OH V I/OL t LZ OUT IN OUT t CAA t CAC t DH t OED t HZ t DS IN t CAP t CAA t CAC t DH t OED t HZ t DS t DH OUT IN t LZ t LZ 1664H-11 Waveforms of RAS-Only Refresh Cycle t RC V IH V IL t CRP UCAS, LCAS V IH V IL t ASR ADDRESS V IH V IL NOTE: ROW ADDR 1664H-12 t RAS t RP RAS t RAH WE, OE = Don’t care Don’t Care V53C1664H Rev. 1.0 February 1998 Undefined 12 MOSEL VITELIC Waveforms of CAS-before-RAS Refresh Counter Test Cycle t RAS RAS V IH V IL t CSR UCAS, LCAS V IH V IL V IH V IL READ V IH V IL t ROH t OAC OE V IH V IL t LZ I/O V IH V IL WRITE V IH V IL V IH V IL t I/O V IH V IL DS V53C1664H t RP t CHR t CP t RSH (W) t CAS ADDRESS t RCS t RRH t RCH WE t HZ t HZ DOUT t RWL t CWL t WCH t WCS WE OE t DH D IN 1664H-13 Waveforms of CAS-before-RAS Refresh Cycle t RC t RP RAS VIH VIL t CP t CSR CAS VIH V IL t HZ I/O VOH VOL NOTE: WE, OE, A 0 –A 8 = Don’t care 1664H-14 t RAS t RP t RPC t CHR Don’t Care V53C1664H Rev. 1.0 February 1998 Undefined 13 MOSEL VITELIC Waveforms of Hidden Refresh Cycle (Read) t RC V IH V IL t RCD t CRP UCAS, LCAS V IH V IL t ASR t RAH ADDRESS V IH V IL V IH V IL t CAA t OAC OE V IH V IL t CAC t LZ t RAC V OH I/O V OL VALID DATA t HZ t HZ ROW ADD COLUMN ADDRESS V53C1664H t RC tRP t RAS t RP t RAS t AR RAS t RSH (R) t CHR t CRP t RAD t ASC t CAH t RCS WE t RRH 1664H-15 Waveforms of Hidden Refresh Cycle (Write) t RC V IH RAS V IL t RCD t CRP UCAS, LCAS V IH V IL t ASR t RAH ADDRESS V IH V IL V IH V IL V IH OE V IL tDS V IH I/O V IL t DH VALID DATA-IN ROW ADD COLUMN ADDRESS t RC t RP t RAS t RP t RAS t AR t RSH t CHR t CRP t RAD t ASC t CAH t WCS WE t WCH t DHR 1664H-16 Don’t Care V53C1664H Rev. 1.0 February 1998 Undefined 14 MOSEL VITELIC Functional Description The V53C1664H is a CMOS dynamic RAM optimized for high data bandwidth, low power applications. It is functionally similar to a traditional dynamic RAM. The V53C1664H reads and writes data by multiplexing an 16-bit address into a 8-bit row and a 8-bit column address. The row address is latched by the Row Address Strobe (RAS). The column address “flows through” an internal address buffer and is latched by the Column Address Strobe (CAS). Because access time is primarily dependent on a valid column address rather than the precise time that the CAS edge occurs, the delay time from RAS to CAS has little effect on the access time. V53C1664H whether WE or CAS falls later. Consequently, the input data must be valid at or before the falling edge of WE or CAS, whichever occurs last. In the CAS-controlled Write Cycle, when the leading edge of WE occurs prior to the CAS low transition, the I/O data pins will be in the High-Z state at the beginning of the Write function. Ending the Write with RAS or CAS will maintain the output in the High-Z state. In the WE controlled Write Cycle, OE must be in the high state and tOED must be satisfied. Refresh Cycle To retain data, 256 Refresh Cycles are required in each 4 ms period. There are two ways to refresh the memory: 1. By clocking each of the 256 row addresses (A0 through A7) with RAS at least once every 4 ms. Any Read, Write, Read-Modify-Write or RASonly cycle refreshes the addressed row. 2. Using a CAS-before-RAS Refresh Cycle. If CAS makes a transition from low to high to low after the previous cycle and before RAS falls, CASb e f o r e -R A S r e f r e s h i s a c t i v a t e d . T h e V53C1664H uses the output of an internal 9-bit counter as the source of row addresses and ignore external address inputs. CAS-before-RAS is a “refresh-only” mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. A CAS -before-RAS c ounter test mode is provided to ensure reliable operation of the internal refresh counter. Memory Cycle A memory cycle is initiated by bringing RAS low. Any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. This ensures proper device operation and data integrity. A new cycle must not be initiated until the minimum precharge time tRP /t CP h as elapsed. Read Cycle A Read cycle is performed by holding the Write Enable (WE ) signal High during a RAS /CAS operation. The column address must be held for a minimum specified by tAR. Data Out becomes valid only when tOAC , t RAC , t CAA a nd t CAC a re all satisifed. As a result, the access time is dependent on the timing relationships between these parameters. For example, the access time is limited by tCAA when tRAC, tCAC and tOAC are all satisfied. Write Cycle A Write Cycle is performed by taking WE and CAS l ow during a RAS o peration. The column address is latched by CAS. The Write Cycle can be WE c ontrolled or CAS c ontrolled depending on V53C1664H Rev. 1.0 February 1998 15 MOSEL VITELIC Fast Page Mode Operation Fast Page Mode operation permits all 256 columns within a selected row of the device to be randomly accessed at a high data rate. Maintaining RAS low while performing successive CAS cycles retains the row address internally and eliminates the need to reapply it for each cycle. The column address buffer acts as a transparent or flowthrough latch while CAS i s high. Thus, access begins from the occurrence of a valid column address rather than from the falling edge of CAS, eliminating tASC and tT from the critical timing path. CAS latches the address into the column address buffer and acts as an output enable. During Fast Page Mode operation, Read, Write, Read-ModifyWrite or Read-Write-Read cycles are possible at random addresses within a row. Following the initial entry cycle into Fast Page Mode, access is tCAA or tCAP controlled. If the column address is valid prior to the rising edge of CAS , the access time is referenced to the CAS r ising edge and is specified by tCAP. If the column address is valid after the rising CAS edge, access is timed from the occurrence of a valid address and is specified by tCAA . In both cases, the falling edge of CAS latches the address and enables the output. Fast Page Mode provides sustained data rates up to 53 MHz for applications that require high data rates such as bit-mapped graphics or high-speed signal processing. The following equation can be used to calculate the maximum data rate: 256 Data Rate = ---------------------------------------t RC + 255 × t PC V53C1664H also disable the output drivers when CAS is low. During a Write cycle, if WE goes low at a time in relationship to CAS that would normally cause the outputs to be active, it is necessary to use OE to disable the output drivers prior to the WE l ow transition to allow Data In Setup Time (tDS) to be satisfied. Power-On After application of the VCC s upply, an initial pause of 200 µs is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a RAS clock). Eight initialization cycles are required after extended periods of bias without clocks (greater than the Refresh Interval). During Power-On, the VCC current requirement of the V53C1664H is dependent on the input levels of RAS and CAS. If RAS is low during Power-On, the device will go into an active cycle and IDD will exhibit current transients. It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges. Table 1. V53C1664H Data Output Operation for Various Cycle Types Cycle Type Read Cycles I/O State Data from Addressed Memory Cell High-Z CAS-Controlled Write Cycle (Early Write) WE-Controlled Write Cycle (Late Write) OE Controlled. High OE = High-Z I/Os Data from Addressed Memory Cell Data from Addressed Memory Cell High-Z Data Output Operation The V53C1664H Input/Output is controlled by OE, CAS , WE a nd RAS . A RAS l ow transition enables the transfer of data to and from the selected row address in the Memory Array. A RAS high transition disables data transfer and latches the output data if the output is enabled. After a memory cycle is initiated with a RAS low transition, a CAS low transition or CAS low level enables the internal I/O path. A CAS high transition or a CAS high level disables the I/O path and the output driver if it is enabled. A CAS low transition while RAS is high has no effect on the I/O data path or on the output drivers. The output drivers, when otherwise enabled, can be disabled by holding OE high. The OE s ignal has no effect on any data stored in the output latches. A WE low level can Read-Modify-Write Cycles Fast Page Mode Read Fast Page Mode Write Cycle (Early Write) Fast Page Mode Read-ModifyWrite Cycle RAS-only Refresh CAS-before-RAS Refresh Cycle Data from Addressed Memory Cell High-Z Data remains as in previous cycle High-Z CAS-only Cycles Package Outlines V53C1664H Rev. 1.0 February 1998 16 MOSEL VITELIC 40-Pin Plastic SOJ 1.025 TYP. (1.035 MAX.) [26.04 TYP. (26.29 MAX.)] 40 21 V53C1664H Unit in inches [mm] 0.400 ±0.005 [10.16 ± 0.127] 0.440 ±0.005 [11.18 ± 0.127] 1 20 0.026 MIN [0.660 MIN] 0.144 MAX [3.66 MAX] 0.010 + 0.004 – 0.002 +0.004 0.025 –0.002 +0.102 0.635 –0.051 +0.102 0.254 –0.051 0.050 ± 0.006 [1.27 ± 0.152] 0.04 [0.1] 0.018 +0.004 –0.002 +0.102 0.457 –0.051 40/44L-Pin TSOP-II 0.0047 – 0.0083 [0.119 – .211] 40 21 Unit in inches [mm] 0.017 – 0.023 [0.432 – 0.584] 0.462 – 0.470 [11.73 – 11.94] 0.396 – 0.404 [10.06 – 10.26] 1 0.0315 BSC [.8001 BSC] 0.039 – 0.047 [0.991 – 1.193] 0.721 – 0.729 [18.31 – 18.52] 0.012 – 0.016 [0.305 – 0.406] 20 0°–5° 0.002 – 0.008 [0.051 – 0.203] BASE PLANE SEATING PLANE V53C1664H Rev. 1.0 February 1998 17 0.368 ± 0.010 [9.35 ± 0.254] MOSEL VITELIC U.S.A. 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 WORLDWIDE OFFICES TAIWAN 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 1 CREATION ROAD I SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-578-3344 FAX: 886-3-579-2838 V53C1664H GERMANY (CONTINENTAL EUROPE & ISRAEL ) 71083 HERRENBERG BENZSTR. 32 GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22 JAPAN WBG MARINE WEST 25F 6, NAKASE 2-CHOME MIHAMA-KU, CHIBA-SHI CHIBA 261-71 PHONE: 81-43-299-6000 FAX: 81-43-299-6555 HONG KONG 19 DAI FU STREET TAIPO INDUSTRIAL ESTATE TAIPO, NT, HONG KONG PHONE: 852-2665-4883 FAX: 852-2664-7535 IRELAND & UK BLOCK A UNIT 2 BROOMFIELD BUSINESS PARK MALAHIDE CO. DUBLIN, IRELAND PHONE: +353 1 8038020 FAX: +353 1 8038049 U.S. SALES OFFICES NORTHWESTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 SOUTHWESTERN SUITE 200 5150 E. PACIFIC COAST HWY. LONG BEACH, CA 90804 PHONE: 562-498-3314 FAX: 562-597-2174 CENTRAL & SOUTHEASTERN 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 972-690-1402 FAX: 972-690-0341 NORTHEASTERN SUITE 436 20 TRAFALGAR SQUARE NASHUA, NH 03063 PHONE: 603-889-4393 FAX: 603-889-9347 © Copyright 1998, MOSEL VITELIC Inc. 2/98 Printed in U.S.A. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. 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