V53C8126

MOSEL VITELIC V53C8126H ULTRA-HIGH PERFORMANCE, 128K X 8 BIT FAST PAGE MODE CMOS DYNAMIC RAM 35 35 ns 18 ns 21 ns 70 ns V53C8126H PRELIMINARY HIGH PERFORMANCE Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Fast Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC) 40 40 ns 20 ns 23 ns 75 ns 45 45 ns 22 ns 25 ns 80 ns 50 50 ns 24 ns 28 ns 90 ns Features s 128K x 8-bit organization s RAS access time: 35, 40, 45, 50 ns s Fast Page Mode supports sustained I/O data rates up to 40 MHz s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh capability s Refresh Interval • V53C8126H – 512 cycles/8 ms s Available in 26/24 pin 300 mil SOJ and 28 pin TSOP package Description The V53C8126H is a high speed 131,072 x 8 bit CMOS dynamic random access memory. The V53C8126H offers a combination of features: Fast Page Mode for high data bandwidth, fast usable speed, CMOS standby current. All inputs and outputs are TTL compatible. Input and output capacitances are significantly lowered to allow increased system performance. Fast Page Mode operation allows random access of up to 256 columns (x8) bits within a row with cycle times as short as 21 ns. Because of static circuitry, the CAS clock is not in the critical timing path. The flowthrough column address latches allow address pipelining while relaxing many critical system timing requirements for fast usable speed. These features make the V53C8126H ideally suited for graphics, digital signal processing and high performance peripherals. Device Usage Chart Operating Temperature Range 0°C to 70 °C Package Outline K T 35 Access Time (ns) 40 45 50 Power Std. Temperature Mark Blank • • • • 1 • • • V53C8126H Rev. 1.1 July 1997 MOSEL VITELIC V 5 3 C 8 1 2 6 H V53C8126H FAMILY DEVICE PKG SPEED ( t RAC) TEMP. PWR. BLANK (0°C to 70°C) BLANK (NORMAL) K (SOJ) T (TSOP) Description SOJ Pkg. K Pin Count 26/24 35 40 45 50 (35 ns) (40 ns) (45 ns) (50 ns) 8126H 01 26/24 Lead SOJ PIN CONFIGURATION Top View VSS I/O1 I/O2 I/O3 I/O4 WE RAS A0 A1 A2 A3 VCC 1 2 3 4 5 6 26 25 24 23 22 21 28 Lead TSOP PIN CONFIGURATION Top View CAS I/O5 I/O6 I/O7 I/O8 VSS VSS NC I/O1 I/O2 I/O3 I/O4 NC WE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 8125H 03 VSS I/O8 I/O7 I/O6 I/O5 CAS OE A8 (Row Add. only) A7 A6 A5 A4 8 9 10 11 12 13 19 18 17 16 15 14 8126H 02 OE A8 A7 A6 A5 A4 NC VCC NC A3 A2 A1 A0 RAS Pin Names A0–A8 RAS CAS WE OE I/O1–I/O8 VCC VSS NC Address Inputs (A8: Row Address only) Row Address Strobe Column Address Strobe Write Enable Output Enable Data Input, Output +5V Supply 0V Supply No Connect V53C8126H Rev. 1.1 July 1997 2 MOSEL VITELIC Absolute Maximum Ratings* Ambient Temperature Under Bias ............................. –10°C to +80°C Storage Temperature (plastic) .... –55°C to +125°C Voltage Relative to VSS .................... –1.0 V to +7.0 V Data Output Current .................................... 50 mA Power Dissipation ......................................... 1.0 W *Note: Operation above Absolute Maximum Ratings can adversely affect device reliability. V53C8126H Capacitance* TA = 25°C, VCC = 5 V ± 10%, VSS = 0 V Symbol CIN1 CIN2 COUT Parameter Address Input RAS, CAS, WE, OE Data Input/Output Typ. Max. 3 4 5 4 5 7 Unit pF pF pF * Note: Capacitance is sampled and not 100% tested Block Diagram 128K x 8 OE WE CAS RAS Fast Page Mode RAS CLOCK GENERATOR CAS CLOCK GENERATOR WE CLOCK GENERATOR OE CLOCK GENERATOR VCC VSS DATA I/O BUS COLUMN DECODERS Y0–Y7 I/O 1 I/O2 I/O3 I/O BUFFER SENSE AMPLIFIERS REFRESH COUNTER 256 x 8 9 A0 A1 • • • A7 A8 I/O4 I/O 5 I/O6 I/O7 I/O8 ADDRESS BUFFERS AND PREDECODERS X0–X8 ROW DECODERS 512 MEMORY ARRAY 8126H 04 V53C8126H Rev. 1.1 July 1997 3 MOSEL VITELIC DC and Operating Characteristics (1-2) TA = 0°C to 70°C, VCC = 5 V ± 10%, VSS = 0 V, unless otherwise specified. V53C8126H Symbol Parameter Access Time Min. –10 V53C8126H Typ. Max. 10 Unit Test Conditions µA VSS ≤ VIN ≤ VCC Notes ILI Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) 35 ILO –10 10 µA VSS≤ VOUT ≤ VCC RAS, CAS at VIH 160 150 145 135 RAS, CAS at VIH other inputs ≥ VSS mA tRC = tRC (min.) 1, 2 ICC1 VCC Supply Current, Operating 40 45 50 ICC2 VCC Supply Current, TTL Standby VCC Supply Current, 35 40 45 50 4 160 150 145 135 95 90 85 80 2 mA ICC3 RAS-Only Refresh mA tRC = tRC (min.) 2 ICC4 VCC Supply Current, Fast Page Mode Operation 35 40 45 50 mA Minimum Cycle 1, 2 ICC5 VCC Supply Current, Standby, Output Enabled VCC Supply Current, CMOS Standby mA RAS=VIH, CAS=VIL other inputs ≥ VSS RAS ≥ VCC – 0.2 V, CAS ≥ VCC – 0.2 V, All other inputs ≥ VSS 1 ICC6 1 mA VIL VIH VOL VOH Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage –1 2.4 0.8 VCC+1 0.4 V V V V IOL = 4.2 mA IOH = –5 mA 3 3 2.4 V53C8126H Rev. 1.1 July 1997 4 MOSEL VITELIC AC Characteristics TA = 0°C to 70°C, VCC = 5 V ±10%, VSS = 0V unless otherwise noted AC Test conditions, input pulse levels 0 to 3V JEDEC Symbol tRL1RH1 tRL2RL2 tRH2RL2 tRL1CH1 tCL1CH1 tRL1CL1 tWH2CL2 tAVRL2 tRL1AX tAVCL2 tCL1AX 35 Symbol tRAS tRC tRP tCSH tCAS tRCD tRCS tASR tRAH tASC tCAH Parameter RAS Pulse Width Read or Write Cycle Time RAS Precharge Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Read Command Setup Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time RAS Hold Time (Read Cycle) CAS to RAS Precharge Time Read Command Hold Time Referenced to CAS Read Command Hold Time Referenced to RAS RAS Hold Time Referenced to OE Access Time from OE Access Time from CAS Access Time from RAS Access Time from Column Address OE or CAS to Low-Z Output OE or CAS to High-Z Output Column Address Hold Time from RAS RAS to Column Address Delay Time RAS or CAS Hold Time in Write Cycle Write Command to CAS Lead Time 0 0 28 6 40 45 50 V53C8126H # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Min. Max. Min. Max. Min. Max. Min. Max. Unit 35 70 25 35 12 16 0 0 6 0 4 12 5 0 23 75K 40 75 25 40 12 17 0 0 7 0 5 12 5 0 28 75K 45 80 25 45 13 18 0 0 8 0 6 13 5 0 32 75K 50 90 30 50 14 19 0 0 9 0 7 14 5 0 36 75K ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 4 tCL1RH1(R) tRSH (R) tCH2RL2 tCH2WX tCRP tRCH 5 15 tRH2WX tRRH 0 0 0 0 ns 5 16 tOEL1RH2 tROH 8 8 9 10 ns 17 18 19 20 tGL1QV tCL1QV tRL1QV tAVQV tOAC tCAC tRAC tCAA 12 12 35 18 12 12 40 20 13 13 45 22 14 14 50 24 ns ns ns ns 6, 7 6, 8, 9 6, 7, 10 21 22 23 tCL1QX tCH2QZ tRL1AX tLZ tHZ tAR 0 0 30 6 0 0 35 7 0 0 40 8 ns ns ns 16 16 24 tRL1AV tRAD 11 17 12 20 13 23 14 26 ns 11 25 tCL1RH1(W) tRSH (W) 12 12 13 14 ns 26 tWL1CH1 tCWL 12 12 13 14 ns V53C8126H Rev. 1.1 July 1997 5 MOSEL VITELIC AC Characteristics (Cont'd) JEDEC Symbol tWL1CL2 tCL1WH1 tWL1WH1 tRL1WH1 35 Symbol tWCS tWCH tWP tWCR Parameter Write Command Setup Time Write Command Hold Time Write Pulse Width Write Command Hold Time from RAS Write Command to RAS Lead Time Data in Setup Time Data in Hold Time Write to OE Hold Time OE to Data Delay Time Read-Modify-Write Cycle Time Read-Modify-Write Cycle RAS Pulse Width CAS to WE Delay RAS to WE Delay in Read-Modify-Write Cycle CAS Pulse Width (RMW) Col. Address to WE Delay Fast Page Mode Read or Write Cycle Time CAS Precharge Time Column Address to RAS Setup Time Access Time from Column Precharge Data in Hold Time Referenced to RAS CAS Setup Time CAS-before-RAS Refresh RAS to CAS Precharge Time CAS Hold Time CAS-before-RAS Refresh Fast Page Mode ReadModify-Write Cycle Time 28 40 45 50 V53C8126H # 27 28 29 30 Min. Max. Min. Max. Min. Max. Min. Max. Unit 0 5 5 28 0 5 5 30 0 6 6 35 0 7 7 40 ns ns ns ns Notes 12, 13 31 tWL1RH1 tRWL 12 12 13 14 ns 32 33 34 35 36 tDVWL2 tWL1DX tWL1GL2 tGH2DX tRL2RL2 (RMW) tDS tDH tWOH tOED tRWC 0 4 5 5 105 0 5 6 6 110 0 6 7 7 115 0 7 8 8 130 ns ns ns ns ns 14 14 14 14 37 tRL1RH1 (RMW) tRRW 70 75 80 87 ns 38 39 tCL1WL2 tRL1WL2 tCWD tRWD 28 54 30 58 32 62 34 68 ns ns 12 12 40 41 42 tCL1CH1 tAVWL2 tCL2CL2 tCRW tAWD tPC 46 35 21 48 38 23 50 41 25 52 42 28 ns ns ns 12 43 44 tCH2CL2 tAVRH1 tCP tCAR 4 18 5 20 6 22 7 24 ns ns 45 tCH2QV tCAP 20 22 24 27 ns 7 46 tRL1DX tDHR 30 35 40 ns 47 tCL1RL2 tCSR 10 10 10 10 ns 48 49 tRH2CL2 tRL1CH1 tRPC tCHR 0 8 0 8 0 10 0 12 ns ns 50 tCL2CL2 (RMW) tPCM 58 60 65 70 ns V53C8126H Rev. 1.1 July 1997 6 MOSEL VITELIC AC Characteristics (Cont'd) JEDEC Symbol tT 35 Symbol tT tREF Parameter Transition Time (Rise and Fall) Refresh Interval (512 Cycles) 40 45 50 V53C8126H # Min. Max. Min. Max. Min. Max. Min. Max. Unit 3 50 8 3 50 8 3 50 8 3 50 8 ns ms Notes 15 17 V53C8126H Rev. 1.1 July 1997 7 MOSEL VITELIC Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. V53C8126H ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the output open. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two transitions per address cycle in Fast Page Mode. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to –1.0 V for a period not to exceed 20 ns. All AC parameters are measured with VIL (min.) ≥ VSS and VIH (max.) ≤ VCC. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA (max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC. Either tRRH or tRCH must be satisified for a Read Cycle to occur. Measured with a load equivalent to two TTL inputs and 50 pF. Access time is determined by the longest of tCAA, tCAC and tCAP. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD exceeds tRAD (max.). Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD exceeds tRCD (max.). 10. Assumes that tRAD ≥ tRAD (max.). 11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC. 12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 13. tWCS (min.) must be satisfied in an Early Write Cycle. 14. tDS and tDH are referenced to the latter occurrence of CAS or WE. 15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 5 ns. 16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent). 17. An initial 200 µs pause and 8 RAS-containing cycles are required when exiting an extended period of bias without clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval. V53C8126H Rev. 1.1 July 1997 8 MOSEL VITELIC Waveforms of Read Cycle t RC (2) t RAS (1) RAS VIH VIL t CSH (4) t CRP (13) CAS VIH VIL t ASR (8) ADDRESS VIH VIL ROW ADDRESS t RAD (24) t RAH (9) t ASC (10) COLUMN ADDRESS t CAR (44) t RCS (7) WE VIH VIL t CAA (20) OE VIH VIL t CAC (18) t RAC (19) I/O VOH VOL t LZ (21) t HZ (22) VALID DATA-OUT t OAC (17) t ROH (16) t RRH (15) t CAH (11) t RCD (6) t RSH (R)(12) t CAS (5) t AR (23) t RP (3) V53C8126H t CRP (13) t RCH (14) t HZ (22) 676 01 Waveforms of Early Write Cycle t RC (2) t RAS (1) RAS V IH V IL t CSH (4) t CRP (13) V IH CAS V IL t RAH (9) t ASR (8) ADDRESS V IH V IL ROW ADDRESS t RAD (24) t CWL (26) V IH V IL t WCR (30) t RWL (31) OE V IH V IL t DHR (46) t DS (32) I/O V IH V IL t DH (33) VALID DATA-IN HIGH-Z 676 02 t RP (3) t AR (23) t RCD (6) t RSH (W)(25) t CAS (5) t CRP (13) t CAR (44) t CAH (11) t ASC (10) COLUMN ADDRESS t WCH (28) t WP (29) t WCS (27) WE V53C8126H Rev. 1.1 July 1997 9 MOSEL VITELIC Waveforms of OE-Controlled Write Cycle t RC (2) t RAS (1) RAS V IH V IL t CRP (13) CAS V IH V IL t RAD (24) t RAH (9) t ASR (8) ADDRESS V IH V IL ROW ADDRESS t ASC (10) COLUMN ADDRESS t CWL (26) t RWL (31) t WP (29) WE V IH V IL t WOH (34) OE V IH V IL t OED (35) V IH V IL t DH (33) t DS (32) VALID DATA-IN t CAR (44) t CAH (11) t CSH (4) t RCD (6) t RSH (W)(12) t CAS (5) t AR (23) t RP (3) V53C8126H t CRP (13) I/O 676 03 Waveforms of Read-Modify-Write Cycle t RWC (36) tRRW (37) RAS VIH VIL t CSH (4) t CRP (13) VIH CAS VIL t RAH (9) t ASR (8) ADDRESS VIH VIL ROW ADDRESS t RAD (24) t RWD (39) WE VIH VIL VIH VIL t OED (35) t CAC (18) t RAC (19) I/O VIH VIL VOH VOL t LZ (21) VALID DATA-OUT t HZ (22) t DS (32) VALID DATA-IN 675 04 t RP (3) t AR (23) t RCD (6) t RSH (W)(25) t CRW (40) t t ASC (10) COLUMN ADDRESS t AWD (41) t CWD (38) t RWL (31) t CWL (26) t CRP (13) CAH (11) t WP (29) t CAA (20) t OAC (17) OE t DH (33) V53C8126H Rev. 1.1 July 1997 10 MOSEL VITELIC Waveforms of Fast Page Mode Read Cycle RAS V IH V IL t RCD (6) t CRP (13) CAS V IH V IL t RAH (9) t CSH (4) t ASC (10) t CAH (11) COLUMN ADDRESS COLUMN ADDRESS t RCH (14) t CAH (11) t CAA (20) t OAC (17) OE V IH V IL t HZ (22) t RAC (19) t CAC (18) t LZ (21) t CAC (18) t HZ (22) t LZ (21) I/O V OH V OL VALID DATA OUT VALID DATA OUT t LZ (21) t HZ (22) t HZ (22) t CAC (18) t RCS (7) COLUMN ADDRESS t RCS (7) t CAR (44) t PC (42) t CP (43) t RSH (R)(12) t CAS (5) t AR (23) t RAS (1) V53C8126H t RP (3) t CAS (5) t CRP (13) t CAS (5) t ASR (8) ADDRESS V IH V IL t ASC (10) ROW ADDRESS t RCS (7) t CAH (11) t RCH (14) WE V IH V IL t CAP (45) t OAC (17) t CAA (20) t OAC (17) t RRH (15) t HZ (22) t HZ (22) VALID DATA OUT 676 05 Waveforms of Fast Page Mode Write Cycle t AR (23) RAS V IH V IL t CRP (13) t RCD (6) CAS V IH V IL t CSH (4) t RAH (9) t ASR (8) ADDRESS V IH V IL t RAD (24) t WCS (27) t WP (29) WE V IH V IL VIH V IL t DS (32) I/O V IH V IL VALID DATA IN ROW ADD COLUMN ADDRESS t RP (3) t RAS (1) t PC (42) t CP (43) t CAS (5) t RSH (W)(25) t CRP (13) t CAS (5) t CAS (5) t CAR (44) t ASC (10) t CAH (11) COLUMN ADDRESS t ASC (10) t CAH (11) COLUMN ADDRESS t CAH (11) t CWL (26) t WCS (27) t WCH (28) t CWL (26) t WCS (27) t WCH (28) t WP (29) t CWL (26) t RWL (31) t WCH (28) t WP (29) OE t DS (32) t DH (33) OPEN VALID DATA IN t DS (32) t DH (33) VALID DATA IN t DH (33) OPEN 676 06 V53C8126H Rev. 1.1 July 1997 11 MOSEL VITELIC Waveforms of Fast Page Mode Read-Write Cycle RAS VIH V IL V53C8126H t RAS (1) t CSH (4) t RCD (6) t PCM (50) t CP (43) V CAS V IH IL t RP (3) t RSH (W)(25) t CRP (13) t CAS (5) t CAS (5) t RAD (24) t RAH (9) t ASC (10) t ASR (8) t ASC (10) t CAH (11) COLUMN ADDRESS COLUMN ADDRESS t CAS (5) t CAR (44) t ASC (10) t CAH (11) COLUMN ADDRESS t CAH (11) V ADDRESS V IH IL ROW ADD t RWD (39) t RCS (7) t CWD (38) V WE V IH IL t CWD (38) t CWL (26) t CWL (26) t CWD (38) t RWL (31) t CWL (26) t AWD (41) t CAA (20) t OAC (17) V OE V IH IL t AWD (41) t WP (29) t OAC (17) t AWD (41) t WP (29) t OAC (17) t WP (29) t CAP (45) t OED (35) t CAC (18) t RAC (19) t CAA (20) t OED (35) t CAC (18) t HZ (22) t CAP (45) t CAA (20) t OED (35) t CAC (18) t HZ (22) t DH (33) t DS (32) OUT IN 676 07 t HZ (22) t DH (33) t DH (33) t DS (32) OUT IN t DS (32) I/O V I/OH V I/OL t LZ (21) OUT IN t LZ (21) t LZ (21) Waveforms of RAS-Only Refresh Cycle t RC (2) V IH V IL t CRP (13) CAS V IH V IL t ASR (8) ADDRESS V IH V IL NOTE: ROW ADDR 1579 08 t RAS (1) t RP (3) RAS t RAH (9) WE, OE = Don’t care V53C8126H Rev. 1.1 July 1997 12 MOSEL VITELIC Waveforms of CAS-before-RAS Refresh Counter Test Cycle t RAS (1) RAS V IH V IL t CSR (47) CAS V IH V IL V IH V IL READ CYCLE V IH V IL t ROH (16) t OAC (17) OE V IH V IL t LZ (21) I/O V IH V IL WRITE CYCLE V IH V IL V IH V IL t I/O V IH V IL DS (32) V53C8126H t RP (3) t CHR (49) t CP (43) t RSH (W)(25) t CAS (5) ADDRESS t RCS (7) t RRH (15) t RCH (14) WE t HZ (22) t HZ (22) DOUT t RWL (31) t CWL (26) t WCS (27) t WCH (28) WE OE t DH (33) D IN 676 12 Waveforms of CAS-before-RAS Refresh Cycle t RC (2) t RP (3) RAS V IH V IL t CP (43) t CSR (47) CAS V IH V IL t HZ (22) I/O V OH V OL NOTE: WE, OE, A 0 –A 7 = Don’t care 675 07 t RAS (1) t RP (3) t RPC (48) t CHR (49) V53C8126H Rev. 1.1 July 1997 13 MOSEL VITELIC Waveforms of Hidden Refresh Cycle (Read) t RC (2) V IH V IL t RCD (6) t CRP (13) CAS V IH V IL t ASR (8) t RAH (9) ADDRESS V IH V IL V IH V IL t CAA (20) t OAC (17) OE V IH V IL t CAC (18) t LZ (21) t RAC (19) I/O V OH V OL VALID DATA ROW ADD V53C8126H t RC (2) tRP (3) t RAS (1) t RP (3) t RAS (1) t AR (23) RAS t RSH (R)(12) t CHR (49) t CRP (13) t RAD (24) t ASC (10) t CAH (11) COLUMN ADDRESS t RCS (7) WE t RRH (15) t HZ (22) t HZ (22) 676 10 Waveforms of Hidden Refresh Cycle (Write) t RC (2) V IH RAS V IL t RCD (6) t CRP (13) CAS V IH V IL t ASR (8) t RAH (9) ADDRESS V IH V IL V IH V IL V IH V IL t DS (32) I/O V IH V IL t DH (33) VALID DATA-IN ROW ADD t RC (2) t RP (3) t RAS (1) t RP (3) t RAS (1) t AR (23) t RSH (12) t CHR (49) t CRP (13) t RAD (24) t ASC (10) t CAH (11) COLUMN ADDRESS t WCS (27) WE t WCH (28) OE t DHR (46) 676 11 V53C8126H Rev. 1.1 July 1997 14 MOSEL VITELIC Functional Description The V53C8126H is a CMOS dynamic RAM optimized for high data bandwidth, low power applications. It is functionally similar to a traditional dynamic RAM. The V53C8126H reads and writes data by multiplexing an 17-bit address into a 9-bit row and an 8-bit column address. The row address is latched by the Row Address Strobe (RAS). The column address “flows through” an internal address buffer and is latched by the Column Address Strobe (CAS). Because access time is primarily dependent on a valid column address rather than the precise time that the CAS edge occurs, the delay time from RAS to CAS has little effect on the access time. V53C8126H Write Cycle A Write Cycle is performed by taking WE and CAS low during a RAS operation. The column address is latched by CAS. The Write Cycle can be WE controlled or CAS controlled depending on whether WE or CAS falls later. Consequently, the input data must be valid at or before the falling edge of WE or CAS, whichever occurs last. In the CAScontrolled Write Cycle, when the leading edge of WE occurs prior to the CAS low transition, the I/O data pins will be in the High-Z state at the beginning of the Write function. Ending the Write with RAS or CAS will maintain the output in the High-Z state. In the WE controlled Write Cycle, OE must be in the high state and tOED must be satisfied. Memory Cycle A memory cycle is initiated by bringing RAS low. Any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. This ensures proper device operation and data integrity. A new cycle must not be initiated until the minimum precharge time tRP/tCP has elapsed. Refresh Cycle To retain data, 512 Refresh Cycles are required in each 8 ms period. There are two ways to refresh the memory: 1. By clocking each of the 512 row addresses (A0 through A8) with RAS at least once every 8 ms. Any Read, Write, Read-Modify-Write or RASonly cycle refreshes the addressed row. 2. Using a CAS-before-RAS Refresh Cycle. If CAS makes a transition from low to high to low after the previous cycle and before RAS falls, CASbefore- RAS r efresh is activated. The V53C8126H uses the output of an internal 9-bit counter as the source of row addresses and ignore external address inputs. CAS-before-RAS is a “refresh-only” mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. A CAS-before-RAS counter test mode is provided to ensure reliable operation of the internal refresh counter. Read Cycle A Read cycle is performed by holding the Write Enable ( WE ) signal High during a R AS / CAS operation. The column address must be held for a minimum specified by tAR. Data Out becomes valid only when tOAC, tRAC, tCAA and tCAC are all satisifed. As a result, the access time is dependent on the timing relationships between these parameters. For example, the access time is limited by tCAA when tRAC, tCAC and tOAC are all satisfied. V53C8126H Rev. 1.1 July 1997 15 MOSEL VITELIC Fast Page Mode Operation Fast Page Mode operation permits all 256 columns within a selected row of the device to be randomly accessed at a high data rate. Maintaining RAS low while performing successive CAS cycles retains the row address internally and eliminates the need to reapply it for each cycle. The column address buffer acts as a transparent or flow-through latch while CAS is high. Thus, access begins from the occurrence of a valid column address rather than from the falling edge of CAS, eliminating tASC and tT from the critical timing path. CAS latches the address into the column address buffer and acts as an output enable. During Fast Page Mode operation, Read, Write, Read-Modify-Write or Read-Write-Read cycles are possible at random addresses within a row. Following the initial entry cycle into Fast Page Mode, access is tCAA or tCAP controlled. If the column address is valid prior to the rising edge of CAS, the access time is referenced to the CAS rising edge and is specified by tCAP. If the column address is valid after the rising CAS edge, access is timed from the occurrence of a valid address and is specified by tCAA. In both cases, the falling edge of CAS latches the address and enables the output. Fast Page Mode provides sustained data rates up to 40 MHz for applications that require high data rates such as bit-mapped graphics or high-speed signal processing. The following equation can be used to calculate the maximum data rate: 256 Data Rate = tRC + 255 x tPC V53C8126H OE signal has no effect on any data stored in the output latches. A WE low level can also disable the output drivers when CAS is low. During a Write cycle, if WE goes low at a time in relationship to CAS that would normally cause the outputs to be active, it is necessary to use OE to disable the output drivers prior to the WE low transition to allow Data In Setup Time (tDS) to be satisfied. Power-On After application of the VCC supply, an initial pause of 200 µs is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a RAS clock). Eight initialization cycles are required after extended periods of bias without clocks (greater than the Refresh Interval). During Power-On, the VCC current requirement of the V53C8126H is dependent on the input levels of RAS and CAS. If RAS is low during Power-On, the device will go into an active cycle and IDD will exhibit current transients. It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges. Table 1. V53C8126H Data Output Operation for Various Cycle Types Cycle Type Read Cycles CAS-Controlled Write Cycle (Early Write) WE-Controlled Write Cycle (Late Write) Read-Modify-Write Cycles Fast Page Mode Read Fast Page Mode Write Cycle (Early Write) Fast Page Mode ReadModify-Write Cycle RAS-only Refresh CAS-before-RAS Refresh Cycle CAS-only Cycles I/O State Data from Addressed Memory Cell High-Z OE Controlled. High OE = High-Z I/Os Data from Addressed Memory Cell Data from Addressed Memory Cell High-Z Data from Addressed Memory Cell High-Z Data remains as in previous cycle High-Z Data Output Operation The V53C8126H Input/Output is controlled by OE, CAS, WE and RAS. A RAS low transition enables the transfer of data to and from the selected row address in the Memory Array. A RAS high transition disables data transfer and latches the output data if the output is enabled. After a memory cycle is initiated with a RAS low transition, a CAS low transition or CAS low level enables the internal I/O path. A CAS high transition or a CAS high level disables the I/O path and the output driver if it is enabled. A CAS low transition while RAS is high has no effect on the I/O data path or on the output drivers. The output drivers, when otherwise enabled, can be disabled by holding OE high. The V53C8126H Rev. 1.1 July 1997 16 MOSEL VITELIC Package Diagrams 26/24-pin 300 mil SOJ 0.332/0.342 0.296/0.304 0.665/0.698 0.125/0.135 V53C8126H 0.082/0.093 0.018 Typ. 0.025 Min. 0.255/0.275 0.028 Typ. 0.05 Typ. 28-pin TSOP-I .035 .043 .039 DIA. .520 .535 .461 .469 0.10 .311 .319 .047 Detail “A” 0.10 (.004) .002 .006 .079 DIA. x .000 Deep .0004 Fixed Pin (1 Plcs.) .035 .043 .55 .055 .063 0.25 Top View 0.10 D See Detail “B” .055 .063 Bottom View .055 .063 .008 .20 Gage Plane 0.25 BSC .020 .028 Detail “B” .012 MAX .037 .041 See Detail “A” D .007 .011 0° 6° With Plating .007 .009 .004 .008 Base Metal .004 .006 Section “D-D” Detail “A” V53C8126H Rev. 1.1 July 1997 17 MOSEL VITELIC U.S.A. 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 WORLDWIDE OFFICES TAIWAN 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 011-886-2-545-1213 FAX: 011-886-2-545-1209 V53C8126H JAPAN RM.302 ANNEX-G HIGASHI-NAKANO NAKANO-KU, TOKYO 164 PHONE: 011-81-03-3365-2851 FAX: 011-81-03-3365-2836 HONG KONG 19 DAI FU STREET TAIPO INDUSTRIAL ESTATE TAIPO, NT, HONG KONG PHONE: 011-852-665-4883 FAX: 011-852-664-7535 1 CREATION ROAD I SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 011-886-35-783344 FAX: 011-886-35-792838 U.S. SALES OFFICES NORTHWESTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 SOUTHWESTERN SUITE 200 5150 E. PACIFIC COAST HWY. LONG BEACH, CA 90804 PHONE: 310-498-3314 FAX: 310-597-2174 CENTRAL & SOUTHEASTERN 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 214-690-1402 FAX: 214-690-0341 NORTHEASTERN SUITE 436 20 TRAFALGAR SQUARE NASHUA, NH 03063 PHONE: 603-889-4393 FAX: 603-889-9347 9/96 © Copyright 1996, MOSEL VITELIC Inc. Printed in U.S.A. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. MOSEL VITELIC V53C8126H Rev. 1.1 July 1997 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461 18