V61C51161024

MOSEL VITELIC V61C51161024 64K x 16 HIGH SPEED STATIC RAM PRELIMINARY Features s s s s s s High-speed: 10, 12, 15 ns All inputs and outputs directly TTL compatible Three state outputs Byte Control Pins Single 5V ± 10% Power Supply Packages – 44-pin TSOP (Standard) – 44-pin 400 mil SOJ Description T he V61C51161024 is a 1,048,576-bit static random-access memory organized as 65,536 words by 16 bits. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Functional Block Diagram A1 Row Decoder Memory Array VCC GND A7 A8 A9 I/O0 Input Data Circuit I/O15 A0 UBE LBE OE WE CE Column I/O Column Decoder A10 A15 Control Circuit 6151161024-01 Device Usage Chart Operating Temperature Range 0°C to 70 °C Package Outline T • K • 10 • Access Time (ns) 12 • 15 • Temperature Mark Blank V61C51161024 Rev. 1.0 July 1998 1 MOSEL VITELIC Pin Descriptions A0–A15 Address Inputs These 16 address inputs select one of the 64K x 16 bit segments in the RAM. CE Chip Enable Input CE is active LOW. It must be active to read from or write to the device. If chip enable is not active, the device is deselected and is in a standby power mode. The I/O pins will be in the high-impedance state when deselected. OE Output Enable Input The output enable input is active LOW. When OE is Low with CE Low and WE High, data will be presented on the I/O pins. The I/O pins will be in the high impedance state when OE is High. V61C51161024 UBE, LEB Byte Enable Active low inputs. These inputs are used to enable the upper or lower data byte. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip enabled, when WE is HIGH and OE is LOW, output data will be present at the I/O pins; when WE is LOW and OE is HIGH, the data present on the I/O pins will be written into the selected memory locations. I/O0–I/O15 Data Input and Data Output Ports These 16 bidirectional ports are used to read data from and write data into the RAM. VCC GND Power Supply Ground Pin Configurations (Top View) 44-Pin SOJ A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 6151161024-02 44-Pin TSOP-II (Standard) A5 A6 A7 OE UBE LBE I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 6151161024-03 A5 A6 A7 OE UBE LBE I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC V61C51161024 Rev. 1.0 July 1998 2 MOSEL VITELIC Part Number Information V MOSEL-VITELIC SRAM FAMILY 61 = HIGH SPEED C = CMOS PROCESS 51 = 5V ORGANIZATION BLANK = STANDARD POWER 16 = 16-bit OPERATING VOLTAGE DENSITY 1024K PWR. 10 ns 12 ns 15 ns SPEED PKG V61C51161024 61 C 51 16 1024 – TEMP. BLANK = 0¡C to 70¡C T = TSOP STANDARD K = 400 mil SOJ 6151161024-04 Absolute Maximum Ratings (1) Symbol VCC VIN VDQ TBIAS TSTG Parameter Supply Voltage Input Voltage Input/Output Voltage Applied Temperature Under Bias Storage Temperature Commercial -0.5 to +7 -0.5 to +7 VCC + 0.5 -10 to +85 -65 to +150 Units V V V °C °C NOTE: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Capacitance* TA = 25°C, f = 1.0MHz Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VI/O = 0V Max. 6 8 Unit pF pF NOTE: 1. This parameter is guaranteed by design and not tested. Truth Table Mode Standby Output Disable Output Disable Read Read Read Write Write Write CE H L L L L L L L L OE X X H L L L X X X WE X X H H H H L L L UBE X H X L L H L L H LBE X H X L H L L H L I/O8-15 Operation High Z High Z High Z DOUT DOUT High Z DIN DIN High Z I/O0-7 Operation High Z High Z High Z DOUT High Z DOUT DIN High Z DIN NOTE: X = Don’t Care, L = LOW, H = HIGH V61C51161024 Rev. 1.0 July 1998 3 MOSEL VITELIC DC Electrical Characteristics (over all temperature ranges, VCC = 5V ± 10%) -10 Symbol IIL IOL ICC ISB Parameter Input Leakage Current Output Leakage Current Test Conditions VCC = MAX, VIN = GND to VCC CE = VIH, VCC = Max, VOUT = GND to VCC CE = VIL, IOUT = 0, f = fmax CE = VIH, f = fmax CE ³ VCC – 0.2V, f = 0, VIN £ 0.2V or VIN > VCC – 0.2V IOL = 8mA IOH = -4mA Min. — — Max. 5 5 Min. — — -12 Max. 5 5 V61C51161024 -15 Min. — — Max. 5 5 Units mA mA mA Operating Power Supply Current Standby Power Supply Current (TTL Level) Standby Power Supply Current (CMOS Level) Output Low Voltage Output High Voltage — 220 — 210 — 200 — 60 — 50 — 40 mA ISB1 VOL VOH — 5.0 — 5.0 — 5.0 mA — 2.4 0.4 — — 2.4 0.4 — — 2.4 0.4 — V V NOTES: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. VIL (Min.) = -3.0V for pulse width < 20ns. 3. fMAX = 1/tRC. 4. Maximum values. AC Test Conditions Input Pulse Levels Input Rise and Fall Times Timing Reference Levels Output Load 0 to 3V 3 ns 1.5V AC Test Loads and Waveforms +5V 480 ½ I/O Pins see below 255 ½ CL = 30 pF* Key to Switching Waveforms WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM H TO L OUTPUTS WILL BE STEADY WILL BE CHANGING FROM H TO L WILL BE CHANGING FROM L TO H CHANGING: STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE “OFF” STATE +5V 480 ½ I/O Pins 255 ½ CL = 5pF* MAY CHANGE FROM L TO H for tCLZ, tCHZ, tOLZ, tWHZ, tOW, and tOHZ * Includes scope and jig capacitance 6151161024-05 DON'T CARE: ANY CHANGE PERMITTED DOES NOT APPLY V61C51161024 Rev. 1.0 July 1998 4 MOSEL VITELIC AC Electrical Characteristics (over all temperature ranges) Read Cycle -10 Parameter Name tRC tAA tACS tBA tOE tCLZ tBLZ tOLZ tCHZ tOHZ tBHZ tOH Parameter Read Cycle Time Address Access Time Chip Enable Access Time UBE, LBE Access Time Output Enable to Output Valid Chip Enable to Output in Low Z UBE, LBE to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z UBE, LBE to Output in High Z Output Hold from Address Change Min. 10 — — — — 0 0 0 0 0 0 2 Max. — 10 10 5 5 — — — 5 5 5 — Min. 12 — — — — 0 0 0 0 0 0 3 -12 Max. — 12 12 6 6 — — — 6 6 6 — V61C51161024 -15 Min. 15 — — — — 0 0 0 0 0 0 3 Max. — 15 15 7 7 — — — 7 7 7 — Unit ns ns ns ns ns ns ns ns ns ns ns ns Write Cycle -10 Parameter Name tWC tCW tAS tAW tWP tWR tWHZ tWLZ tDW tDH tBW Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output High-Z Write to Output Low Z Data Setup to End of Write Data Hold from End of Write UBE, LBE to End of Write Min. 10 7 0 7 7 0 0 3 5 0 7 Max. — — — — — — 5 — — — — Min. 12 8 0 8 8 0 0 3 6 0 8 -12 Max. — — — — — — 6 — — — — Min. 15 10 0 10 10 0 0 5 7 0 10 -15 Max. — — — — — — 7 — — — — Unit ns ns ns ns ns ns ns ns ns ns ns V61C51161024 Rev. 1.0 July 1998 5 MOSEL VITELIC Switching Waveforms (Read Cycle) Read Cycle 1(1, 2) tRC ADDRESS tAA OE tOE tOLZ tBLZ UBE, LBE tBA I/O V61C51161024 tOHZ(5) tBHZ 51161024-07 Read Cycle 2(1, 2, 4) tRC ADDRESS tOH I/O 51161024-08 tAA tOH Read Cycle 3(1, 3, 4) ADDRESS tACS CE tCLZ(5) I/O 51161024-09 tCHZ(5) NOTES: 1. WE = VIH. 2. CE1 = VIL. 3. Address valid prior to or coincident with CE transition LOW. 4. OE = VIL. 5. Transition is measured ±500mV from steady state with CL = 5pF. This parameter is guaranteed and not 100% tested. 6. UBE = VIL, LBE = VIL. V61C51161024 Rev. 1.0 July 1998 6 MOSEL VITELIC Switching Waveforms (Write Cycle) Write Cycle 1 (WE Controlled)(4) tWC ADDRESS tCW(6) CE tAS WE tAW tWR(2) V61C51161024 tBW UBE, LBE tWP(1) OUTPUT tWHZ(3) INPUT 51161024-10 tDW tDH Write Cycle 2 (CE Controlled)(4) tWC ADDRESS tAS CE tAW WE tBW UBE, LBE Hi-Z tDW INPUT 51161024-11 tCW(6) tWR(2) OUTPUT tDH (5) NOTES: 1. The internal write time of the memory is defined by the overlap of CE active and WE low. All signals must be active to initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 2. tWR is measured from the earlier of CE or WE going high. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 4. OE = VIL or VIH. However it is recommended to keep OE at VIH during write cycle to avoid bus contention. 5. If CE is LOW during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 6. tCW is measured from CE going low to the end of write. V61C51161024 Rev. 1.0 July 1998 7 MOSEL VITELIC Package Diagrams 44-pin 400 mil TSOP-II +0.004 0.006 -0.002 +0.01 0.15 -0.05 44 23 V61C51161024 0.020 ± 0.006 [0.50 ± .019] 0.463 ± 0.008 [11.76 ± 0.20] 1 22 0¡–5¡ 0.741[18.81] MAX 0.725 ± 0.004 [18.41 ± 0.10] 0.047 [1.20] MAX 0.004 MAX Unit in inches [mm] 0.032 [0.80] 0.031 [0.80] 0.014 ± 0.004 [0.35 ± 0.10] 0.000 [0.0] MIN V61C51161024 Rev. 1.0 July 1998 8 0.400 [10.16] MOSEL VITELIC Package Diagrams 44-pin 400 mil SOJ (450 mil pin-to-pin) 1.131+0.008 28.73 +0.2 -0.014 -0.36 44 23 V61C51161024 Unit in inches [mm] 1 22 0.31 [0.8] MIN 0.400 [10.16] 0.102 [2.6] 0.091 0.029 [0.74] 0.041 +.006 –.007 [1.03 ± 0.15] 0.138 ± 0.008 [3.5 ± 0.2] +.008 –.007 [2.3±0.2] 0.440 ± 0.008 [11.18 ± 0.20] 0.008 +0.004 -0.002 0.20 +0.10 -0.05 0.050 [1.27] 0.004 [0.10] 0.005 [0.12] M 0.016+0.004 –0.005 [0.40 ± 0.10] 0.370 ± 0.008 [9.4 ± 0.20] 0.033 [0.85] V61C51161024 Rev. 1.0 July 1998 9 MOSEL VITELIC U.S.A. 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 WORLDWIDE OFFICES TAIWAN 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 1 CREATION ROAD I SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-578-3344 FAX: 886-3-579-2838 V61C51161024 GERMANY (CONTINENTAL EUROPE & ISRAEL ) 71083 HERRENBERG BENZSTR. 32 GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22 JAPAN WBG MARINE WEST 25F 6, NAKASE 2-CHOME MIHAMA-KU, CHIBA-SHI CHIBA 261-71 PHONE: 81-43-299-6000 FAX: 81-43-299-6555 HONG KONG 19 DAI FU STREET TAIPO INDUSTRIAL ESTATE TAIPO, NT, HONG KONG PHONE: 852-2665-4883 FAX: 852-2664-7535 IRELAND & UK BLOCK A UNIT 2 BROOMFIELD BUSINESS PARK MALAHIDE CO. DUBLIN, IRELAND PHONE: +353 1 8038020 FAX: +353 1 8038049 U.S. SALES OFFICES NORTHWESTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 SOUTHWESTERN SUITE 200 5150 E. PACIFIC COAST HWY. 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MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461