V61C518256-15T

MOSEL VITELIC V61C518256 32K X 8 HIGH SPEED STATIC RAM Description PRELIMINARY Features s High-speed: 10, 12, 15 ns s Low Power Dissipation: – CMOS Standby: 0.5 mA (Max.) s Fully static operation s All inputs and outputs directly compatible s Three state outputs s Ultra low data retention current (VCC = 2V) s Single 5V ± 10% Power Supply s Packages – 28-pin TSOP (Standard) – 28-pin 300 mil SOJ The V61C518256 is a 262,144-bit static random access memory organized as 32,768 words by 8 bits. It is built with MOSEL VITELIC’s high performance CMOS process. Inputs and threestate outputs are TTL compatible and allow for direct interfacing with common system bus structures. Functional Block Diagram A0 A1 A6 A10 A13 A14 I/O0 Input Data Circuit I/O7 A2 CE OE WE A5 A11 A12 Row Decoder 512 x 512 Memory Array VCC GND Column I/O Column Decoder Control Circuit 518256-01 Device Usage Chart Operating Temperature Range 0°C to 70 °C Package Outline T • N • R • 10 • Access Time (ns) 12 • 15 • Temperature Mark Blank V61C518256 Rev. 0.3 July 1998 1 MOSEL VITELIC Pin Descriptions A0–A14 Address Inputs These 15 address inputs select one of the 32,768 x 8 bit segments in the RAM. CE Chip Enable Inputs CE is an active LOW input. Chip Enable must be LOW when reading from or writing to the device. When HIGH, the device is in standby mode with I/O pins in the high impedance state. OE Output Enable Input The Output Enable input is active LOW. When OE is LOW with CE LOW and WE HIGH, data of the selected memory location will be available on the I/O pins. When OE is HIGH, the I/O pins will be in the high impedance state. V61C518256 WE Write Enable Input An active LOW input, WE input controls read and write operations. When CE and WE inputs are both LOW, the data present on the I/O pins will be written into the selected memory location. I/O0–I/O7 Data Input and Data Output Ports These 8 bidirectional ports are used to read data from and write data into the RAM. VCC GND Power Supply Ground Pin Configurations (Top View) 28-Pin SOJ A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 518256-01 28-Pin TSOP (Standard) VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 518256-03 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 V61C518256 Rev. 0.3 July 1998 2 MOSEL VITELIC Part Number Information V MOSEL-VITELIC MANUFACTURED V61C518256 61 C 51 8 256 – TEMP. SRAM FAMILY OPERATING VOLTAGE DENSITY 256K SPEED PKG BLANK = 0¡C to 70¡C 61 = STANDARD C = CMOS PROCESS 51 = 5V T = TSOP STANDARD R = 300-mil SOJ ORGANIZATION 8 = 8-bit PWR. 10 ns 12 ns 15 ns BLANK = STANDARD 518256-05 Absolute Maximum Ratings (1) Symbol VCC VN VDQ TBIAS TSTG Parameter Supply Voltage Input Voltage Input/Output Voltage Applied Temperature Under Bias Storage Temperature Commercial -0.5 to +7 -0.5 to +7 VCC + 0.5 -55 to +85 -55 to +125 Units V V V °C °C NOTE: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Capacitance* TA = 25°C, f = 1.0MHz Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VI/O = 0V Max. 6 8 Unit pF pF Truth Table Mode Standby Read Read Write CE H L L L OE X L H X WE X H H L I/O Operation High Z DOUT High Z DIN NOTE: * This parameter is guaranteed by design and not tested. NOTE: X = Don’t Care, L = LOW, H = HIGH V61C518256 Rev. 0.3 July 1998 3 MOSEL VITELIC DC Electrical Characteristics (over all temperature ranges, VCC = 5V ± 10%) Symbol VIL VIH IIL IOL VOL VOH V61C518256 Parameter Input LOW Voltage(1,2) Input HIGH Voltage(1) Input Leakage Current Output Leakage Current Output LOW Voltage Output HIGH Voltage Test Conditions Min. -0.5 2.2 Typ. — — — — — — Max. 0.8 6 5 5 0.4 — Units V V mA mA V V VCC = Max, VIN = 0V to VCC VCC = Max, CE = VIH, VOUT = 0V to VCC VCC = Min, IOL = 8mA VCC = Min, IOH = -4mA -5 -5 — 2.4 Symbol ICC1 ISB ISB1 Parameter Average Operating Current, CE £ VIL Output Open, VCC = Max., f = fMAX(3) TTL Standby Current CE ³ VIH, VCC = Max. CMOS Standby Current, CE ³ VCC – 0.2V, VIN ³ VCC – 0.2V or VIN £ 0.2V, VCC = Max. Com.(4) 110 Ind. 130 Units mA 25 40 mA 1 2 mA NOTES: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. VIL (Min.) = -3.0V for pulse width < 20ns. 3. fMAX = 1/tRC. 4. Maximum values. V61C518256 Rev. 0.3 July 1998 4 MOSEL VITELIC Data Retention Characteristics Symbol VDR ICCDR V61C518256 Parameter VCC for Data Retention Data Retention Current VDR = 3.0V, CE ³ VDR – 0.2V Chip Deselect to Data Retention Time Operation Recovery Time (see Retention Waveform) CE ³ VCC – 0.2V Com’l Ind. Min. 2.0 — — 0 tRC (1) Typ.(2) — — — — — Max. 5.5 150 200 — — Units V mA tCDR tR ns ns NOTES: 1. tRC = Read Cycle Time 2. TA = +25°C. Low VCC Data Retention Waveform Data Retention Mode VCC 4.5V tCDR CE 2.2V VDR VDR ³ 2V tR 2.2V 518256-07 4.5V AC Test Conditions Input Pulse Levels Input Rise and Fall Times Timing Reference Levels Output Load 0 to 3V 3 ns 1.5V see below Key to Switching Waveforms WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM H TO L OUTPUTS WILL BE STEADY WILL BE CHANGING FROM H TO L WILL BE CHANGING FROM L TO H CHANGING: STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE “OFF” STATE AC Test Loads and Waveforms MAY CHANGE FROM L TO H +5V 480 ½ I/O Pin 255 ½ CL = 30 pF* DOES NOT APPLY DON'T CARE: ANY CHANGE PERMITTED * Includes scope and jig capacitance +5V 480 ½ I/O Pin 255 ½ 5 pF* Output load for tCLZ, tCHZ, tOHZ, tOLZ, tWZ, tOW 518256-06 V61C518256 Rev. 0.3 July 1998 5 MOSEL VITELIC AC Electrical Characteristics (over all temperature ranges) Read Cycle Parameter Name tRC tAA tACS tOE tCLZ tOLZ tCHZ tOHZ tOH V61C518256 -10 Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Enable to Output Valid Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change -12 Min. 12 — — — 3 0 0 0 3 -15 Min. 15 — — — 3 0 0 0 3 Min. 10 — — — 2 0 0 0 2 Max. — 10 10 5 — — 2 2 — Max. — 12 12 6 — — 3 3 — Max. — 15 15 7 — — 4 4 — Unit ns ns ns ns ns ns ns ns ns Write Cycle Parameter Name tWC tCW tAS tAW tWP tAH tWHZ tDW tDH tOW -10 Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Address Hold from End of Write Write to Output High-Z Data Setup to End of Write Data Hold from End of Write Output Active from End of Write -12 Min. 12 10 0 10 9 — 0 7 0 3 -15 Min. 15 12 0 12 11 — 0 8 0 3 Min. 10 9 0 9 8 — 0 6 0 3 Max. — — — — — 0.5 5 — — — Max. — — — — — 0.5 5 — — — Max. — — — — — 0.5 5 — — — Unit ns ns ns ns ns ns ns ns ns ns V61C518256 Rev. 0.3 July 1998 6 MOSEL VITELIC Switching Waveforms (Read Cycle) Read Cycle 1(1, 2) tRC ADDRESS tAA OE tOE tOLZ I/O tOHZ(5) V61C518256 518256-08 Read Cycle 2(1, 2, 4) tRC ADDRESS tOH I/O 518256-09 tAA tOH Read Cycle 3(1, 3, 4) ADDRESS tACS CE tCLZ(5) I/O 518256-10 tCHZ(5) NOTES: 1. WE = VIH. 2. CE = VIL. 3. Address valid prior to or coincident with CE transition LOW. 4. OE = VIL. 5. Transition is measured ±500mV from steady state with CL = 5pF. This parameter is guaranteed and not 100% tested. V61C518256 Rev. 0.3 July 1998 7 MOSEL VITELIC Switching Waveforms (Write Cycle) Write Cycle 1 (WE Controlled)(4) tWC ADDRESS tCW(6) CE tAS WE tWP(1) OUTPUT tWHZ(3) INPUT tDW tDH tAW tAH(2) V61C518256 518256-11 Write Cycle 2 (CE Controlled)(4) tWC ADDRESS tAS CE tAW WE Hi-Z tDW INPUT 518256-12 tCW(6) tAH(2) OUTPUT tDH (5) NOTES: 1. The internal write time of the memory is defined by the overlap of CE active and WE low. Both signals must be active to initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 2. tAH is measured from the earlier of CE or WE going HIGH. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 4. OE = VIL or VIH. However it is recommended to keep OE at VIH during write cycle to avoid bus contention. 5. If CE is LOW during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 6. tCW is measured from CE going LOW to the end of write. V61C518256 Rev. 0.3 July 1998 8 MOSEL VITELIC Package Diagrams 28-pin 300 mil SOJ 0.715 ± 0.015(1) [18.161 ± 0.381] 28 15 V61C518256 0.334 ±0.013 [8.484 ±0.330] +0.005 0.300(1)–0.008 1 14 0.011 ±0.003 [0.279 ±0.076] 0.100 ±0.005 [2.540 ±0.127] 0.029 ± 0.003 [0.737 ± 0.076] 0.034 ±0.011 [0.836 ±0.279] 0.134 ±0.006 [3.404 ±0.152] Unit in inches [mm] 0.050 TYP [1.270 TYP] 0.019 ±0.003 [0.483 ±0.076] 0.004 [0.102] 0.020 MIN [0.508 MIN] (1) Does not include mold flash protrusion and should be measured from the bottom of the package. 28-Pin TSOP Unit in inches [mm] 0.463 ±0.003 [11.76 ± 0.076] 0.528 ±0.008 [13.41 ± 0.203] 0.315 ±0.004 [8.00 ± 0.102] 0.046 ±0.004 [1.17 ± 0.102] +0.007 0.020 –0.008 +0.178 0.508 –0.305 0.006 ±0.002 [0.152 ± 0.051] 0.022 [0.559] BSC 0.006 ±0.004 [0.152 ± 0.102] V61C518256 Rev. 0.3 July 1998 9 0.265 ±0.020 [6.731 ±0.508] +0.127 7.620 –0.203 MOSEL VITELIC Notes V61C518256 V61C518256 Rev. 0.3 July 1998 10 MOSEL VITELIC Notes V61C518256 V61C518256 Rev. 0.3 July 1998 11 MOSEL VITELIC U.S.A. 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 WORLDWIDE OFFICES TAIWAN 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 011-886-2-545-1213 FAX: 011-886-2-545-1209 1 CREATION ROAD I SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 011-886-35-783344 FAX: 011-886-35-792838 V61C518256 JAPAN WBG MARINE WEST 25F 6, NAKASE 2-CHOME MIHAMA-KU, CHIBA-SHI CHIBA 261-71 PHONE: 011-81-43-299-6000 FAX: 011-81-43-299-6555 HONG KONG 19 DAI FU STREET TAIPO INDUSTRIAL ESTATE TAIPO, NT, HONG KONG PHONE: 011-852-665-4883 FAX: 011-852-664-7535 U.S. SALES OFFICES NORTHWESTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 SOUTHWESTERN SUITE 200 5150 E. PACIFIC COAST HWY. LONG BEACH, CA 90804 PHONE: 562-498-3314 FAX: 562-597-2174 CENTRAL & SOUTHEASTERN 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 972-690-1402 FAX: 972-690-0341 NORTHEASTERN SUITE 436 20 TRAFALGAR SQUARE NASHUA, NH 03063 PHONE: 603-889-4393 FAX: 603-889-9347 © Copyright 1997, MOSEL VITELIC Inc. 7/98 Printed in U.S.A. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461