V62C2162048L-85B

V62C2162048L(L) Ultra Low Power 128K x 16 CMOS SRAM Features • Low-power consumption - Active: 65mA ICC at 35ns - Stand-by: 10 µA (CMOS input/output) 2 µA (CMOS input/output, L version) • 35/45/55/70/85/100 ns access time • Equal access and cycle time • Single +2.2V to 2.7V Power Supply • Tri-state output • Automatic power-down when deselected • Multiple center power and ground pins for improved noise immunity • Individual byte controls for both Read and Write cycles • Available in 44 pin TSOP II / 48-fpBGA Functional Description The V62C2162048L is a Low Power CMOS Static RAM organized as 131,072 words by 16 bits. Easy memory expansion is provided by an active LOW (CE ) and (OE) pin. This device has an automatic power-down mode feature when deselected. Separate Byte Enable controls (BLE and BHE) allow individual bytes to be accessed. BLE controls the lower bits I/O1 - I/O8. BHE controls the upper bits I/O9 - I/O16. Writing to these devices is performed by taking Chip Enable (CE) with Write Enable (WE) and Byte Enable (BLE/BHE) LOW. Reading from the device is performed by taking Chip Enable (CE) with Output Enable (OE) and Byte Enable (BLE/BHE) LOW while Write Enable (WE) is held HIGH. Logic Block Diagram Pre-Charge Circuit A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 Data Cont Data Cont Vcc Vss TSOPII / 48-fpBGA Memory Array 1024 X 2048 I/O1 - I/O8 I/O9 - I/O16 I/O Circuit Column Select A10 A11 A12 A13 A14 A15 A16 WE OE BHE BLE CE A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC Row Select 1 REV. 1.3 OCT 2001 V62C2162048L(L) V62C2162048L(L) MOSEL VITELIC V62C2162048L(L)B 1 2 3 4 5 6 1 2 3 4 5 6 A B BLE OE A0 A1 A2 NC I/O9 BHE A3 A4 CE I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D E VSS I/O12 NC A7 I/O4 VCC VCC I/O13 NC A16 I/O5 VSS F G H I/O15 I/O14 A14 A15 I/O6 I/O7 I/O16 NC NC A8 A12 A9 A13 A10 WE A11 I/O8 NC Note: NC means no Ball. Top View Top View 48 Ball - 9x12 fpBGA (Ultra Low Power) C A1 PACKAGE OUTLINE DWG. SYMBOL A UNIT:MM 1.05+0.15 0.25+0.05 0.35+.05 0.30(TYP) 12.00+0.10 5.25 9.00+0.10 3.75 0.75TYP 0.10 A aaa SIDE VIEW A1 b c D D1 D D1 E 6 e E1 e 5 aaa E1 4 3 2 1 A B C D E F G H BOTTOM VIEW b SOLDER BALL 2 REV. 1.3 OCT 2001 V62C2162048L(L) E V62C2162048L(L) Absolute Maximum Ratings * Parameter Voltage on Any Pin Relative to Gnd Power Dissipation Storage Temperature (Plastic) Temperature Under Bias Symbol Vt PT Tstg Tbias Minimum -0.5 − -55 -40 Maximum +4.6 1.0 +150 +85 Unit V W 0 C 0C * Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth Table CE H L L L L L L L L OE X L L L X X X H X WE X H H H L L L H X BLE BHE I/O1-I/O8 I/O9-I/O16 X X High-Z High-Z L H Data Out High-Z H L High-Z Data Out L L Data Out Data Out L L Data In Data In L H Data In High-Z H L High-Z Data In X X High-Z High-Z H H High-Z High-Z Power Standby Active Active Active Active Active Active Active Active Mode Standby Low Byte Read High Byte Read Word Read Word Write Low Byte Write High Byte Write Output Disable Output Disable * Key: X = Don’t Care, L = Low, H = High Recommended Operating Conditions (TA = 00C to +700C / -400C to 850C**) Parameter Supply Voltage Symbol VCC Gnd VIH VIL Min 2.2 0.0 2.2 -0.5* Typ 2.5 0.0 - Max 2.7 0.0 VCC + 0.2 0.8 Unit V V V V Input Voltage * VIL min = -1.0V for pulse width less than tRC/2. ** For Industrial Temperature 3 REV. 1.3 OCT 2001 V62C2162048L(L) V62C2162048L(L) DC Operating Characteristics (Vcc = 2.2 to 2.7V, Gnd = 0V, TA = 00C to +700C / -400C to 850C) Parameter Input Leakage Current Output Leakage Current Operating Power Supply Current Average Operating Current Sym Test Conditions Vcc = Max, Vin = Gnd to Vcc CE = VIH or Vcc= Max, VOUT = Gnd to Vcc CE = VIL , VIN = VIH or VIL , IOUT = 0 IOUT = 0mA, Min Cycle, 100% Duty CE < 0.2V IOUT = 0mA, CE = VIH CE > Vcc - 0.2V VIN < 0.2V or VIN > Vcc- 0.2V IOL = 2 mA IOH = -2 mA -55 1 1 5 50 3 - -70 1 1 5 45 3 - -85 1 1 5 40 3 - -100 1 1 5 40 3 Min Max Min Max Min Max Min Max Unit µA µA mA IILII IILOI ICC ICC1 ICC2 mA mA Cycle Time=1µs, Duty=100% Standby Power Supply Current (TTL Level) Standby Power Supply Current (CMOS Level) Output Low Voltage Output High Voltage ISB ISB1 - 0.5 10 2 0.4 - 2.4 0.5 10 2 0.4 - 2.4 0.5 10 2 0.4 - 2.4 0.5 10 2 0.4 - mA µA µA V V L 2.4 VOL VOH Capacitance (f = 1MHz, TA = 25oC) Parameter* Input Capacitance I/O Capacitance Symbol Cin CI/O Test Condition Vin = 0V Vin = Vout = 0V Max 7 8 Unit pF pF * This parameter is guaranteed by device characterization and is not production tested. AC Test Conditions Input Pulse Level 0.6V to 2.2V Input Rise and Fall Time 5ns Input and Output Timing Reference Level 1.4V Output Load Condition 55ns/70ns/85ns C = 30pf + 1TTL Load L Load for 100ns CL = 100pf + 1TTL Load CL* TTL Figure A. * Including Scope and Jig Capacitance 4 REV. 1.3 OCT 2001 V62C2162048L(L) V62C2162048L(L) DC Operating Characteristics (Vcc = 2.2 to 2.7V, Gnd = 0V, TA = 00C to +700C / -400C to 850C) Parameter Input Leakage Current Output Leakage Current Operating Power Supply Current Average Operating Current Sym Test Conditions -35 -45 Unit Min Max Min Max 1 1 5 65 3 1 1 5 60 3 µA µA mA IILII IILOI ICC ICC1 ICC2 Vcc = Max, Vin = Gnd to Vcc CE = VIH or Vcc= Max, VOUT = Gnd to Vcc CE = VIL , VIN = VIH or VIL , IOUT = 0 IOUT = 0mA, Min Cycle, 100% Duty CE < 0.2V IOUT = 0mA, CE = VIH CE > Vcc - 0.2V VIN < 0.2V or VIN > Vcc- 0.2V IOL = 2 mA IOH = -2 mA mA mA Cycle Time=1µs, Duty=100% Standby Power Supply Current (TTL Level) Standby Power Supply Current (CMOS Level) Output Low Voltage Output High Voltage ISB ISB1 - 0.5 10 2 0.4 - 2.4 0.5 10 2 0.4 - mA µA µA V V L 2.4 VOL VOH 5 REV. 1.33 OCT 2001 V62C2162048L(L) V62C2162048L(L) Read Cycle (9) (Vcc = 2.2 to 2.7V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Chip Enable to Output in Low-Z Chip Disable to Output in High-Z Output Enable to Output in Low-Z Output Disable to Output in High-Z BLE, BHE Enable to Output in Low-Z BLE, BHE Disable to Output in High-Z BLE, BHE Access Time Sym tRC tAA tACE tOE tOH tLZ tHZ tOLZ tOHZ tBLZ tBHZ tBA 55 10 10 5 5 - -55 55 55 35 25 25 25 35 70 10 10 5 5 - -70 70 70 40 30 25 25 40 85 10 10 5 5 - -85 85 85 40 35 30 30 40 -100 100 10 10 5 5 100 100 50 40 35 35 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns Note Min Max Min Max Min Max Min Max 4,5 3,4,5 4,5 3,4,5 Write Cycle (11) (Vcc = 2.2 to2.7V, Gnd = 0V, T A = 00C to +700C / -400C to +850C) Parameter Write Cycle Time Chip Enable to Write End Address Setup to Write End Address Setup Time Write Pulse Width Write Recovery Time Data Valid to Write End Data Hold Time Write Enable to Output in High-Z Output Active from Write End BLE, BHE Setup to Write End Symbol tWC tCW tAW tAS tWP tWR tDW tDH tWHZ tOW tBW 55 50 50 0 45 0 25 0 5 50 -55 25 6 70 60 60 0 50 0 30 0 5 60 -70 30 85 70 70 0 60 0 35 0 5 70 -85 35 100 80 80 0 70 0 40 0 5 80 -100 40 - Unit ns ns ns ns ns ns ns ns ns ns ns Note Min Max Min Max Min Max Min Max REV. 1.3 OCT 2001 V62C2162048L(L) V62C2162048L(L) Read Cycle (9) (Vcc = 2.2 to 2.7V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Chip Enable to Output in Low-Z Chip Disable to Output in High-Z Output Enable to Output in Low-Z Output Disable to Output in High-Z BLE, BHE Enable to Output in Low-Z BLE, BHE Disable to Output in High-Z BLE, BHE Access Time Sym tRC tAA tACE tOE tOH tLZ tHZ tOLZ tOHZ tBLZ tBHZ tBA -35 35 5 5 5 5 35 35 20 15 15 15 20 -45 45 5 5 5 5 45 45 25 20 20 20 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns Note Min Max Min Max 4,5 3,4,5 4,5 3,4,5 Write Cycle (11) (Vcc = 2.2 to 2.7V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter Write Cycle Time Chip Enable to Write End Address Setup to Write End Address Setup Time Write Pulse Width Write Recovery Time Data Valid to Write End Data Hold Time Write Enable to Output in High-Z Output Active from Write End BLE, BHE Setup to Write End Sym tWC tCW tAW tAS tWP tWR tDW tDH tWHZ tOW tBW 7 -35 35 30 30 0 30 0 20 0 5 30 25 - -45 45 35 35 0 35 0 25 0 5 35 25 - Unit ns ns ns ns ns ns ns ns ns ns ns Note Min Max Min Max REV. 1.3 OCT 2001 V62C2162048L(L) V62C2162048L(L) Timing Waveform of Read Cycle 1 (Address Controlled) tRC Address tOH Data Out Previous Data Valid tAA Data Valid Timing Waveform of Read Cycle 2 tRC Address tAA CE tACE tLZ(4,5) tBA tBLZ(4,5) tOE High-Z tOLZ tHZ(3,4,5) tBHZ(3,4,5) (BLE/BHE) tOHZ tOH Data Valid OE Data Out Notes (Read Cycle) 1. WE are high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to VOH or VOL levels. 4. At any given temperature and voltage condition tHZ (max.) is less than tLZ (min.) both for a given device and from device to device. 5. Transition is measured + 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 6. Device is continuously selected with CE = VIL. 7. Address valid prior to coincident with CE transition Low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 9. For test conditions, see AC Test Condition, Figure A. 8 REV. 1.3 OCT 2001 V62C2162048L(L) V62C2162048L(L) Timing Waveform of Write Cycle 1 Address tAW CE BLE/BHE tAS (4) WE Data In Data Out High-Z (Address Controlled) tWC tWR (5) tCW (3) tBW tWP (2) tDW tDH tOHZ (6) High-Z (8) tOW Timing Waveform of Write Cycle 2 tWC Address tAW CE BLE/BHE WE Data In Data Out High-Z (CE Controlled) tCW (3) tWR (5) tAS (4) tBW tWP (2) tDW tLZ tWHZ (6) tDH High-Z High-Z (8) Timing Waveform of Write Cycle 3 Address tAW CE tAS (4) BLE/BHE WE Data In Data Out High-Z tWC (BLE/BHE Controlled) tCW (3) tWR (5) tBW tWP (2) tDW tBLZ tWHZ (6) tDH High-Z High-Z (8) REV. 1.3 OCT 2001 V62C2162048L(L) 9 V62C2162048L(L) Notes (Write Cycle) All write timing is referenced from the last valid address to the first transition address. A write occurs during the overlap of a low CE and WE. A write begins at the latest transition among CE and WE going low: A write ends at the earliest transition among CE going high and WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CE going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. 6. If OE, CE and WE are in the Read Mode during this period, the I/O pins are in the output Low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state. 9. DOUT is the read data of the new address. 10. When CE is low: I/O pins are in the outputs state. The input signals in the opposite phase leading to the output should not be applied. 11. For test conditions, see AC Test Condition, Figure A. 1. 2. 10 REV. 1.3 OCT 2001 V62C2162048L(L) V62C2162048L(L) Data Retention Characteristics (L Version Only)(1) Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time(2) Symbol VDR ICCDR tCDR tR Test Condition CE > VCC - 0.2V Min 2.0 - Max - Unit V µA ns ns 1 - VIN > VCC - 0.2V or VIN < 0.2V 0 tRC Data Retention Waveform (L Version Only) (TA = 00C to +700C / -400C to +850C) Data Retention Mode VCC Vcc_typ VDR > 2.0V Vcc_typ tCDR CE VDR tR VIH VIH Notes (Write Cycle) 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. L-version includes this feature. This Parameter is samples and not 100% tested. For test conditions, see AC Test Condition, Figure A. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage. This parameter is guaranteed, but is not tested. WE is High for read cycle. CE and OE are LOW for read cycle. Address valid prior to or coincident with CE transition LOW. All read cycle timings are referenced from the last valid address to the first transtion address. CE or WE must be HIGH during address transition. All write cycle timings are referenced from the last valid address to the first transition address. 11 REV. 1.3 OCT 2001 V62C2162048L(L) V62C2162048L(L) Ordering Information Device Type* V62C2162048L-35T V62C2162048L-45T V62C2162048L-55T V62C2162048L-70T V62C2162048L-85T V62C2162048L-100T V62C2162048LL-35T V62C2162048LL-45T V62C2162048LL-55T V62C2162048LL-70T V62C2162048LL-85T V62C2162048LL-100T V62C2162048L(L)-35B V62C2162048L(L)-45B V62C2162048L(L)-55B V62C2162048L(L)-70B V62C2162048L(L)-85B V62C2162048L(L)-100B Speed 35 ns 45 ns 55 ns 70 ns 85 ns 100 ns 35 ns 45 ns 55 ns 70 ns 85 ns 100 ns 35 ns 45 ns 55 ns 70 ns 85 ns 100 ns 48-fpBGA Package 44-pin TSOP Type 2 * For Industrial temperature tested devices, an “I” designator will be added to the end of the device number. 12 REV. 1.3 OCT 2001 V62C2162048L(L) MOSEL VITELIC U.S.A. 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 WORLDWIDE OFFICES TAIWAN 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888 V62C2162048L(L) UK & IRELAND SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516 SINGAPORE 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 JAPAN ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402 GERMANY (CONTINENTAL EUROPE & ISRAEL) BENZSTRASSE 32 71083 HERRENBERG GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22 U.S. SALES OFFICES NORTHWESTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 SOUTHWESTERN 302 N. EL CAMINO REAL #200 SAN CLEMENTE, CA 92672 PHONE: 949-361-7873 FAX: 949-361-7807 CENTRAL, NORTHEASTERN & SOUTHEASTERN 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 214-826-6176 FAX: 214-828-9754 © Copyright 2001, MOSEL VITELIC Inc. Printed in U.S.A. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461