33887

Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Document order number: MC33887 Rev 9.0, 10/2004 5.0 A H-Bridge with Load Current Feedback The 33887 is a monolithic H-Bridge Power IC with a load current feedback feature making it ideal for closed-loop DC motor control. The IC incorporates internal control logic, charge pump, gate drive, and low RDS(ON) MOSFET output circuitry. The 33887 is able to control inductive loads with continuous DC load currents up to 5.0 A, and with peak current active limiting between 5.2 A and 7.8 A. Output loads can be pulse width modulated (PWM-ed) at frequencies up to 10 kHz. The load current feedback feature provides a proportional (1/375th of the load current) constant-current output suitable for monitoring by a microcontroller’s A/D input. This feature facilitates the design of closed-loop torque/speed control as well as open load detection. A Fault Status output terminal reports undervoltage, short circuit, and overtemperature conditions. Two independent inputs provide polarity control of two half-bridge totem-pole outputs. Two disable inputs force the H-Bridge outputs to tri-state (exhibit high impedance). The 33887 is parametrically specified over a temperature range of -40°C ≤ TA ≤ 125°C and a voltage range of 5.0 V ≤ V+ ≤ 28 V. The IC can also be operated up to 40 V with derating of the specifications. Features • 5.0 V to 40 V Continuous Operation • 120 mΩ RDS(ON) H-Bridge MOSFETs • TTL/CMOS Compatible Inputs • PWM Frequencies up to 10 kHz • Active Current Limiting (Regulation) via Internal Constant OFF-Time PWM (with Temperature-Dependent Threshold Reduction) • Output Short Circuit Protection (Short to V+ or Short to GND) • Undervoltage Shutdown • Fault Status Reporting • Sleep Mode with Current Draw ≤50 µA (Inputs Floating or Set to Match Default Logic States) • Pb-Free Packaging Designated by Suffix Codes VW and PNB 33887 5.0 A H-BRIDGE WITH LOAD CURRENT FEEDBACK Freescale Semiconductor, Inc... DH SUFFIX VW (Pb-FREE) SUFFIX CASE 979-04 20-TERMINAL HSOP PNB (Pb-FREE) SUFFIX CASE 1503-01 36-TERMINAL PQFN Bottom View DWB SUFFIX CASE 1390-01 54-TERMINAL SOICW-EP ORDERING INFORMATION Device MC33887DH/R2 PC33887VW/R2 MC33887PNB/R2 MC33887DWB/R2 -40°C to 125°C -40°C to 125°C -40°C to 125°C Temperature Range (TA) Package 20 HSOP 36 PQFN 54 SOICW-EP 33887 Simplified Application Diagram Simplified Application Diagram 33887 Simplified Application Diagram 5.0 V CCP 33887 33887 V+ OUT1 V+ IN OUT OUT OUT OUT OUT A/D FS EN IN1 IN2 D1 D2 FB MOTOR OUT2 PGND AGND MCU © Motorola, Inc. 2004 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Ccp C CP ChargePump Charge Pump VPWR V+ EN 5.0 V 5.0 V Regulator Regulator 80 uA 80 µA (each) (each) Freescale Semiconductor, Inc... Low-Side Current Limit, Current Limit, Ov ercurrent Short Circuit Sens e, & Sense, and Feedback Current Feedback Circuit Circuit IN1 IN2 D1 D2 25 A 25µuA OUT1 Gate Drive Gate Drive OUT2 Control Logic Logic Control OverOver Overtemperature Detection temperature Temperature Undervoltage Undervoltage Protection FS FB AGND PGND Figure 1. 33887 Simplified Internal Block Diagram 33887 2 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. Tab AGND FS IN1 V+ V+ OUT1 OUT1 FB PGND PGND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 EN IN2 D1 CCP V+ OUT2 OUT2 D2 PGND PGND Tab Freescale Semiconductor, Inc... HSOP TERMINAL DEFINITIONS A functional description of each terminal can be found in the System/Application Information section, page 19. Terminal 1 2 3 4, 5, 16 6, 7 8 9–12 13 14, 15 17 18 19 20 Tab/Pad Terminal Name AGND FS IN1 V+ OUT1 FB PGND D2 OUT2 CCP D1 IN2 EN Thermal Interface Formal Name Analog Ground Fault Status for H-Bridge Logic Input Control 1 Positive Power Supply H-Bridge Output 1 Feedback for H-Bridge Power Ground Disable 2 H-Bridge Output 2 Charge Pump Capacitor Disable 1 Logic Input Control 2 Enable Exposed Pad Thermal Interface Low-current analog signal ground. Open drain active LOW Fault Status output requiring a pullup resistor to 5.0 V. Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH). Positive supply connections Output 1 of H-Bridge. Current sensing feedback output providing ground referenced 1/375th (0.00266) of H-Bridge high-side current. High-current power ground. Active LOW input used to simultaneously tri-state disable both H-Bridge outputs. When D2 is Logic LOW, both outputs are tri-stated. Output 2 of H-Bridge. External reservoir capacitor connection for internal charge pump capacitor. Active HIGH input used to simultaneously tri-state disable both H-Bridge outputs. When D1 is Logic HIGH, both outputs are tri-stated. Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH). Logic input Enable control of device (i.e., EN logic HIGH = full operation, EN logic LOW = Sleep Mode). Exposed pad thermal interface for sinking heat from the device. Note Must be DC-coupled to analog ground and power ground via very low impedance path to prevent injection of spurious signals into IC substrate. Definition MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33887 3 Freescale Semiconductor, Inc. Transparent Top View of Package 36 35 34 33 32 31 30 29 CCP V+ V+ OUT2 OUT2 NC OUT2 OUT2 NC D1 IN2 EN V+ V+ NC AGND FS NC 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 11 28 27 26 25 24 23 22 21 20 19 NC D2 PGND PGND PGND PGND PGND PGND FB NC Freescale Semiconductor, Inc... PQFN TERMINAL DEFINITIONS A functional description of each terminal can be found in the System/Application Information section, page 19. Terminal 1, 7, 10, 16, 19, 28, 31 2 3 4 5, 6, 12, 13, 34, 35 8 9 11 14, 15, 17, 18 20 21–26 27 29, 30, 32, 33 36 Pad Terminal Name NC D1 IN2 EN V+ AGND FS IN1 OUT1 FB PGND D2 OUT2 CCP Thermal Interface Formal Name No Connect Disable 1 Logic Input Control 2 Enable Positive Power Supply Analog Ground Fault Status for H-Bridge Logic Input Control 1 H-Bridge Output 1 Feedback for H-Bridge Power Ground Disable 2 H-Bridge Output 2 Charge Pump Capacitor Exposed Pad Thermal Interface Definition No internal connection to this terminal. Active HIGH input used to simultaneously tri-state disable both H-Bridge outputs. When D1 is Logic HIGH, both outputs are tri-stated. Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH). Logic input Enable control of device (i.e., EN logic HIGH = full operation, EN logic LOW = Sleep Mode). Positive supply connections. Low-current analog signal ground. Open drain active LOW Fault Status output requiring a pullup resistor to 5.0 V. Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH). Output 1 of H-Bridge. Current feedback output providing ground referenced 1/375th ratio of H-Bridge high-side current. High-current power ground. Active LOW input used to simultaneously tri-state disable both H-Bridge outputs. When D2 is Logic LOW, both outputs are tri-stated. Output 2 of H-Bridge. External reservoir capacitor connection for internal charge pump capacitor. Exposed pad thermal interface for sinking heat from the device. Note Must be DC-coupled to analog ground and power ground via very low impedance path to prevent injection of spurious signals into IC substrate. 33887 4 For More Information On This Product, Go to: www.freescale.com IN1 V+ V+ OUT1 OUT1 NC OUT1 OUT1 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. Transparent Top View of Package Freescale Semiconductor, Inc... PGND PGND PGND PGND NC NC NC D2 NC OUT2 OUT2 OUT2 OUT2 NC V+ V+ V+ V+ NC NC NC NC CCP D1 IN2 EN NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 .35 34 33 32 31 30 29 28 PGND PGND PGND PGND NC NC NC FB NC OUT1 OUT1 OUT1 OUT1 NC V+ V+ V+ V+ NC NC NC NC IN1 FS AGND NC NC SOICW-EP TERMINAL DEFINITIONS A functional description of each terminal can be found in the System/Application Information section, page 19. Terminal 1–4, 51–54 5–7, 9, 14, 19–22, 27– 29, 33–36, 41, 46, 48–50 8 10–13 15 –18, 37–40 23 24 25 26 30 31 32 42–45 47 Pad Terminal Name PGND NC Formal Name Power Ground No Connect High-current power ground. No internal connection to this terminal. Definition D2 OUT2 V+ CCP D1 IN2 EN AGND FS IN1 OUT1 FB Thermal Interface Disable 2 H-Bridge Output 2 Positive Power Supply Charge Pump Capacitor Disable 1 Logic Input Control 2 Enable Analog Ground Fault Status for H-Bridge Logic Input Control 1 H-Bridge Output 1 Feedback for H-Bridge Exposed Pad Thermal Interface Active LOW input used to simultaneously tri-state disable both H-Bridge outputs. When D2 is Logic LOW, both outputs are tri-stated. Output 2 of H-Bridge. Positive supply connections. External reservoir capacitor connection for internal charge pump capacitor. Active HIGH input used to simultaneously tri-state disable both H-Bridge outputs. When D1 is Logic HIGH, both outputs are tri-stated. Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH). Logic input Enable control of device (i.e., EN logic HIGH = full operation, EN logic LOW = Sleep Mode). Low-current analog signal ground. Open drain active LOW Fault Status output requiring a pullup resistor to 5.0 V. Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH). Output 1 of H-Bridge. Current feedback output providing ground referenced 1/375th ratio of H-Bridge high-side current. Exposed pad thermal interface for sinking heat from the device. Note Must be DC-coupled to analog ground and power ground via very low impedance path to prevent injection of spurious signals into IC substrate. 33887 5 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. . MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit ELECTRICAL RATINGS Supply Voltage Input Voltage (Note 1) FS Status Output (Note 2) Continuous Current (Note 3) DH Suffix HSOP ESD Voltage Human Body Model (Note 4) Each Terminal to AGND Each Terminal to PGND Each Terminal to V+ Each I/O to All Other I/Os Machine Model (Note 5) VW Suffix HSOP ESD Voltage Human Body Model (Note 4) Machine Model (Note 5) PQFN ESD Voltage Human Body Model (Note 4) Machine Model (Note 5) SOICW-EP ESD Voltage Human Body Model (Note 4) Machine Model (Note 5) VESD1 VESD2 ±1600 ±200 VESD1 VESD2 ±2000 ±200 V VESD1 VESD2 ±2000 ±200 V VESD1 VESD1 VESD1 VESD1 VESD2 ±1000 ±1500 ±2000 ±2000 ±200 V V+ VIN V FS IOUT 40 -0.3 to 7.0 7.0 5.0 V V V A V Freescale Semiconductor, Inc... THERMAL RATINGS Storage Temperature Operating Temperature (Note 6) Ambient Junction Peak Package Reflow Temperature During Solder Mounting (Note 7) HSOP PQFN SOICW-EP Notes 1. 2. 3. 4. 5. 6. TA TJ TSOLDER -40 to 125 -40 to 150 °C 220 260 240 TSTG -65 to 150 °C °C Exceeding the input voltage on IN1, IN2, EN, D1, or D2 may cause a malfunction or permanent damage to the device. Exceeding the pullup resistor voltage on the open Drain FS terminal may cause permanent damage to the device. Continuous current capability so long as junction temperature is ≤ 150°C. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω). ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief nonrepetitive excursions of junction temperature above 150°C can be tolerated as long as duration does not exceed 30 seconds maximum. (nonrepetitive events are defined as not occurring more than once in 24 hours.) Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 7. 33887 6 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. MAXIMUM RATINGS (continued) All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit THERMAL RESISTANCE (AND PACKAGE DISSIPATION) RATINGS (Note 8), (Note 9), (Note 10), (Note 11) Junction-to-Board (Bottom Exposed Pad Soldered to Board) HSOP (6.0 W) PQFN (4.0 W) SOICW-EP (2.0 W) Junction-to-Ambient, Natural Convection, Single-Layer Board (1s) (Note 12) HSOP (6.0 W) PQFN (4.0 W) SOICW-EP (2.0 W) Junction-to-Ambient, Natural Convection, Four-Layer Board (2s2p) (Note 13) HSOP (6.0 W) PQFN (4.0 W) SOICW-EP (2.0 W) Junction-to-Case (Exposed Pad) (Note 14) HSOP (6.0 W) PQFN (4.0 W) SOICW-EP (2.0 W) RθJC ~0.5 ~0.9 ~1.5 RθJMA ~30 ~21.3 ~TBD °C/W RθJA ~41 ~TBD ~62 °C/W RθJB ~5.0 ~4.3 ~8.0 °C/W °C/W Freescale Semiconductor, Inc... Notes 8. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking. 9. Exposed heatsink pad plus the power and ground terminals comprise the main heat conduction paths. The actual RθJB (junction-to-PC board) values will vary depending on solder thickness and composition and copper trace thickness. Maximum current at maximum die temperature represents ~16 W of conduction loss heating in the diagonal pair of output MOSFETs. Therefore, the RθJC-total must be less than 5.0 °C/W for maximum load at 70°C ambient. Module thermal design must be planned accordingly. 10. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 11. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 12. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal. 13. Per JEDEC JESD51-6 with the board horizontal. 14. Indicates the average thermal resistance between the die and the exposed pad surface as measured by the cold plate method (MIL SPEC883 Method 1012.1) with the cold plate temperature used for the case temperature. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33887 7 Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER SUPPLY Operating Voltage Range (Note 15) Sleep State Supply Current (Note 16) IOUT = 0 A, VEN = 0 V Standby Supply Current IOUT = 0 A, VEN = 5.0 V Threshold Supply Voltage Switch-OFF Switch-ON Hysteresis V+(thres-OFF) V+(thres-ON) V+(hys) IQ(standby) – 4.15 4.5 150 – 4.4 4.75 – 20 4.65 5.0 – V V mV V+ IQ(sleep) – 25 50 mA 5.0 – 40 V µA Freescale Semiconductor, Inc... CHARGE PUMP Charge Pump Voltage V+ = 5.0 V 8.0 V ≤ V+ ≤ 40 V VCP - V+ 3.35 – – – – 20 V CONTROL INPUTS Input Voltage (IN1, IN2, D1, D2) Threshold HIGH Threshold LOW Hysteresis Input Current (IN1, IN2, D1) VIN - 0.0 V Input Current (D2, EN) V D2 = 5.0 V IINP – 25 100 VIH VIL VHYS IINP -200 -80 – µA V 3.5 – 0.7 – – 1.0 – 1.4 – µA Notes 15. Specifications are characterized over the range of 5.0 V ≤ V+ ≤ 28 V. Operation >28 V will cause some parameters to exceed listed min/max values. Refer to typical operating curves to extrapolate values for operation >28 V but ≤ 40 V. 16. IQ(sleep) is with sleep mode function enabled. 33887 8 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER OUTPUTS (OUT1, OUT2) Output ON-Resistance (Note 17) 5.0 V ≤ V+ ≤ 28 V, TJ = 25°C 8.0 V ≤ V+ ≤ 28 V, TJ = 150°C 5.0 V ≤ V+ ≤ 8.0 V, TJ = 150°C Active Current Limiting Threshold (via Internal Constant OFF-Time PWM) on Low-Side MOSFETs (Note 18) ILIM ISCH ISCL IOUT(leak) – – VF – – 2.0 °C TLIM THYS 175 10 – – 225 30 100 30 200 60 V RDS(ON) – – – 5.2 11 8.0 120 – – 6.5 – – – 225 300 7.8 – – A A A µA mΩ Freescale Semiconductor, Inc... High-Side Short Circuit Detection Threshold Low-Side Short Circuit Detection Threshold Leakage Current (Note 19) VOUT = V+ VOUT = Ground Output MOSFET Body Diode Forward Voltage Drop IOUT = 3.0 A Overtemperature Shutdown Thermal Limit Hysteresis HIGH-SIDE CURRENT SENSE FEEDBACK Feedback Current I OUT = 0 mA I OUT = 500 mA I OUT = 1.5 A I OUT = 3.0 A I OUT = 6.0 A I FB – 1.07 3.6 7.2 14.4 – 1.33 4.0 8.0 16 600 1.68 4.62 9.24 18.48 µA mA mA mA mA FAULT STATUS (Note 20) Fault Status Leakage Current (Note 21) V FS = 5.0 V Fault Status SET Voltage (Note 22) I FS = 300 µA Notes 17. 18. 19. 20. 21. 22. Output-ON resistance as measured from output to V+ and ground. Active current limitation applies only for the low-side MOSFETs. Outputs switched OFF with D1 or D2. Fault Status output is an open Drain output requiring a pullup resistor to 5.0 V. Fault Status Leakage Current is measured with Fault Status HIGH and not SET. Fault Status Set Voltage is measured with Fault Status LOW and SET with I FS = 300 µA. V FS(LOW) – – 1.0 I FS(leak) – – 10 V µA MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33887 9 Freescale Semiconductor, Inc. DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit TIMING CHARACTERISTICS PWM Frequency (Note 23) Maximum Switching Frequency During Active Current Limiting (Note 24) Output ON Delay (Note 25) V+ = 14 V Output OFF Delay (Note 25) V+ = 14 V t d (OFF) – ta tb t f, t r 2.0 t d(disable) t pod t wud t rr – – – 100 5.0 – 1.0 1.0 – 8.0 8.0 5.0 5.0 – µs ms ms ns 15 12 – 20.5 16.5 18 26 21 µs µs µs f PWM f MAX t d (ON) – – 18 µs – – 10 – – 20 kHz kHz µs Freescale Semiconductor, Inc... ILIM Output Constant-OFF Time for Low-Side MOSFETs (Note 26), (Note 27) ILIM Blanking Time for Low-Side MOSFETs (Note 28), (Note 27) Output Rise and Fall Time (Note 29) V+ = 14 V, IOUT = 3.0 A Disable Delay Time (Note 30) Power-ON Delay Time (Note 31) Wake-Up Delay Time (Note 31) Output MOSFET Body Diode Reverse Recovery Time (Note 32) Notes 23. The outputs can be PWM-controlled from an external source. This is typically done by holding one input high while applying a PWM pulse train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching frequency. See Typical Switching Waveforms, Figures 11 through 18, pp. 15–16. 24. The Maximum Switching Frequency during active current limiting is internally implemented. The internal current limit circuitry produces a constant-OFF-time pulse-width modulation of the output current. The output load’s inductance, capacitance, and resistance characteristics affect the total switching period (OFF-time + ON-time) and thus the PWM frequency during current limit. 25. Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition direction) of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from the midpoint of the input signal to the 90% point of the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from the midpoint of the input signal to the 10% point of the output response signal. See Figure 2, page 11. 26. ILIM Output Constant-OFF Time is the time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the output bridge. 27. Load currents ramping up to the current regulation threshold become limited at the ILIM value. The short circuit currents possess a di/dt that ramps up to the ISCH or ISCL threshold during the ILIM blanking time, registering as a short circuit event detection and causing the shutdown circuitry to force the output into an immediate tri-state latch-OFF. See Figures 6 and 7, page 12. Operation in Current Limit mode may cause junction temperatures to rise. Junction temperatures above ~160°C will cause the output current limit threshold to progressively “fold back”, or decrease with temperature, until ~175°C is reached, after which the TLIM thermal latch-OFF will occur. Permissible operation within this foldback region is limited to nonrepetitive transient events of duration not to exceed 30 seconds. See Figure 5, page 11. 28. ILIM Blanking Time is the time during which the current regulation threshold is ignored so that the short-circuit detection threshold comparators my have time to act. 29. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 4, page 11. 30. Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See Figure 3, page 11. 31. Parameter has been characterized but not production tested. 32. Parameter is guaranteed by design but not production tested. 33887 10 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. Timing Diagrams VIN1, IN2 (V) 5.0 50% 0 td(ON) 90% 50% td(OFF) VOUT1, 2 (V) VPWR 0 10% TIME Figure 2. Output Delay Time Freescale Semiconductor, Inc... 5.0 V 0V ∞Ω 0Ω Figure 3. Disable Delay Time VOUT1, 2 (V) V PWR 90% tf tr 90% 10% 10% 0 Figure 4. Output Switching Time IILIM,ILIM, CURRENT (A) (A) MAX OUTPUT CURRENT 6.5 6.6 Operation within this region must be limited to nonrepetitive events not to exceed 30 seconds 4.0 2.5 Thermal Shutdown 150 160 175 T J, JUNCTION TEMPERATURE (o C) Figure 5. Active Current Limiting Versus Temperature (Typical) MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33887 11 Freescale Semiconductor, Inc. ILOAD, OUTPUT CURRENT (A) >8A 6.5 Active Current Limiting on Low-Side MOSFET 0 IN1 or IN2 IN1 or IN2 Short Circuit Detection Threshold Typical Current Limit Threshold High Current Load Being Regulated via Constant-OFF-Time PWM Hard Short Detection and Latch-OFF Moderate Current Load INn, LOGIC IN [1] IN1 IN2 Freescale Semiconductor, Inc... [0] IN2 or IN1 IN2 or IN1 D1, LOGIC IN D2, LOGIC IN SF, LOGIC OUT [1] [0] [1] [0] [1] Outputs [0] Tri-Stated Outputs Operation (per Input Control Condition) Time Outputs Tri-Stated Figure 6. Operating States ILOAD, OUTPUT CURRENT (A) IOUT, CURRENT (A) 8.0 t on 6.5 ta a IShort hort Circuit Detection Threshold Overcurrent Minimum Threshold SCL S Circuit Detect Threshold tb b ta = Tristate Output OFF Time a = Output Constant-OFF Time ILIM Blanking Time ttb = Current Limit Blank Time b = Output Blanking Time Typical Current Typical PWM Load Limiting Waveform Current Limiting Waveform Hard short occurs. Hard short Detection Hard Output Hard Short is detected during t b Short Latch-OFF and output is latched-off. TIME 0.0 5.0 Figure 7. Example Short Circuit Detection Detail on Low-Side MOSFET 33887 12 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. Electrical Performance Curves 0.40 0.35 0.30 0.25 Ohms Freescale Semiconductor, Inc... 0.20 0.15 0.10 0.05 0.0 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 Volts Figure 8. Typical High-Side RDS(ON) Versus V+ 0.13 0.128 0.126 Ohms OHMS 0.124 0.122 0.12 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 Volts VPWR Figure 9. Typical Low-Side RDS(ON) Versus V+ MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33887 13 Freescale Semiconductor, Inc. 9.0 8.0 7.0 6.0 5.0 Freescale Semiconductor, Inc... OHMS Milliamperes 4.0 3.0 2.0 1.0 0.0 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 Volts VPWR Figure 10. Typical Quiescent Supply Current Versus V+ 33887 14 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. Typical Switching Waveforms Important For all plots, the following applies: • Ch2=2.0 A per division • LLOAD =533 µH @ 1.0 kHz • LLOAD =530 µH @ 10.0 kHz • RLOAD =4.0 Ω Output Voltage (OUT1) Output Voltage (OUT1) Freescale Semiconductor, Inc... IOUT IOUT Input Voltage (IN1) V+=24 V fPWM =1.0 kHz Duty Cycle=10% Input Voltage (IN1) V+=34 V fPWM =1.0 kHz Duty Cycle=90% Figure 11. Output Voltage and Current vs. Input Voltage at V+ = 24 V, PMW Frequency of 1.0 kHz, and Duty Cycle of 10% Figure 13. Output Voltage and Current vs. Input Voltage at V+ = 34 V, PMW Frequency of 1.0 kHz, and Duty Cycle of 90%, Showing Device in Current Limiting Mode Output Voltage (OUT1) Output Voltage (OUT1) IOUT IOUT Input Voltage (IN1) V+=24 V fPWM = 1.0 kHz Duty Cycle = 50% Input Voltage (IN1) V+=22 V fPWM =1.0 kHz Duty Cycle=90% Figure 12. Output Voltage and Current vs. Input Voltage at V+ = 24 V, PMW Frequency of 1.0 kHz, and Duty Cycle of 50% Figure 14. Output Voltage and Current vs. Input Voltage at V+ = 22 V, PMW Frequency of 1.0 kHz, and Duty Cycle of 90% MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33887 15 Freescale Semiconductor, Inc. Output Voltage (OUT1) Output Voltage (OUT1) IOUT IOUT Freescale Semiconductor, Inc... Input Voltage (IN1) V+=24 V fPWM =10 kHz Duty Cycle=50% Input Voltage (IN1) V+=12 V fPWM =20 kHz Duty Cycle=50% Figure 15. Output Voltage and Current vs. Input Voltage at V+ = 24 V, PMW Frequency of 10 kHz, and Duty Cycle of 50% Figure 17. Output Voltage and Current vs. Input Voltage at V+ = 12 V, PMW Frequency of 20 kHz, and Duty Cycle of 50% for a Purely Resistive Load Output Voltage (OUT1) Output Voltage (OUT1) IOUT IOUT Input Voltage (IN1) V+=24 V fPWM =10 kHz Duty Cycle=90% Input Voltage (IN1) V+=12 V fPWM =20 kHz Duty Cycle=90% Figure 16. Output Voltage and Current vs. Input Voltage at V+ = 24 V, PMW Frequency of 10 kHz, and Duty Cycle of 90% Figure 18. Output Voltage and Current vs. Input Voltage at V+ = 12 V, PMW Frequency of 20 kHz, and Duty Cycle of 90% for a Purely Resistive Load 33887 16 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. Table 1. Truth Table The tri-state conditions and the fault status are reset using D1 or D2. The truth table uses the following notations: L = LOW, H = HIGH, X = HIGH or LOW, and Z = High impedance (all output power transistors are switched off). Input Conditions Fault Status Flag Output States Device State EN Forward Reverse Freewheeling Low Freewheeling High Disable 1 (D1) H H H H H H H H H H H H H L Z D1 L L L L H X L L Z X X X X X X D2 IN1 H L L H X X Z X X X X X X X X IN2 L H L H X X X Z X X X X X X X FS OUT1 H L L H Z Z H X Z Z Z Z Z Z Z OUT2 L H L H Z Z X H Z Z Z Z Z Z Z H H H H X L H H X Z X X X X X H H H H L L H H L L L L L H H Freescale Semiconductor, Inc... Disable 2 (D2) IN1 Disconnected IN2 Disconnected D1 Disconnected D2 Disconnected Undervoltage (Note 33) Overtemperature (Note 34) Short Circuit (Note 34) Sleep Mode EN EN Disconnected Notes 33. In the case of an undervoltage condition, the outputs tri-state and the fault status is SET logic LOW. Upon undervoltage recovery, fault status is reset automatically or automatically cleared and the outputs are restored to their original operating condition. 34. When a short circuit or overtemperature condition is detected, the power outputs are tri-state latched-OFF independent of the input signals and the fault status flag is SET logic LOW. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33887 17 Freescale Semiconductor, Inc. SYSTEM/APPLICATION INFORMATION INTRODUCTION Numerous protection and operational features (speed, torque, direction, dynamic braking, PWM control, and closedloop control), in addition to the 5.0 A current capability, make the 33887 a very attractive, cost-effective solution for controlling a broad range of small DC motors. In addition, a pair of 33887 devices can be used to control bipolar stepper motors. The 33887 can also be used to excite transformer primary windings with a switched square wave to produce secondary winding AC currents. As shown in Figure 1, Simplified Internal Block Diagram, page 2, the 33887 is a fully protected monolithic H-Bridge with Enable, Fault Status reporting, and High-Side current sense feedback to accommodate closed-loop PWM control. For a DC motor to run, the input conditions need be as follows: Enable input logic HIGH, D1 input logic LOW, D2 input logic HIGH, FS flag cleared (logic HIGH), one IN logic LOW and the other IN logic HIGH (to define output polarity). The 33887 can execute dynamic braking by simultaneously turning on either both highside MOSFETs or both low-side MOSFETs in the output H-Bridge; e.g., IN1 and IN2 logic HIGH or IN1 and IN2 logic LOW. The 33887 outputs are capable of providing a continuous DC load current of 5.0 A from a 40 V V+ source. An internal charge pump supports PWM frequencies to 10 kHz. An external pullup resistor is required at the FS terminal for fault status reporting. The 33887 has an analog feedback (current mirror) output terminal (the FB terminal) that provides a constant-current source ratioed to the active high-side MOSFET. This can be used to provide “real time” monitoring of load current to facilitate closed-loop operation for motor speed/torque control. Two independent inputs (IN1 and IN2) provide control of the two totem-pole half-bridge outputs. Two disable inputs (D1 and D2) provide the means to force the H-Bridge outputs to a highimpedance state (all H-Bridge switches OFF). An EN terminal controls an enable function that allows the 33887 to be placed in a power-conserving sleep mode. The 33887 has undervoltage shutdown with automatic recovery, active current limiting, output short-circuit latch-OFF, and overtemperature latch-OFF. An undervoltage shutdown, output short-circuit latch-OFF, or overtemperature latch-OFF fault condition will cause the outputs to turn OFF (i.e., become high impedance or tri-stated) and the fault output flag to be set LOW. Either of the Disable inputs or V+ must be “toggled” to clear the fault flag. Active current limiting is accomplished by a constant OFFtime PWM method employing active current limiting threshold triggering. The active current limiting scheme is unique in that it incorporates a junction temperature-dependent current limit threshold. This means the active current limiting threshold is “ramped down” as the junction temperature increases above 160°C, until at 175°C the current will have been decreased to about 4.0 A. Above 175°C, the overtemperature shutdown (latch-OFF) occurs. This combination of features allows the device to remain in operation for 30 seconds at junction temperatures above 150°C for nonrepetitive unexpected loads. Freescale Semiconductor, Inc... 33887 18 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. FUNCTIONAL TERMINAL DESCRIPTION PGND and AGND Power and analog ground terminals should be connected together with a very low impedance connection. The outputs also have thermal shutdown (tri-state latch-OFF) with hysteresis as well as short circuit latch-OFF protection. A disable timer (time t b) incorporated to detect currents that are higher than current limit is activated at each output activation to facilitate hard short detection (see Figure 7, page 12). V+ V+ terminals are the power supply inputs to the device. All V+ terminals must be connected together on the printed circuit board with as short as possible traces offering as low impedance as possible between terminals. V+ terminals have an undervoltage threshold. If the supply voltage drops below a V+ undervoltage threshold, the output power stage switches to a tri-state condition and the fault status flag is SET and the Fault Status terminal voltage switched to a logic LOW. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input terminals and the fault status flag is automatically reset logic HIGH. CCP A filter capacitor (up to 33 nF) can be connected from the charge pump output terminal and PGND. The device can operate without the external capacitor, although the CCP capacitor helps to reduce noise and allows the device to perform at maximum speed, timing, and PWM frequency. Freescale Semiconductor, Inc... EN The EN terminal is used to place the device in a sleep mode so as to consume very low currents. When the EN terminal voltage is a logic LOW state, the device is in the sleep mode. The device is enabled and fully operational when the EN terminal voltage is logic HIGH. An internal pulldown resistor maintains the device in sleep mode in the event EN is driven through a high impedance I/O or an unpowered microcontroller, or the EN input becomes disconnected. Fault Status (FS) The FS terminal is the device fault status output. This output is an active LOW open drain structure requiring a pullup resistor to 5.0 V. Refer to Table 1, Truth Table, page 17. IN1, IN2, D1, and D2 These terminals are input control terminals used to control the outputs. These terminals are 5.0 V CMOS-compatible inputs with hysteresis. The IN1 and IN2 independently control OUT1 and OUT2, respectively. D1 and D2 are complementary inputs used to tri-state disable the H-Bridge outputs. When either D1 or D2 is SET (D1 = logic HIGH or D2 = logic LOW) in the disable state, outputs OUT1 and OUT2 are both tristate disabled; however, the rest of the device circuitry is fully operational and the supply IQ(standby) current is reduced to a few milliamperes. Refer to Table 1, Truth Table, and STATIC ELECTRICAL CHARACTERISTICS table, page 8. FB The 33887 has a feedback output (FB) for “real time” monitoring of H-Bridge high-side current to facilitate closedloop operation for motor speed and torque control. The FB terminal provides current sensing feedback of the H-Bridge high-side drivers. When running in the forward or reverse direction, a ground referenced 1/375th (0.00266) of load current is output to this terminal. Through the use of an external resistor to ground, the proportional feedback current can be converted to a proportional voltage equivalent and the controlling microcontroller can “read” the current proportional voltage with its analog-to-digital converter (ADC). This is intended to provide the user with motor current feedback for motor torque control. The resistance range for the linear operation of the FB terminal is 100