MC9S12DG128

MOTOROLA Freescale Semiconductor, Inc. MC9S12D-FamilyPP Rev 6.1, 23-Oct-02 SEMICONDUCTOR TECHNICAL DATA MC9S12D-Family Product Brief 16-Bit Microcontroller Designed for automotive multiplexing applications, members of the MC9S12D-Family of 16 bit Flashbased microcontrollers are fully pin compatible and enable users to choose between different memory and peripheral options for scalable designs. All MC9S12D-Family members are composed of standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 512K bytes of Flash EEPROM, 14K bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), three serial peripheral interfaces (SPI), IIC-bus, an enhanced capture timer (ECT), two 8-channel 10-bit analog-to-digital converters (ADC), an eight-channel pulse-width modulator (PWM), J1850 interface and up to five CAN 2.0 A, B software compatible modules (MSCAN12). System resource mapping, clock generation, interrupt control and bus interfacing are managed by the system integration module (SIM). The MC9S12D-Family has full 16-bit data paths throughout, however, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 22 I/O ports are available with interrupt capability allowing Wake-Up from STOP or WAIT mode. Freescale Semiconductor, Inc... Features NOTE Not all features listed here are available in all configurations. Additional information about D and B family inter-operability is given in: EB386 “HCS12 D-Family Compatibility Considerations” and EB388 “Using the HCS12 D-Family as a development platform for the HCS12 B family” • 16-bit CPU12 — Upward compatible with M68HC11 instruction set — Interrupt stacking and programmer’s model identical to M68HC11 — HCS12 Instruction queue — Enhanced indexed addressing • Multiplexed bus — Single chip or expanded — 16 address/16 data wide or 16 address/8 data narrow modes — External address space 1MByte for Data and Program space (112 pin package only) • Wake-up interrupt inputs depending on the package option — 8-bit port H — 2-bit port J1:0 — 2-bit port J7:6 shared with IIC, CAN4 and CAN0 module — 8-bit port P shared with PWM or SPI1,2 • Memory options — 32K, 64K, 128K, 256K, 512K Byte Flash EEPROM — 1K, 2K, 4K Byte EEPROM — 2K, 4K, 8K, 12K, 14K Byte RAM This document contains information on a new product. Specifications and information herein are subject to change without notice. © MOTOROLA 2002 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. • Analog-to-Digital Converters — One or two 8-channel modules with 10-bit resolution depending on the package option — External conversion trigger capability • Up to five 1M bit per second, CAN 2.0 A, B software compatible modules — Five receive and three transmit buffers — Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit — Four separate interrupt channels for Receive, Transmit, Error and Wake-up — Low-pass filter wake-up function in STOP mode — Loop-back for self test operation • Enhanced Capture Timer (ECT) — 16-bit main counter with 7-bit prescaler — 8 programmable input capture or output compare channels; 4 of the 8 input captures with buffer — Input capture filters and buffers, three successive captures on four channels, or two captures on four channels with a capture/compare selectable on the remaining four — Four 8-bit or two 16-bit pulse accumulators — 16-bit modulus down-counter with 4-bit prescaler — Four user-selectable delay counters for signal filtering • 8 PWM channels with programmable period and duty cycle (7 channels on 80 Pin Packages) — 8-bit, 8-channel or 16-bit, 4-channel — Separate control for each pulse width and duty cycle — Center- or left-aligned outputs — Programmable clock select logic with a wide range of frequencies • Serial interfaces — Two asynchronous serial communications interfaces (SCI) — Up to three synchronous serial peripheral interfaces (SPI) — IIC • SAE J1850 Compatible Module (BDLC) — 10.4 kbps Variable Pulse Width format — Byte level receive and transmit — 4x receive mode supported • SIM (System Integration Module) — CRG (windowed COP watchdog, real time interrupt, clock monitor, clock generation and reset) — MEBI (multiplexed external bus interface) — INT (interrupt control) • Clock generation — Phase-locked loop clock frequency multiplier — Limp home mode in absence of external clock — Clock Monitor — Low power 0.5 to 16 MHz crystal oscillator reference clock • Operating frequency for ambient temperatures TA -40°C