MMFT1N10

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MMFT1N10E/D Medium Power Field Effect Transistor N–Channel Enhancement Mode Silicon Gate TMOS E–FETt SOT–223 for Surface Mount This advanced E–FET is a TMOS Medium Power MOSFET designed to withstand high energy in the avalanche and commutation modes. This new energy efficient device also offers a drain–to–source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, dc–dc converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. The device is housed in the SOT–223 package which is designed for medium power surface mount applications. • Silicon Gate for Fast Switching Speeds • Low RDS(on) — 0.25 Ω max • The SOT–223 Package can be Soldered Using Wave or Reflow. The Formed Leads Absorb Thermal Stress During Soldering, Eliminating the Possibility of Damage to the Die • Available in 12 mm Tape and Reel Use MMFT1N10ET1 to order the 7 inch/1000 unit reel. Use MMFT1N10ET3 to order the 13 inch/4000 unit reel. MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Rating Drain–to–Source Voltage Gate–to–Source Voltage — Continuous Drain Current — Continuous Drain Current — Pulsed Total Power Dissipation @ TA = 25°C Derate above 25°C Operating and Storage Temperature Range Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 60 V, VGS = 10 V, Peak IL= 1 A, L = 0.2 mH, RG = 25 Ω) Symbol VDS VGS ID IDM PD(1) TJ, Tstg EAS 1 G S 3 MMFT1N10E Motorola Preferred Device ® MEDIUM POWER TMOS FET 1 AMP 100 VOLTS RDS(on) = 0.25 OHM 2,4 D 1 4 2 3 CASE 318E–04, STYLE 3 TO–261AA Value 100 ± 20 1 4 0.8 6.4 – 65 to 150 168 Unit Vdc Adc Watts mW/°C °C mJ DEVICE MARKING 1N10 THERMAL CHARACTERISTICS Thermal Resistance — Junction–to–Ambient (surface mounted) Maximum Temperature for Soldering Purposes, Time in Solder Bath RθJA TL 156 260 10 °C/W °C Sec (1) Power rating when mounted on FR–4 glass epoxy printed circuit board using recommended footprint. TMOS is a registered trademark of Motorola, Inc. E–FET is a trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company Preferred devices are Motorola recommended choices for future use and best overall value. REV 3 ©Motorola TMOS Power MOSFET Transistor Device Data Motorola, Inc. 1995 1 MMFT1N10E ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain–to–Source Breakdown Voltage, (VGS = 0, ID = 250 µA) Zero Gate Voltage Drain Current, (VDS = 100 V, VGS = 0) Gate–Body Leakage Current, (VGS = 20 V, VDS = 0) ON CHARACTERISTICS Gate Threshold Voltage, (VDS = VGS, ID = 1 mA) Static Drain–to–Source On–Resistance, (VGS = 10 V, ID = 0.5 A) Drain–to–Source On–Voltage, (VGS = 10 V, ID = 1 A) Forward Transconductance, (VDS = 10 V, ID = 0.5 A) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS Turn–On Delay Time Rise Time Turn–Off Delay Time Fall Time Total Gate Charge Gate–Source Charge Gate–Drain Charge (VDS = 80 V, ID = 1 A, VGS = 10 Vdc) See Figures 15 and 16 (VDD = 25 V, ID = 0.5 A VGS = 10 V, RG = 50 ohms, RGS = 25 ohms) td(on) tr td(off) tf Qg Qgs Qgd — — — — — — — 15 15 30 32 7 1.3 3.2 — — ns — — — — — nC (VDS = 20 V, VGS = 0, f = 1 MHz) Ciss Coss Crss — — — 410 145 55 — — — pF VGS(th) RDS(on) VDS(on) gFS 2 — — — — — — 2.2 4.5 0.25 0.33 — Vdc Ohms Vdc mhos V(BR)DSS IDSS IGSS 100 — — — — — — 10 100 Vdc µAdc nAdc Symbol Min Typ Max Unit SOURCE DRAIN DIODE CHARACTERISTICS(1) Forward On–Voltage Forward Turn–On Time Reverse Recovery Time IS = 1 A, VGS = 0 IS = 1 A, VGS = 0, dlS/dt = 400 A/µs, VR = 50 V VSD ton trr — — 0.8 — Vdc Limited by stray inductance 90 — ns (1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2% 2 Motorola TMOS Power MOSFET Transistor Device Data MMFT1N10E 10 8 TJ = 25°C 6V 6 VGS(TH), GATE THRESHOLD VOLTAGE (NORMALIZED) 10 V 9V 8V 7V 1.2 VDS = VGS ID = 1.0 mA 1.1 I D, DRAIN CURRENT (AMPS) 1.0 4 5V 0.9 2 VGS = 4 V 0 0 4 6 8 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 2 10 0.8 0.7 – 50 0 50 100 TJ, JUNCTION TEMP (°C) 150 Figure 1. On Region Characteristics Figure 2. Gate–Threshold Voltage Variation With Temperature RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) 4 TJ = – 55°C 0.5 VDS = 10 V 100°C VGS = 10 V I D, DRAIN CURRENT (AMPS) 0.4 TJ = 100°C 25°C – 55°C 0.1 3 25°C 0.3 2 0.2 1 0 0 2 4 6 8 10 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 0 0 2 ID, DRAIN CURRENT (AMPS) 4 Figure 3. Transfer Characteristics RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) Figure 4. On–Resistance versus Drain Current 0.5 TJ = 25°C ID = 1 A 0.5 VGS = 10 V ID = 1 A 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 4 6 8 10 12 14 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 16 0 – 50 0 50 100 TJ, JUNCTION TEMPERATURE (°C) 150 Figure 5. On–Resistance versus Gate–to–Source Voltage Figure 6. On–Resistance versus Junction Temperature Motorola TMOS Power MOSFET Transistor Device Data 3 MMFT1N10E FORWARD BIASED SAFE OPERATING AREA The FBSOA curves define the maximum drain–to–source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on an ambient temperature of 25°C and a maximum junction temperature of 150°C. Limitations for repetitive pulses at various ambient temperatures can be determined by using the thermal response curves. Motorola Application Note, AN569, “Transient Thermal Resistance– General Data and Its Use” provides detailed instructions. SWITCHING SAFE OPERATING AREA The switching safe operating area (SOA) is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, BVDSS. The switching SOA is applicable for both turn–on and turn–off of the devices for switching times less than one microsecond. 1.0 r(t), EFFECTIVE THERMAL RESISTANCE (NORMALIZED) 0.001 0.1 10 I D, DRAIN CURRENT (AMPS) 1 VGS = 20 V SINGLE PULSE TA = 25°C 20 ms 100 ms 0.1 1s DC 500 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 0.01 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 7. Maximum Rated Forward Biased Safe Operating Area D = 0.5 0.2 0.1 0.1 0.05 0.02 P(pk) RθJA(t) = r(t) RθJA RθJA = 156°C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) – TA = P(pk) RθJA(t) 0.01 0.01 SINGLE PULSE 0.001 1.0E–05 t1 t2 DUTY CYCLE, D = t1/t2 1.0E–01 1.0E–04 1.0E–03 1.0E–02 t, TIME (s) 1.0E+00 1.0E+01 Figure 8. Thermal Response COMMUTATING SAFE OPERATING AREA (CSOA) The Commutating Safe Operating Area (CSOA) of Figure 10 defines the limits of safe operation for commutated source–drain current versus re–applied drain voltage when the source–drain diode has undergone forward bias. The curve shows the limitations of IFM and peak VDS for a given rate of change of source current. It is applicable when waveforms similar to those of Figure 9 are present. Full or half–bridge PWM DC motor controllers are common applications requiring CSOA data. Device stresses increase with increasing rate of change of source current so dIS/dt is specified with a maximum value. Higher values of dIS/dt require an appropriate derating of IFM, peak VDS or both. Ultimately dIS/dt is limited primarily by device, package, and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse blocking. VDS(pk) is the peak drain–to–source voltage that the device must sustain during commutation; I FM is the maximum forward source–drain diode current just prior to the onset of commutation. VR is specified at 80% rated BVDSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero. RGS should be minimized during commutation. TJ has only a second order effect on CSOA. Stray inductances in Motorola’s test circuit are assumed to be practical minimums. dV DS /dt in excess of 10 V/ns was attained with dI S /dt of 400 A/µ s. 4 Motorola TMOS Power MOSFET Transistor Device Data MMFT1N10E 15 V VGS 0 IFM 90% IS 10% ton IRM tfrr VDS(pk) VR VDS VdsL MAX. CSOA STRESS AREA 0.25 IRM dlS/dt trr Vf Figure 9. Commutating Waveforms 5 4.5 IS , SOURCE CURRENT (AMPS) 4 3.5 3 2.5 2 1.5 1 0.5 0 0 20 40 60 80 100 120 140 VGS – VR + IFM + 20 V – IS VDS Li dIS/dt ≤ 400 A/µs RGS DUT VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VR = 80% OF RATED VDSS VdsL = Vf + Li ⋅ dlS/dt Figure 10. Commutating Safe Operating Area (CSOA) Figure 11. Commutating Safe Operating Area Test Circuit BVDSS L VDS IL VDD t RG VDD tP t, (TIME) IL(t) Figure 12. Unclamped Inductive Switching Test Circuit Figure 13. Unclamped Inductive Switching Waveforms Motorola TMOS Power MOSFET Transistor Device Data 5 MMFT1N10E VGS 1400 1200 Crss C, CAPACITANCE (pF) 1000 800 600 Ciss 400 200 0 20 15 10 5 0 5 Coss Crss 10 15 20 Coss Ciss VDS TJ = 25°C f = 1 MHz GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 14. Capacitance Variation With Voltage VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 10 VDS = 50 V 8 VDS = 80 V 6 4 TJ = 25°C ID = 1 A VGS = 10 V 2 0 0 2 4 Qg, TOTAL GATE CHARGE (nC) 6 8 Figure 15. Gate Charge versus Gate–To–Source Voltage +18 V VDD 1 mA SAME DEVICE TYPE AS DUT 0.1 µF FERRITE BEAD 47 k Vin 15 V 2N3904 100 k 47 k 10 V 100 k 2N3904 100 DUT Vin = 15 Vpk; PULSE WIDTH ≤ 100 µs, DUTY CYCLE ≤ 10%. Figure 16. Gate Charge Test Circuit 6 Motorola TMOS Power MOSFET Transistor Device Data MMFT1N10E INFORMATION FOR USING THE SOT–223 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface 0.15 3.8 0.079 2.0 between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.091 2.3 0.079 2.0 0.059 1.5 0.059 1.5 0.091 2.3 0.248 6.3 0.059 1.5 inches mm SOT–223 SOT–223 POWER DISSIPATION The power dissipation of the SOT–223 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT–223 package, PD can be calculated as follows: TJ(max) – TA RθJA dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RθJA versus drain pad area is shown in Figure 17. 160 R JA , Thermal Resistance, Junction to Ambient ( C/W) Board Material = 0.0625″ G–10/FR–4, 2 oz Copper TA = 25°C 140 0.8 Watts PD = ° 120 1.25 Watts* 1.5 Watts The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 800 milliwatts. 150°C – 25°C = 800 milliwatts PD = 156°C/W The 156°C/W for the SOT–223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 800 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT–223 package. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power 100 *Mounted on the DPAK footprint 80 0.0 0.2 0.4 0.6 A, Area (square inches) 0.8 1.0 Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad™. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. θ Figure 17. Thermal Resistance versus Drain Pad Area for the SOT–223 Package (Typical) Motorola TMOS Power MOSFET Transistor Device Data 7 MMFT1N10E SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass or stainless steel with a typical thickness of 0.008 inches. The stencil opening size for the SOT–223 package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration. SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed • When shifting from preheating to soldering, the maximum • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. temperature gradient shall be 5°C or less. 260°C for more than 10 seconds. TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177 –189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. STEP 1 PREHEAT ZONE 1 “RAMP” 200°C STEP 2 STEP 3 VENT HEATING “SOAK” ZONES 2 & 5 “RAMP” STEP 5 STEP 4 HEATING HEATING ZONES 3 & 6 ZONES 4 & 7 “SPIKE” “SOAK” 170°C 160°C STEP 6 STEP 7 VENT COOLING 205° TO 219°C PEAK AT SOLDER JOINT DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150°C 150°C 100°C 100°C 140°C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) 50°C DESIRED CURVE FOR LOW MASS ASSEMBLIES TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 18. Typical Solder Heating Profile 8 Motorola TMOS Power MOSFET Transistor Device Data MMFT1N10E PACKAGE DIMENSIONS A F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 4 S 1 2 3 B D L G J C 0.08 (0003) H M K INCHES DIM MIN MAX A 0.249 0.263 B 0.130 0.145 C 0.060 0.068 D 0.024 0.035 F 0.115 0.126 G 0.087 0.094 H 0.0008 0.0040 J 0.009 0.014 K 0.060 0.078 L 0.033 0.041 M 0_ 10 _ S 0.264 0.287 MILLIMETERS MIN MAX 6.30 6.70 3.30 3.70 1.50 1.75 0.60 0.89 2.90 3.20 2.20 2.40 0.020 0.100 0.24 0.35 1.50 2.00 0.85 1.05 0_ 10 _ 6.70 7.30 CASE 318E–04 TO–261AA SOT–223 ISSUE H STYLE 3: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN Motorola TMOS Power MOSFET Transistor Device Data 9 MMFT1N10E Motorola reserves the right to make changes without further notice to any products herein. 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