MPC565CZP40

MOTOROLA MPC565PB/D Rev. 2, 5 December 2001 SEMICONDUCTOR PRODUCT BRIEF MPC565/MPC566 Product Brief MPC565/MPC566 RISC MCU with Code Compression Option Features The MPC565 / MPC566 key features are as follows. The information inside boxes are optional features. • 40 MHz / 56 MHz operation • 56 MHz operation is available as an option. — -40° – 125 °C ambient temperature — 2.6 V ± 0.1 V external bus • External bus is compatible with external memory devices operating from 2.5 V to 3.4 V. • Extended voltage range (2.7 – 3.4 V) degrades data drive timing by 1.1 ns on date writes. — 2.6 ± 0.1 V internal logic — 5-V I/O (5.0 ± 0.25 V) • High performance RISC CPU system — High performance core • Single issue integer core • Instruction set compatible with PowerPC instruction set architecture • Precise exception model • Floating point • Code compression supported on the MPC566 — Compression reduces usage of internal or external flash memory — Compression optimized for automotive (non-cached) applications — New compression scheme increases compression performance to 40% – 50% compression — 4-Kbyte static DECRAM can be used as memory if Compression is not used. — General-purpose I/O support • On address (24) and data (32) pins • 16 GPIO in MIOS14 • Many peripheral pins can be used as GPIO when not used as primary functions • 2.6-V outputs on external bus pins • Extensive system development support — On-chip watchpoints and breakpoints — Program flow tracking — Background debug mode (BDM) Key Feature Details MPC500 System Interface (USIU, BBC, L2U) • Periodic interrupt timer, bus monitor, clocks, decrementer and time base • Clock synthesizer, power management, reset controller • External bus tolerates 5-V inputs, provides 3.3-V outputs • Enhanced interrupt controller supports a separate interrupt vector for up to eight external and 40 Internal interrupts This document contains information on a new product. Specifications and information herein are subject to change without notice. © MOTOROLA 2001, All Rights Reserved • IEEE 1149.1 JTAG test access port • Bus supports multiple master designs • Flexible memory protection units in BBC (IMPU) and L2U (DMPU) • Flexible chip selects via memory controller — 24-bit address and 32-bit data buses — Four- to 16-Mbyte (data) or 4-Gbyte (instruction) region size support — Four-beat transfer bursts, two-clock minimum bus transactions — Use with SRAM, EPROM, flash and other peripherals — Byte selects or write enables — 32-bit address decodes with bit masks — Four instruction regions — Four data regions • Default attributes available in one global entry • Attribute support for speculative accesses • Exception vector table relocation features allow exception table to be relocated to following locations: — 0x0000 0100 (normal MPC5xx exception table location) — 0x0001 0000 (0 + 64 Kbytes; second page of internal flash) — Second internal flash module — Internal SRAM — 0x0FFF_0100 (external memory space; normal MPC5xx exception table location) • USIU supports dual-mapping of flash to move part of internal flash memory to external bus for development One Mbyte Flash • Two UC3F modules, 512 Kbytes each • Page mode read • Block (64-Kbyte) erasable • External 4.75- to 5.25-V VPP program, erase, and read power supply 36-Kbyte Static RAM (CALRAM) • Composed of four- and 32-Kbyte CALRAM modules • Fast access: one clock • Keep-alive power • Soft defect detection (SDD) • 4-Kbyte calibration (overlay) RAM per module (eight Kbytes total) • Eight 512-byte overlay regions per module (16 regions total) IEEE – ISTO Nexus 5001-1999 Debug Port (Class 3) • Address (24) and data (32) pins can be used as GPIO in single chip mode • Reduced-port mode (1 MDI, 2 MDo) or full-port mode (2 MDI. 8 MDO) • Many peripheral pins can be used as GPIO when not used as primary functions • 5-V outputs with slew rate control Integrated I/O System • True 5-V I/O • Three time processing units (TPU3) — 16 channels each — Each TPU3 is a microcoded timer subsystem — One 6-Kbyte and one 4-Kbyte dual port TPU RAM (DPTRAM), one (6-Kbyte) shared by two TPU3 modules for TPU microcode and the 4-Kbyte dedicated to the third TPU3 for microcode. MPC565/MPC566 PRODUCT BRIEF MOTOROLA 2 22-Channel MIOS timer (MIOS14) • Six modulus counter sub-module (MCSM) — Four additional MCSM submodules compared to MIOS1 • 10 double action sub-module (DASM). • 12 dedicated PWM sub-modules (PWMSM) — Four additional PWM submodules compared to MIOS1 (shared with MIOS GPIO pins) • Real-time clock sub-module (MRTCSM) provides low power clock/counter — Requires external 32-KHz crystal — Uses four pins: two for 32-KHz crystal, two for power/ground. Two Queued Analog-to-Digital Converter Modules (QADC64E_A, QADC64E_B) • AMUXes providing a total of 40 analog channels. • 40 total input channels on the two modules with internal multiplexing (AMUXes) • Each QADC64E can see all 40 input channels • 10 bit A/D converter with internal sample/hold • Typical conversion time is 4 µs (250-Kbyte samples/sec) • Two conversion command queues of variable length • Automated queue modes initiated by: — External edge trigger/level gate — Software command — Periodic/interval timer, assignable to both queue 1 and 2 • 64 result registers in each QADC64E module • Conversions alternate reference (ALTREF) pin. This pin can be connected to a different reference voltage • Output data is right or left justified, signed or unsigned Message Data Link Controller (DLCMD2) Module • Two pins muxed with QSMCM_B pins. Muxing controlled by QSMCM_B PCS3 pin assignment register • SAE J1850 Class B data communications network interface compatible and ISO compatible for low-speed (< 125 Kbps) serial data communications in automotive applications • 10.4 Kbps variable pulse width (VPW) bit format • Digital noise filter, collision detection • Hardware cyclical redundancy check (CRC) generation and checking • Block mode receive and transmit supported • 4X receive mode supported (41.6 Kbps) • Digital loopback mode • In-frame response (IFR) types 0, 1, 2, and 3 supported • Dedicated register for symbol timing adjustments • Inter-module bus 3 (IMB3) slave interface • Power-saving IMB3 stop mode with automatic wakeup on network activity • Power-saving IMB3 CLOCKDIS mode • Debug mode available through IMB3 FREEZE signal or user controllable SOFT_FRZ bit • Polling and IMB3 interrupt generation with vector lookup available Three TouCAN™ Modules (TOUCAN_A, TOUCAN_B, TOUCAN_C) • 16 message buffers each, programmable I/O modes • Maskable interrupts • Programmable loop-back for self test operation • Independent of the transmission medium (external transceiver is assumed) • Open network architecture, multimaster concept • High immunity to EMI • Short latency time for high-priority messages • Low power sleep mode, with programmable wake up on bus activity MPC565/MPC566 PRODUCT BRIEF MOTOROLA 3 • TOUCAN_C pins shared with MIOS14 GPIO pins Two Queued Serial Modules with One Queued-SPI and two SCI Each (QSMCM_A, QSMCM_B) • QSMCM_A matches full MPC555/MPC556 QSMCM functionality • QSMCM_B has pins muxed with DLCMD2 module — Two pins are muxed with DLCMD2 (J1850) transmit and receive pins (B_PCS3_J1850_TX and B_RXD2_J1850_RX) — QSMCM_B vs J1850 mux control provided by QPAPCS3 bit in QSMCM pin assignment register (PQSPAR) • Queued-SPI — Provides full-duplex communication port for peripheral expansion or interprocessor communication — Up to 32 preprogrammed transfers, reducing overhead — Synchronous serial interface with baud rate of up to system clock / 4 — Four programmable peripheral-selects pins support up to 16 devices — Special wrap-around mode allows continuous sampling of a serial peripheral for efficient interfacing to serial analog-to-digital (A/D) converters • SCI — UART mode provides NRZ format and half- or full-duplex interface — 16 register receive buffer and 16 register transmit buffer on one SCI — Advanced error detection, and optional parity generation and detection — word length programmable as eight or nine bits — Separate transmitter and receiver enable bits, and double buffering of data — Wake-up functions allow the CPU to run uninterrupted until either a true idle line is detected, or a new address byte is received — External source clock for baud generation • Available in package — Plastic ball grid array (PBGA) packaging • 352/388 ball PBGA • 27 mm x 27 mm body size • 1.0 mm ball pitch MPC565/MPC566 PRODUCT BRIEF MOTOROLA 4 JTAG 512 Kbytes Flash Burst Int. 512 Kbytes Flash U-BUS USIU E-BUS MPC5xx Core + FP 4-Kbyte CALRAM_B 4-Kbyte Overlay READI L-BUS 32K CALRAM_A 28 Kbytes SRAM (No Overlay) 4-Kbyte Overlay L2U I/F QADC64E w/AMUX QADC64E w/AMUX QSMCM QSMCM UIMB I/F DLCMD2 IMB3 TPU3 6 Kbytes DPTRAM TPU3 TPU3 4 Kbytes DPTRAM Tou CAN Tou CAN Tou CAN MIOS14 Figure 1 MPC565/MPC566 Block Diagram MPC565/MPC566 PRODUCT BRIEF MOTOROLA 5 0x00 0000 0x07 FFFF 0x08 0000 0x0F FFFF 0x10 0000 0x2F C000 UC3F_A Flash 512 Kbytes UC3F_B Flash 512 Kbytes USIU Control Registers C3F_A Control (64 bytes) C3F_B Control (64 bytes) 0x2F C800 0x2F C840 0x2F C87F 0x30 0000 0x30 0040 0x30 0080 0x30 0090 0x30 1000 0x30 2000 0x30 3800 0x30 4000 0x30 4400 0x30 4800 0x30 4C00 0x30 5000 0x30 5400 0x30 5800 0x30 5C00 0x30 6000 0x30 7000 0x30 7400 0x30 7800 0x30 7C00 0x30 7F80 0x30 7FFF Reserved for Flash (2,016 Kbytes) 0x2F 7FFF 0x2F 8000 0x2F BFFF 0x2F C000 0x2F FFFF 0x30 0000 DECRAM / BBC 16 Kbytes USIU & Flash Control 16 Kbytes UIMB I/F & IMB Modules 32 Kbytes 0x30 7FFF 0x30 8000 0x37 FFFF 0x38 0000 Reserved for IMB 480 Kbytes DPTRAM_AB Registers (64 bytes) DPTRAM_C Registers (64 bytes) DLCMD2 (16 bytes) Reserved (3952 bytes) DPTRAM_C (4 Kbytes) DPTRAM_AB (6 Kbytes) Reserved (2 Kbytes) TPU3_A (1 Kbytes) TPU3_B (1 Kbytes) QADC64_A (1 Kbytes) QADC64_B (1 Kbytes) QSMCM_A (1 Kbytes) QSMCM_B (1 Kbytes) Reserved (1 Kbytes) TPU3_C (1 Kbytes) MIOS14 (4 Kbytes) TOUCAN_A (1 Kbytes) CALRAM/ Readi Control 256 bytes 0x38 00FF 0x38 0100 Reserved (L-bus Control) ~32 Kbytes 0x38 3FFF 0x38 4000 Reserved (L-bus Mem) 444 Kbytes 0x3F 6FFF 0x3F 7000 0x3F 7FFF 0x3F 8000 All 4-Kbytes can be Overlay Section TOUCAN_B (1 Kbytes) TOUCAN_C (1 Kbytes) Reserved (896 bytes) CALRAM_B (4 Kbyte) CALRAM_A (32 Kbyte) UIMB REGISTERS (128 bytes) 4-Kbyte Overlay Section 0x3F FFFF Figure 2 MPC565 / MPC566 Internal Memory Block MPC565/MPC566 PRODUCT BRIEF MOTOROLA 6 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF VDD 2 AN64_B_PQB0 3 VRH 4 VRL 5 AN84 6 AN80 7 AN48_A_PQB4 8 AN53_A_MA1_P QA1 9 VDDA 10 VSSA 11 AN76_B_PQA4 12 AN72_B_MA0_P QA0 13 AN67_B_PQB3 14 AN65_B_PQB1 15 QVDDL 16 A_TPUCH2 17 A_TPUCH4 18 A_TPUCH6 19 A_TPUCH10 20 A_TPUCH14 21 A_TPUCH1 22 B_TPUCH5 23 B_TPUCH10 24 B_TPUCH12 25 B_TPUCH14 26 VSS A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF VSS VDD AN44_ANW_A_P QB0 ALTREF AN85 AN81 AN49_A_PQB5 AN52_A_MA0_P QA0 AN56_A_PQA4 AN58_A_PQA6 AN77_B_PQA5 AN73_B_MA1_P QA1 AN69_B_PQB5 AN66_B_PQB2 QVDDL ETRIG2 A_TPUCH5 A_TPUCH8 A_TPUCH11 A_T2CLK B_TPUCH3 B_TPUCH6 B_TPUCH7 B_TPUCH13 VSS VDD VDDRTC VSS VDD AN45_ANX_A_P QB1 AN87 AN83 AN46_ANY_A_P QB2 AN50_A_PQB6 AN54_A_MA2_P QA2 AN57_A_PQA5 AN79_B_PQA7 AN75_B_PQA3 AN71_B_PQB7 AN70_B_PQB6 QVDDL ETRIG1 B_CNRX0 A_TPUCH9 A_TPUCH12 A_TPUCH15 B_TPUCH4 B_TPUCH11 B_TPUCH8 VSS VDD B_TPUCH15 EXTAL32 VDDSRAM2 VSS VDD VDDH AN86 AN82 AN47_ANZ_A_P QB3 AN51_A_PQB7 AN55_A_PQA3 AN59_A_PQA7 AN78_B_PQA6 AN74_B_MA2_P QA2 AN68_B_PQB4 QVDDL VDDH A_TPUCH3 A_TPUCH7 A_TPUCH13 A_TPUCH0 B_TPUCH9 NVDDL VSS VDD B_TPUCH2 B_TPUCH0 XTAL32 B_CNTX0 VDDSRAM1 VSS VDD B_TPUCH1 B_T2CLK MPWM17 VSSRTC C_TPUCH14 C_TPUCH15 NVDDL MPWM5_MPIO3 2B6 MPWM18 MDA11 MDA13 C_TPUCH10 C_TPUCH11 C_TPUCH12 VDDSRAM3 MDA12 MDA27 MDA28 MDA29 C_TPUCH9 C_TPUCH7 C_TPUCH8 C_T2CLK MDA30 MDA31 MPWM0 MPWM1 NOTE: This is a top down view of the balls. C_TPUCH6 C_TPUCH5 C_TPUCH3 C_TPUCH13 MPWM3 MPWM2 MPWM16 MPWM20_MPIO 32B11 C_TPUCH2 C_TPUCH1 C_TPUCH0 C_TPUCH4 MDA15 MDA14 MPWM21_MPIO C_CNTX0_MPIO 32B12 32B13 MDI_0 TCK_DSCK MDI_1 MCKI VSS VSS VSS VSS VSS VSS C_CNRX0_MPIO 32B14 MPIO32B15 MPWM19 VF0_MPIO32B0 TDI_DSDI EVTI_B RSTI_B MSEI_B VSS VSS VSS VSS VSS VSS VF1_MPIO32B1 VF2_MPIO32B2 MPWM4_MPIO3 VFLS0_MPIO32B 2B5 3 TMS MDO_4_MPIO32 MDO_6_MPIO32 MDO_5_MPIO32 B10 B8 B9 VSS VSS VSS VSS VSS VSS VDDH VFLS1_MPIO32B B_PCS0_SS_B_ B_PCS1_QGPIO 4 QGPIO0 1 MDO_7_MPIO32 B7 JCOMP MCKO MDO_0 VSS VSS VSS VSS VSS VSS B_ECK B_MISO_QGPIO B_PCS3_J1850_ B_MOSI_QGPIO 4 TX 5 MDO_1 TDO_DSDO MDO_2 IWP1_VFLS1 VSS VSS VSS VSS VSS VSS B_SCK_QGPIO6 B_PCS2_QGPIO B_TXD1_QGPO1 B_TXD2_QGPO2 2 MDO_3 MSEO_B IWP0_VFLS0 SGPIOC6_FRZ_ PTR_B VSS VSS VSS VSS VSS VSS A_MISO_QGPIO B_RXD2_J1850_ A_SCK_QGPIO6( A_TXD1_QGPO1 4 RX C3F_CLK) ADDR_SGPIOA1 ADDR_SGPIOA1 ADDR_SGPIOA8 6 7 NVDDL A_PCS2_QGPIO A_RXD1_QPI1(C A_MOSI_QGPIO A_PCS3_QGPIO 2 3F_SUP1) 5 3(C3F_IOUT) ADDR_SGPIOA1 ADDR_SGPIOA1 ADDR_SGPIOA1 ADDR_SGPIOA9 0 8 9 A_RXD2_QPI2(C A_PCS0_SS_B_ B_RXD1_QGPI1 A_TXD2_QGPO2 3F_SUP2) QGPIO0 ADDR_SGPIOA2 ADDR_SGPIOA2 ADDR_SGPIOA1 ADDR_SGPIOA1 0 1 1 2 NVDDL VFLASH A_PCS1_QGPIO 1 PULLSEL ADDR_SGPIOA2 ADDR_SGPIOA2 ADDR_SGPIOA1 ADDR_SGPIOA1 2 3 3 4 VDDF EXTCLK A_CNTXO KAPWR ADDR_SGPIOA2 ADDR_SGPIOA2 ADDR_SGPIOA1 ADDR_SGPIOA3 4 5 5 0 PORESET_B _TRST_B A_CNRXO VSSF XTAL ADDR_SGPIOA2 ADDR_SGPIOA2 ADDR_SGPIOA3 6 7 1 QVDDL HRESET_B IRQ6_B_MODCK RSTCONF_B_TE 2 XP EXTAL ADDR_SGPIOA2 8 NC QVDDL VSS VDD VDDH DATA_SGPIOD2 DATA_SGPIOD2 9 7 NVDDL DATA_SGPIOD2 DATA_SGPIOD2 DATA_SGPIOD2 4 2 0 NVDDL SGPIOC7_IRQO UT_B_LWP0 NVDDL WE_B_AT1 NVDDL CS3_B BI_B_STS_B VDDH VDD VSS QVDDL SRESET_B IRQ7_B_MODCK 3 VSSSYN ADDR_SGPIOA2 9 QVDDL VSS VDD NC DATA_SGPIOD3 DATA_SGPIOD3 DATA_SGPIOD2 DATA_SGPIOD2 DATA_SGPIOD2 DATA_SGPIOD2 DATA_SGPIOD2 DATA_SGPIOD1 IRQ4_B_AT2_SG 1 0 8 6 5 3 1 9 PIOC4 TEA_B IRQ2_B_CR_B_S GPIOC2 WE_B_AT2 CS1_B TSIZ0 B0EPEE CLKOUT VDD VSS QVDDL IRQ5_B_SGPIOC 5_MODCK1 XFC QVDDL VSS VDD IRQ3_B_KR_B_R DATA_SGPIOD1 DATA_SGPIOD1 DATA_SGPIOD1 DATA_SGPIOD1 ETRY_B_SGPIO BB_B_VF2_IWP3 DATA_SGPIOD1 DATA_SGPIOD3 DATA_SGPIOD5 DATA_SGPIOD7 DATA_SGPIOD9 1 3 5 7 C3 RD_WR_B OE_B WE_B_AT0 CS0_B BURST_B TS_B BDIP_B NC VDD VSS QVDDL VDDSYN VSS VDD IRQ0_B_SGPIOC DATA_SGPIOD1 DATA_SGPIOD1 DATA_SGPIOD1 DATA_SGPIOD1 DATA_SGPIOD1 IRQ1_B_RSV_B_ BG_B_VF0_LWP BR_B_VF1_IWP2 DATA_SGPIOD0 DATA_SGPIOD2 DATA_SGPIOD4 DATA_SGPIOD6 DATA_SGPIOD8 0 0 2 4 6 8 SGPIOC1 1 WE_B_AT3 CS2_B TSIZ1 TA_B EPEE ENGCLK_BUCLK NC VDD VSS QVDDL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Figure 3 MPC565 / MPC566 Ball Diagram MPC565/MPC566 PRODUCT BRIEF MOTOROLA 7 Ordering Information Table 1 MPC565 / MPC566 Device Name MPC565 MPC565 MPC565 MPC565 MPC566 MPC566 MPC566 MPC566 Order Part Number1 MPC565MZP40 MPC565CZP40 MPC565MZP56 MPC565CZP56 MPC566MZP40 MPC566CZP40 MPC566MZP56 MPC566CZP56 Package Info 388 PBGA 388 PBGA 388 PBGA 388 PBGA 388 PBGA 388 PBGA 388 PBGA 388 PBGA Temperature Range -40 – 125° C -40 – 85° C -40 – 125° C -40 – 85° C -40 – 125° C -40 – 85° C -40 – 125° C -40 – 85° C Maximum Frequency 40 MHz 40 MHz 56 MHz 56 MHz 40 MHz 40 MHz 56 MHz 56 MHz Code Compression No No No No Yes Yes Yes Yes NOTES: 1. Add R2 suffix for parts shipped in tape and reel media. Table 2 lists the documents that provide a complete description of the MPC565/566 and are required to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola Semiconductor documentation page on the Internet (the source for the latest information). Table 2 Available Documentation Document Number MPC565RM/D AN1821/D AN2002/D AN2109/D AN2127/D Title MPC565/MPC566 Reference Manual Exception Table Relocation and Multi-Processor Address Mapping in the Embedded MPC5XX Family MPC565/566 Nexus Interface Connector Options MPC555 Interrupts EMC Guidelines for MPC500-Based Automotive Powertrain Systems MPC565/MPC566 PRODUCT BRIEF MOTOROLA 8 MPC565/MPC566 PRODUCT BRIEF MOTOROLA 9 MPC565/MPC566 PRODUCT BRIEF MOTOROLA 10 MPC565/MPC566 PRODUCT BRIEF MOTOROLA 11 OnCE, DigitalDNA, and the DigitalDNA logo are trademarks of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 1-303-675-2140 1-800-441-2447 Technical Information Center 1-800-521-6274 JAPAN Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong 852-26668334 Home Page http://www.motorola.com/semiconductors Order Number MPC565PB/D