MPC850

A dvance Information MPC850EC/D Rev. 0.2, 04/2002 MPC850 (Rev. A/B/C) Communications Controller Hardware Specifications This document contains detailed information on power considerations, AC/DC electrical characteristics, and AC timing specifications for revision A,B, and C of the MPC850. This document contains the following topics: Topic Page Part I, “Overview” Part II, “Features” Part III, “Electrical and Thermal Characteristics” Part IV, “Thermal Characteristics” Part V, “Power Considerations” Part VI, “Bus Signal Timing” Part VII, “IEEE 1149.1 Electrical Specifications” Part VIII, “CPM Electrical Characteristics” Part IX, “Mechanical Data and Ordering Information” Part X, “Document Revision History” 1 3 7 8 9 10 37 39 61 67 Part I Overview The MPC850 is a versatile, one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications, excelling particularly in communications and networking products. The MPC850, which includes support for Ethernet, is specifically designed for cost-sensitive, remote-access, and telecommunications applications. It is provides functions similar to the MPC860, with system enhancements such as universal serial bus (USB) support and a larger (8-Kbyte) dual-port RAM. In addition to a high-performance embedded MPC8xx core, the MPC850 integrates system functions, such as a versatile memory controller and a communications processor module (CPM) that incorporates a specialized, independent RISC communications processor (referred to as the CP). This separate processor off-loads peripheral tasks from the embedded MPC8xx core. The CPM of the MPC850 supports up to seven serial channels, as follows: • One or two serial communications controllers (SCCs). The SCCs support Ethernet, ATM (MPC850SAR), HDLC and a number of other protocols, along with a transparent mode of operation. • • • • One USB channel Two serial management controllers (SMCs) One I2C port One serial peripheral interface (SPI). Table 1 shows the functionality supported by the members of the MPC850 family. Table 1. MPC850 Functionality Matrix Part MPC850 MPC850DE MPC850SAR Number of SCCs Supported 1 2 2 Ethernet Support Yes Yes Yes ATM Support Yes USB Support Yes Yes Yes Number of Multi-channel PCMCIA Slots HDLC Support Supported Yes 1 1 1 Additional documentation may be provided for parts listed in Table 1. 2 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Part II Features Figure 1 is a block diagram of the MPC850, showing its major components and the relationships among those components: 2-Kbyte I-Cache Embedded MPC8xx Core Instruction Bus Instruction MMU 1-Kbyte D-Cache Load/Store Bus Data MMU System Interface Unit Memory Controller Unified Bus Bus Interface Unit System Functions Real-Time Clock PCMCIA Interface Baud Rate Generators Parallel I/O Ports — UTOPIA (850SAR) Four Timers Interrupt Controller Dual-Port RAM 20 Virtual Serial DMA Channels and 2 Virtual IDMA Channels Peripheral Bus Communications Processor Module 32-Bit RISC Communications Processor (CP) and Program ROM Timer SCC2 TDMa SCC3 SMC1 SMC2 USB SPI I2C Time Slot Assigner Non-Multiplexed Serial Interface Figure 1. MPC850 Microprocessor Block Diagram The following list summarizes the main features of the MPC850: • Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs) — Performs branch folding and branch prediction with conditional prefetch, but without conditional execution MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 3 — 2-Kbyte instruction cache and 1-Kbyte data cache (Harvard architecture) – Caches are two-way, set-associative – Physically addressed – Cache blocks can be updated with a 4-word line burst – Least-recently used (LRU) replacement algorithm – Lockable one-line granularity — Memory management units (MMUs) with 8-entry translation lookaside buffers (TLBs) and fully-associative instruction and data TLBs — MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and eight protection groups • • Advanced on-chip emulation debug mode Data bus dynamic bus sizing for 8, 16, and 32-bit buses — Supports traditional 68000 big-endian, traditional x86 little-endian and modified little-endian memory systems — Twenty-six external address lines • • Completely static design (0–80 MHz operation) System integration unit (SIU) — Hardware bus monitor — Spurious interrupt monitor — Software watchdog — Periodic interrupt timer — Low-power stop mode — Clock synthesizer — Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture — Reset controller — IEEE 1149.1 test access port (JTAG) • Memory controller (eight banks) — Glueless interface to DRAM single in-line memory modules (SIMMs), synchronous DRAM (SDRAM), static random-access memory (SRAM), electrically programmable read-only memory (EPROM), flash EPROM, etc. — Memory controller programmable to support most size and speed memory interfaces — Boot chip-select available at reset (options for 8, 16, or 32-bit memory) — Variable block sizes, 32 Kbytes to 256 Mbytes — Selectable write protection — On-chip bus arbiter supports one external bus master — Special features for burst mode support • General-purpose timers — Four 16-bit timers or two 32-bit timers — Gate mode can enable/disable counting 4 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA — Interrupt can be masked on reference match and event capture • Interrupts — Eight external interrupt request (IRQ) lines — Twelve port pins with interrupt capability — Fifteen internal interrupt sources — Programmable priority among SCCs and USB — Programmable highest-priority request • Single socket PCMCIA-ATA interface — Master (socket) interface, release 2.1 compliant — Single PCMCIA socket — Supports eight memory or I/O windows • Communications processor module (CPM) — 32-bit, Harvard architecture, scalar RISC communications processor (CP) — Protocol-specific command sets (for example, GRACEFUL STOP TRANSMIT stops transmission after the current frame is finished or immediately if no frame is being sent and CLOSE RXBD closes the receive buffer descriptor) — Supports continuous mode transmission and reception on all serial channels — Up to 8 Kbytes of dual-port RAM — Twenty serial DMA (SDMA) channels for the serial controllers, including eight for the four USB endpoints — Three parallel I/O registers with open-drain capability • Four independent baud-rate generators (BRGs) — Can be connected to any SCC, SMC, or USB — Allow changes during operation — Autobaud support option • Two SCCs (serial communications controllers) — Ethernet/IEEE 802.3, supporting full 10-Mbps operation — HDLC/SDLC™ (all channels supported at 2 Mbps) — HDLC bus (implements an HDLC-based local area network (LAN)) — Asynchronous HDLC to support PPP (point-to-point protocol) — AppleTalk® — Universal asynchronous receiver transmitter (UART) — Synchronous UART — Serial infrared (IrDA) — Totally transparent (bit streams) — Totally transparent (frame based with optional cyclic redundancy check (CRC)) • QUICC multichannel controller (QMC) microcode features — Up to 64 independent communication channels on a single SCC — Arbitrary mapping of 0–31 channels to any of 0–31 TDM time slots MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 5 — Supports either transparent or HDLC protocols for each channel — Independent TxBDs/Rx and event/interrupt reporting for each channel • • One universal serial bus controller (USB) — Supports host controller and slave modes at 1.5 Mbps and 12 Mbps Two serial management controllers (SMCs) — UART — Transparent — General circuit interface (GCI) controller — Can be connected to the time-division-multiplexed (TDM) channel • One serial peripheral interface (SPI) — Supports master and slave modes — Supports multimaster operation on the same bus • One I2C® (interprocessor-integrated circuit) port — Supports master and slave modes — Supports multimaster environment • Time slot assigner — Allows SCCs and SMCs to run in multiplexed operation — Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user-defined — 1- or 8-bit resolution — Allows independent transmit and receive routing, frame syncs, clocking — Allows dynamic changes — Can be internally connected to four serial channels (two SCCs and two SMCs) • Low-power support — Full high: all units fully powered at high clock frequency — Full low: all units fully powered at low clock frequency — Doze: core functional units disabled except time base, decrementer, PLL, memory controller, real-time clock, and CPM in low-power standby — Sleep: all units disabled except real-time clock and periodic interrupt timer. PLL is active for fast wake-up — Deep sleep: all units disabled including PLL, except the real-time clock and periodic interrupt timer — Low-power stop: to provide lower power dissipation — Separate power supply input to operate internal logic at 2.2 V when operating at or below 25 MHz — Can be dynamically shifted between high frequency (3.3 V internal) and low frequency (2.2 V internal) operation • Debug interface — Eight comparators: four operate on instruction address, two operate on data address, and two operate on data 6 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA — The MPC850 can compare using the =, ≠, conditions to generate watchpoints — Each watchpoint can generate a breakpoint internally • 3.3-V operation with 5-V TTL compatibility on all general purpose I/O pins. Part III Electrical and Thermal Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC850. Table 2 provides the maximum ratings. Table 2. Maximum Ratings (GND = 0V) Rating Supply voltage Symbol VDDH VDDL KAPWR VDDSYN -0.3 to 4.0 -0.3 to 4.0 -0.3 to 4.0 -0.3 to 4.0 Value Unit V V V V V ˚C ˚C Input voltage 1 temperature 2 Vin Tj Tstg GND-0.3 to VDDH + 2.5 V 0 to 95 (standard) -40 to 95 (extended) -55 to +150 Junction Storage temperature range 1 Functional operating conditions are provided with the DC electrical specifications in Table 5. Absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device. CAUTION: All inputs that tolerate 5 V cannot be more than 2.5 V greater than the supply voltage. This restriction applies to power-up and normal operation (that is, if the MPC850 is unpowered, voltage greater than 2.5 V must not be applied to its inputs). 2 The MPC850, a high-frequency device in a BGA package, does not provide a guaranteed maximum ambient temperature. Only maximum junction temperature is guaranteed. It is the responsibility of the user to consider power dissipation and thermal management. Junction temperature ratings are the same regardless of frequency rating of the device. This device contains circuitry protecting against damage due to high-static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VCC). Table 3 provides the package thermal characteristics for the MPC850. MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 7 Part IV Thermal Characteristics Table 3 shows the thermal characteristics for the MPC850. Table 3. Thermal Characteristics Characteristic Thermal resistance for BGA 1 Symbol θJA θJA θJA Thermal Resistance for BGA (junction-to-case) 1 Value 40 2 31 3 24 4 8 Unit °C/W °C/W °C/W °C/W θJC For more information on the design of thermal vias on multilayer boards and BGA layout considerations in general, refer to AN-1231/D, Plastic Ball Grid Array Application Note available from your local Motorola sales office. 2 Assumes natural convection and a single layer board (no thermal vias). 3 Assumes natural convection, a multilayer board with thermal vias4, 1 watt MPC850 dissipation, and a board temperature rise of 20°C above ambient. 4 Assumes natural convection, a multilayer board with thermal vias4, 1 watt MPC850 dissipation, and a board temperature rise of 13°C above ambient. TJ = TA + (PD •θJA) PD = (VDD • IDD) + PI/O where: PI/O is the power dissipation on pins Table 4 provides power dissipation information. Table 4. Power Dissipation (PD) Characteristic Power Dissipation All Revisions (1:1) Mode 1 2 Frequency (MHz) 33 40 50 Typical 1 TBD TBD TBD Maximum 2 515 590 725 Unit mW mW mW Typical power dissipation is measured at 3.3V Maximum power dissipation is measured at 3.65 V Table 5 provides the DC electrical characteristics for the MPC850. Table 5. DC Electrical Specifications Characteristic Operating voltage at 40 MHz or less Operating voltage at 40 MHz or higher Input high voltage (address bus, data bus, EXTAL, EXTCLK, and all bus control/status signals) Input high voltage (all general purpose I/O and peripheral pins) Symbol VDDH, VDDL, KAPWR, VDDSYN VDDH, VDDL, KAPWR, VDDSYN VIH VIH Min 3.0 3.135 2.0 2.0 Max 3.6 3.465 3.6 5.5 Unit V V V V 8 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Table 5. DC Electrical Specifications (continued) Characteristic Input low voltage EXTAL, EXTCLK input high voltage Input leakage current, Vin = 5.5 V (Except TMS, TRST, DSCK and DSDI pins) Input leakage current, Vin = 3.6V (Except TMS, TRST, DSCK and DSDI pins) Input leakage current, Vin = 0V (Except TMS, TRST, DSCK and DSDI pins) Input capacitance Output high voltage, IOH = -2.0 mA, VDDH = 3.0V except XTAL, XFC, and open-drain pins Output low voltage IOL = 2.0 mA CLKOUT IOL = 3.2 mA 1 IOL = 5.3 mA 2 IOL = 7.0 mA PA[14]/USBOE, PA[12]/TXD2 IOL = 8.9 mA TS, TA, TEA, BI, BB, HRESET, SRESET 1 Symbol VIL VIHC Iin IIn IIn Cin VOH VOL Min GND 0.7*(VCC) — — — — 2.4 — Max 0.8 VCC+0.3 100 10 10 20 — 0.5 Unit V V µA µA µA pF V V A[6:31], TSIZ0/REG, TSIZ1, D[0:31], DP[0:3]/IRQ[3:6], RD/WR, BURST, RSV/IRQ2, IP_B[0:1]/IWP[0:1]/VFLS[0:1], IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3, PA[15]/USBRXD, PA[13]/RXD2, PA[9]/L1TXDA/SMRXD2, PA[8]/L1RXDA/SMTXD2, PA[7]/CLK1/TIN1/L1RCLKA/BRGO1, PA[6]/CLK2/TOUT1/TIN3, PA[5]/CLK3/TIN2/L1TCLKA/BRGO2, PA[4]/CLK4/TOUT2/TIN4, PB[31]/SPISEL, PB[30]/SPICLK/TXD3, PB[29]/SPIMOSI /RXD3, PB[28]/SPIMISO/BRGO3, PB[27]/I2CSDA/BRGO1, PB[26]/I2CSCL/BRGO2, PB[25]/SMTXD1/TXD3, PB[24]/SMRXD1/RXD3, PB[23]/SMSYN1/SDACK1, PB[22]/SMSYN2/SDACK2, PB[19]/L1ST1, PB[18]/RTS2/L1ST2, PB[17]/L1ST3, PB[16]/L1RQa/L1ST4, PC[15]/DREQ0/L1ST5, PC[14]/DREQ1/RTS2/L1ST6, PC[13]/L1ST7/RTS3, PC[12]/L1RQa/L1ST8, PC[11]/USBRXP, PC[10]/TGATE1/USBRXN, PC[9]/CTS2, PC[8]/CD2/TGATE1, PC[7]/USBTXP, PC[6]/USBTXN, PC[5]/CTS3/L1TSYNCA/SDACK1, PC[4]/CD3/L1RSYNCA, PD[15], PD[14], PD[13], PD[12], PD[11], PD[10], PD[9], PD[8], PD[7], PD[6], PD[5], PD[4], PD[3] BDIP/GPL_B5, BR, BG, FRZ/IRQ6, CS[0:5], CS6/CE1_B, CS7/CE2_B, WE0/BS_AB0/IORD, WE1/BS_AB1/IOWR, WE2/BS_AB2/PCOE, WE3/BS_AB3/PCWE, GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1, GPL_A[2:3]/GPL_B[2:3]/CS[2:3], UPWAITA/GPL_A4/AS, UPWAITB/GPL_B4, GPL_A5, ALE_B/DSCK/AT1, OP2/MODCK1/STS, OP3/MODCK2/DSDO 2 Part V Power Considerations The average chip-junction temperature, TJ, in °C can be obtained from the equation: TJ = TA + (PD • θJA) where TA PD = Ambient temperature, °C = PINT + PI/O θJA = Package thermal resistance, junction to ambient, °C/W PINT = IDD x VDD, watts—chip internal power PI/O = Power dissipation on input and output pins—user determined MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 9 (1) Layout Practices For most applications PI/O < 0.3 • PINT and can be neglected. If PI/O is neglected, an approximate relationship between PD and TJ is: PD = K ÷ (TJ + 273°C) Solving equations (1) and (2) for K gives: K = PD • (TA + 273°C) + θJA • PD 2 (2) (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. 5.1 Layout Practices Each VCC pin on the MPC850 should be provided with a low-impedance path to the board’s supply. Each GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four 0.1 µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC and GND should be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes. All output pins on the MPC850 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data busses. Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. Part VI Bus Signal Timing Table 6 provides the bus operation timing for the MPC850 at 50 MHz, 66 MHz, and 80 MHz. Timing information for other bus speeds can be interpolated by equation using the MPC850 Electrical Specifications Spreadsheet found at http://www.mot.com/netcomm. The maximum bus speed supported by the MPC850 is 50 MHz. Higher-speed parts must be operated in half-speed bus mode (for example, an MPC850 used at 66 MHz must be configured for a 33 MHz bus). The timing for the MPC850 bus shown assumes a 50-pF load. This timing can be derated by 1 ns per 10 pF. Derating calculations can also be performed using the MPC850 Electrical Specifications Spreadsheet. 10 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Layout Practices Table 6. Bus Operation Timing 50 MHz Num B1 B1a Characteristic Min CLKOUT period EXTCLK to CLKOUT phase skew (EXTCLK > 15 MHz and MF 10 MHz and MF < 10) 20 -0.90 Max — 0.90 Min 30.30 -0.90 Max — 0.90 Min 25 -0.90 Max — 0.90 — — 66 MHz 1 80 MHz FFACT Cap Load (default 50 pF) — 50.00 Unit ns ns B1b -2.30 2.30 -2.30 2.30 -2.30 2.30 — 50.00 ns B1c B1d B1e B1f B1g B1h B2 B3 B4 B5 B7 CLKOUT phase jitter (EXTCLK > -0.60 15 MHz and MF 500) 2 Frequency jitter on EXTCLK 3 CLKOUT pulse width low CLKOUT width high CLKOUT rise time CLKOUT fall time CLKOUT to A[6–31], RD/WR, BURST, D[0–31], DP[0–3] invalid CLKOUT to TSIZ[0–1], REG, RSV, AT[0–3], BDIP, PTR invalid CLKOUT to BR, BG, FRZ, VFLS[0–1], VF[0–2] IWP[0–2], LWP[0–1], STS invalid 4 CLKOUT to A[6–31], RD/WR, BURST, D[0–31], DP[0–3] valid CLKOUT to TSIZ[0–1], REG, RSV, AT[0–3] BDIP, PTR valid CLKOUT to BR, BG, VFLS[0–1], VF[0–2], IWP[0–2], FRZ, LWP[0–1], STS valid 4 CLKOUT to A[6–31] RD/WR, BURST, D[0–31], DP[0–3], TSIZ[0–1], REG, RSV, AT[0–3], PTR high-Z -2.00 — — — — 8.00 8.00 — — 5.00 0.60 2.00 0.50 2.00 3.00 0.50 — — 4.00 4.00 — -0.60 -2.00 — — — — 12.12 12.12 — — 7.58 0.60 2.00 0.50 2.00 3.00 0.50 — — 4.00 4.00 — -0.60 -2.00 — — — — 10.00 10.00 — — 6.25 0.60 2.00 0.50 2.00 3.00 0.50 — — 4.00 4.00 — — — — — — — — — — — 0.250 50.00 50.00 50.00 50.00 50.00 50.00 50.00 50.00 50.00 50.00 50.00 ns ns % % % % ns ns ns ns ns B7a B7b 5.00 5.00 — — 7.58 7.58 — — 6.25 6.25 — — 0.250 0.250 50.00 50.00 ns ns B8 5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns B8a B8b 5.00 5.00 11.75 11.74 7.58 7.58 14.33 14.33 6.25 6.25 13.00 13.00 0.250 0.250 50.00 50.00 ns ns B9 5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 11 Layout Practices Table 6. Bus Operation Timing 50 MHz Num B11 Characteristic Min CLKOUT to TS, BB assertion 5.00 2.50 Max 11.00 9.25 Min 7.58 2.50 Max 13.58 9.25 Min 6.25 2.50 Max 12.25 9.25 0.250 — 66 MHz 1 (continued) 80 MHz FFACT Cap Load (default 50 pF) 50.00 50.00 Unit ns ns B11a CLKOUT to TA, BI assertion, (When driven by the memory controller or PCMCIA interface) B12 CLKOUT to TS, BB negation 5.00 2.50 11.75 11.00 7.58 2.50 14.33 11.00 6.25 2.50 13.00 11.00 0.250 — 50.00 50.00 ns ns B12a CLKOUT to TA, BI negation (when driven by the memory controller or PCMCIA interface) B13 CLKOUT to TS, BB high-Z 5.00 2.50 19.00 15.00 7.58 2.50 21.58 15.00 6.25 2.50 20.25 15.00 0.250 — 50.00 50.00 ns ns B13a CLKOUT to TA, BI high-Z, (when driven by the memory controller or PCMCIA interface) B14 B15 B16 CLKOUT to TEA assertion CLKOUT to TEA high-Z TA, BI valid to CLKOUT(setup time) 5 2.50 2.50 9.75 10.00 8.50 1.00 2.00 6.00 10.00 15.00 — — — — — — 2.50 2.50 9.75 10.00 8.50 1.00 2.00 6.00 10.00 15.00 — — — — — — 2.50 2.50 9.75 10.00 8.50 1.00 2.00 6.00 10.00 15.00 — — — — — — — — — — — — — — 50.00 50.00 50.00 50.00 50.00 50.00 50.00 50.00 ns ns ns ns ns ns ns ns B16a TEA, KR, RETRY, valid to CLKOUT (setup time) 5 B16b BB, BG, BR valid to CLKOUT (setup time) 6 B17 CLKOUT to TA, TEA, BI, BB, BG, BR valid (Hold time).5 B17a CLKOUT to KR, RETRY, except TEA valid (hold time) B18 D[0–31], DP[0–3] valid to CLKOUT rising edge (setup time) 7 CLKOUT rising edge to D[0–31], DP[0–3] valid (hold time) 7 D[0–31], DP[0–3] valid to CLKOUT falling edge (setup time) 8 CLKOUT falling edge to D[0–31], DP[0–3] valid (hold time) 8 CLKOUT rising edge to CS asserted GPCM ACS = 00 B19 B20 1.00 4.00 — — 1.00 4.00 — — 1.00 4.00 — — — — 50.00 50.00 ns ns B21 B22 2.00 5.00 — — 11.75 8.00 2.00 7.58 — — 14.33 8.00 2.00 6.25 — — 13.00 8.00 — 0.250 — — 50.00 50.00 — ns ns B22a CLKOUT falling edge to CS asserted GPCM ACS = 10, TRLX = 0,1 B22b CLKOUT falling edge to CS asserted GPCM ACS = 11, TRLX = 0, EBDF = 0 5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns 12 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Layout Practices Table 6. Bus Operation Timing 50 MHz Num Characteristic Min B22c CLKOUT falling edge to CS asserted GPCM ACS = 11, TRLX = 0, EBDF = 1 B23 CLKOUT rising edge to CS negated GPCM read access, GPCM write access ACS = 00, TRLX = 0 & CSNT = 0 A[6–31] to CS asserted GPCM ACS = 10, TRLX = 0. 7.00 Max Min Max Min 9.00 Max 16.00 0.375 14.00 11.00 18.00 66 MHz 1 (continued) 80 MHz FFACT Cap Load (default 50 pF) 50.00 Unit ns 2.00 8.00 2.00 8.00 2.00 8.00 — 50.00 ns B24 3.00 8.00 — 2.00 23.00 28.00 — — — 9.00 9.00 — — 9.00 6.00 13.00 — 2.00 36.00 43.00 — — — 9.00 9.00 — — 9.00 4.00 11.00 — 2.00 29.00 36.00 — — — 9.00 9.00 — — 9.00 0.250 0.500 — — 1.250 1.500 — 50.00 50.00 50.00 50.00 50.00 50.00 50.00 ns ns ns ns ns ns ns B24a A[6–31] to CS asserted GPCM ACS = 11, TRLX = 0 B25 B26 B27 CLKOUT rising edge to OE, WE[0–3] asserted CLKOUT rising edge to OE negated A[6–31] to CS asserted GPCM ACS = 10, TRLX = 1 B27a A[6–31] to CS asserted GPCM ACS = 11, TRLX = 1 B28 CLKOUT rising edge to WE[0–3] negated GPCM write access CSNT = 0 B28a CLKOUT falling edge to WE[0–3] 5.00 negated GPCM write access TRLX = 0,1 CSNT = 1, EBDF = 0 B28b CLKOUT falling edge to CS negated GPCM write access TRLX = 0,1 CSNT = 1, ACS = 10 or ACS = 11, EBDF = 0 B28c CLKOUT falling edge to WE[0–3] negated GPCM write access TRLX = 0,1 CSNT = 1 write access TRLX = 0, CSNT = 1, EBDF = 1 B28d CLKOUT falling edge to CS negated GPCM write access TRLX = 0,1 CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1 B29 WE[0–3] negated to D[0–31], DP[0–3] high-Z GPCM write access, CSNT = 0 — 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns 12.00 — 14.00 — 13.00 0.250 50.00 ns 7.00 14.00 11.00 18.00 9.00 16.00 0.375 50.00 ns — 14.00 — 18.00 — 16.00 0.375 50.00 ns 3.00 — 6.00 — 4.00 — 0.250 50.00 ns B29a WE[0–3] negated to D[0–31], DP[0–3] high-Z GPCM write access, TRLX = 0 CSNT = 1, EBDF = 0 8.00 — 13.00 — 11.00 — 0.500 50.00 ns MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 13 Layout Practices Table 6. Bus Operation Timing 50 MHz Num Characteristic Min B29b CS negated to D[0–31], DP[0–3], high-Z GPCM write access, ACS = 00, TRLX = 0 & CSNT = 0 B29c CS negated to D[0–31], DP[0–3] high-Z GPCM write access, TRLX = 0, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 0 B29d WE[0–3] negated to D[0–31], DP[0–3] high-Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 0 3.00 Max — Min 6.00 Max — Min 4.00 Max — 0.250 66 MHz 1 (continued) 80 MHz FFACT Cap Load (default 50 pF) 50.00 Unit ns 8.00 — 13.00 — 11.00 — 0.500 50.00 ns 28.00 — 43.00 — 36.00 — 1.500 50.00 ns B29e CS negated to D[0–31], DP[0–3] 28.00 high-Z GPCM write access, TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 0 B29f WE[0–3] negated to D[0–31], DP[0–3] high-Z GPCM write access TRLX = 0, CSNT = 1, EBDF = 1 5.00 — 43.00 — 36.00 — 1.500 50.00 ns — 9.00 — 7.00 — 0.375 50.00 ns B29g CS negated to D[0–31], DP[0–3] high-Z GPCM write access TRLX = 0, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1 B29h WE[0–3] negated to D[0–31], DP[0–3] high-Z GPCM write access TRLX = 0, CSNT = 1, EBDF = 1 B29i 5.00 — 9.00 — 7.00 — 0.375 50.00 ns 25.00 — 39.00 — 31.00 — 1.375 50.00 ns CS negated to D[0–31], DP[0–3] 25.00 high-Z GPCM write access, TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1 CS, WE[0–3] negated to A[6–31] invalid GPCM write access 9 3.00 — 39.00 — 31.00 — 1.375 50.00 ns B30 — 6.00 — 4.00 — 0.250 50.00 ns 8.00 B30a WE[0–3] negated to A[6–31] invalid GPCM write access, TRLX = 0, CSNT = 1, CS negated to A[6–31] invalid GPCM write access TRLX = 0, CSNT =1, ACS = 10 or ACS = 11, EBDF = 0 — 13.00 — 11.00 — 0.500 50.00 ns 14 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Layout Practices Table 6. Bus Operation Timing 50 MHz Num Characteristic Min 28.00 B30b WE[0–3] negated to A[6–31] invalid GPCM write access, TRLX = 1, CSNT = 1. CS negated to A[6–31] Invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 0 B30c WE[0–3] negated to A[6–31] invalid GPCM write access, TRLX = 0, CSNT = 1. CS negated to A[6–31] invalid GPCM write access, TRLX = 0, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1 5.00 Max — Min 43.00 Max — Min 36.00 Max — 1.500 66 MHz 1 (continued) 80 MHz FFACT Cap Load (default 50 pF) 50.00 Unit ns — 8.00 — 6.00 — 0.375 50.00 ns B30d WE[0–3] negated to A[6–31] 25.00 invalid GPCM write access TRLX = 1, CSNT =1, CS negated to A[6–31] invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1 B31 CLKOUT falling edge to CS valid - as requested by control bit CST4 in the corresponding word in the UPM 1.50 — 39.00 — 31.00 — 1.375 50.00 ns 6.00 1.50 6.00 1.50 6.00 — 50.00 ns B31a CLKOUT falling edge to CS valid - as requested by control bit CST1 in the corresponding word in the UPM B31b CLKOUT rising edge to CS valid - as requested by control bit CST2 in the corresponding word in the UPM B31c CLKOUT rising edge to CS valid - as requested by control bit CST3 in the corresponding word in the UPM B31d CLKOUT falling edge to CS valid - as requested by control bit CST1 in the corresponding word in the UPM EBDF = 1 B32 CLKOUT falling edge to BS valid - as requested by control bit BST4 in the corresponding word in the UPM 5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns 1.50 8.00 1.50 8.00 1.50 8.00 — 50.00 ns 5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns 9.00 14.00 13.00 18.00 11.00 16.00 0.375 50.00 ns 1.50 6.00 1.50 6.00 1.50 6.00 — 50.00 ns B32a CLKOUT falling edge to BS valid - as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 0 5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 15 Layout Practices Table 6. Bus Operation Timing 50 MHz Num Characteristic Min B32b CLKOUT rising edge to BS valid - as requested by control bit BST2 in the corresponding word in the UPM B32c CLKOUT rising edge to BS valid - as requested by control bit BST3 in the corresponding word in the UPM B32d CLKOUT falling edge to BS valid - as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 1 B33 CLKOUT falling edge to GPL valid - as requested by control bit GxT4 in the corresponding word in the UPM 1.50 Max 8.00 Min 1.50 Max 8.00 Min 1.50 Max 8.00 — 66 MHz 1 (continued) 80 MHz FFACT Cap Load (default 50 pF) 50.00 Unit ns 5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns 9.00 14.00 13.00 18.00 11.00 16.00 0.375 50.00 ns 1.50 6.00 1.50 6.00 1.50 6.00 — 50.00 ns B33a CLKOUT rising edge to GPL valid - as requested by control bit GxT3 in the corresponding word in the UPM B34 A[6–31] and D[0–31] to CS valid - as requested by control bit CST4 in the corresponding word in the UPM 5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns 3.00 — 6.00 — 4.00 — 0.250 50.00 ns B34a A[6–31] and D[0–31] to CS valid - as requested by control bit CST1 in the corresponding word in the UPM 8.00 — 13.00 — 11.00 — 0.500 50.00 ns B34b A[6–31] and D[0–31] to CS valid 13.00 - as requested by CST2 in the corresponding word in UPM B35 A[6–31] to CS valid - as requested by control bit BST4 in the corresponding word in UPM 3.00 — 21.00 — 17.00 — 0.750 50.00 ns — 6.00 — 4.00 — 0.250 50.00 ns B35a A[6–31] and D[0–31] to BS valid - as requested by BST1 in the corresponding word in the UPM 8.00 — 13.00 — 11.00 — 0.500 50.00 ns B35b A[6–31] and D[0–31] to BS valid 13.00 - as requested by control bit BST2 in the corresponding word in the UPM B36 A[6–31] and D[0–31] to GPL valid - as requested by control bit GxT4 in the corresponding word in the UPM 3.00 — 21.00 — 17.00 — 0.750 50.00 ns — 6.00 — 4.00 — 0.250 50.00 ns 16 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Layout Practices Table 6. Bus Operation Timing 50 MHz Num B37 B38 B39 B40 Characteristic Min UPWAIT valid to CLKOUT falling edge 10 CLKOUT falling edge to UPWAIT valid 10 AS valid to CLKOUT rising edge 11 1 (continued) 80 MHz FFACT Min 6.00 1.00 7.00 7.00 Max — — — — — — — — Cap Load (default 50 pF) 50.00 50.00 50.00 50.00 Unit ns ns ns ns 66 MHz Min 6.00 1.00 7.00 7.00 Max — — — — Max — — — — 6.00 1.00 7.00 7.00 A[6–31], TSIZ[0–1], RD/WR, BURST, valid to CLKOUT rising edge. TS valid to CLKOUT rising edge (setup time) CLKOUT rising edge to TS valid (hold time) AS negation to memory controller signals negation B41 B42 B43 1 7.00 2.00 — — — TBD 7.00 2.00 — — — TBD 7.00 2.00 TBD — — — — — — 50.00 50.00 50.00 ns ns ns The minima provided assume a 0 pF load, whereas maxima assume a 50pF load. For frequencies not marked on the part, new bus timing must be calculated for all frequency-dependent AC parameters. Frequency-dependent AC parameters are those with an entry in the FFactor column. AC parameters without an FFactor entry do not need to be calculated and can be taken directly from the frequency column corresponding to the frequency marked on the part. The following equations should be used in these calculations. For a frequency F, the following equations should be applied to each one of the above parameters: For minima: FFACTOR x 1000 (D50 - 20 x FFACTOR) D= + F For maxima: FFACTOR x 1000 (D50 -20 x FFACTOR) 1ns(CAP LOAD - 50) / 10 + + D= F where: D is the parameter value to the frequency required in ns F is the operation frequency in MHz D50 is the parameter value defined for 50 MHz CAP LOAD is the capacitance load on the signal in question. FFACTOR is the one defined for each of the parameters in the table. 2 Phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed value. 3 If the rate of change of the frequency of EXTAL is slow (i.e. it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time) then the maximum allowed jitter on EXTAL can be up to 2%. 4 The timing for BR output is relevant when the MPC850 is selected to work with external bus arbiter. The timing for BG output is relevant when the MPC850 is selected to work with internal bus arbiter. 5 The setup times required for TA, TEA, and BI are relevant only when they are supplied by an external device (and not when the memory controller or the PCMCIA interface drives them). 6 The timing required for BR input is relevant when the MPC850 is selected to work with the internal bus arbiter. The timing for BG input is relevant when the MPC850 is selected to work with the external bus arbiter. 7 The D[0–31] and DP[0–3] input timings B20 and B21 refer to the rising edge of the CLKOUT in which the TA input signal is asserted. MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 17 Layout Practices 8 The D[0:31] and DP[0:3] input timings B20 and B21 refer to the falling edge of CLKOUT. This timing is valid only for read accesses controlled by chip-selects controlled by the UPM in the memory controller, for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT. 9 The timing B30 refers to CS when ACS = '00' and to WE[0:3] when CSNT = '0'. 10 The signal UPWAIT is considered asynchronous to CLKOUT and synchronized internally. The timings specified in B37 and B38 are specified to enable the freeze of the UPM output signals. 11 The AS signal is considered asynchronous to CLKOUT. Figure 2 is the control timing diagram. CLKOUT 2.0 V 0.8 V A B 0.8 V 2.0 V Outputs 2.0 V 0.8 V 2.0 V 0.8 V A B Outputs 2.0 V 0.8 V D C 2.0 V 0.8 V Inputs 2.0 V 0.8 V 2.0 V 0.8 V D C Inputs 2.0 V 0.8 V 2.0 V 0.8 V A B C D Maximum output delay specification Minimum output hold time Minimum input setup time specification Minimum input hold time specification Figure 2. Control Timing 18 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Layout Practices Figure 3 provides the timing for the external clock. CLKOUT B1 B1 B4 B3 B2 B5 Figure 3. External Clock Timing Figure 4 provides the timing for the synchronous output signals. CLKOUT B8 B7 Output Signals B8a B7a Output Signals B8b B7b Output Signals B9 B9 Figure 4. Synchronous Output Signals Timing MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 19 Layout Practices Figure 5 provides the timing for the synchronous active pull-up and open-drain output signals. CLKOUT B13 B11 TS, BB B13a B11a TA, BI B14 B15 TEA B12a B12 Figure 5. Synchronous Active Pullup and Open-Drain Outputs Signals Timing Figure 6 provides the timing for the synchronous input signals. CLKOUT B16 B17 TA, BI B16a B17a TEA, KR, RETRY B16b B17 BB, BG, BR Figure 6. Synchronous Input Signals Timing 20 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Layout Practices Figure 7 provides normal case timing for input data. CLKOUT B16 B17 TA B18 B19 D[0:31], DP[0:3] Figure 7. Input Data Timing in Normal Case Figure 8 provides the timing for the input data controlled by the UPM in the memory controller. CLKOUT TA B20 B21 D[0:31], DP[0:3] Figure 8. Input Data Timing when Controlled by UPM in the Memory Controller MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 21 Layout Practices Figure 9 through Figure 12 provide the timing for the external bus read controlled by various GPCM factors. CLKOUT B11 TS B8 A[6:31] B22 CSx B25 OE B28 WE[0:3] B18 D[0:31], DP[0:3] B19 B26 B23 B12 Figure 9. External Bus Read Timing (GPCM Controlled—ACS = 00) 22 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Layout Practices CLKOUT B11 TS B8 A[6:31] B22a B12 B23 CSx B24 OE B18 D[0:31], DP[0:3] B19 B25 B26 Figure 10. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) CLKOUT B11 TS B8 A[6:31] B22c CSx B24a OE B18 D[0:31], DP[0:3] B19 B25 B26 B23 B22b B12 Figure 11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 23 Layout Practices CLKOUT B11 TS B8 A[6:31] B22a CSx B27 OE B27a B22bB22c D[0:31], DP[0:3] B18 B19 B26 B23 B12 Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, ACS = 11) 24 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Layout Practices Figure 13 through Figure 15 provide the timing for the external bus write controlled by various GPCM factors. CLKOUT B11 TS B8 A[6:31] B22 CSx B25 WE[0:3] B26 OE B8 D[0:31], DP[0:3] B9 B29 B29a B28 B23 B30 B12 Figure 13. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0) MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 25 Layout Practices CLKOUT B11 TS B8 A[6:31] B22 CSx B25 WE[0:3] B26 OE B8 D[0:31], DP[0:3] B28a B28c B9 B29aB29f B29cB29g B28bB28d B23 B30aB30c B12 Figure 14. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1) 26 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Layout Practices CLKOUT B11 TS B8 A[6:31] B22 CSx B25 WE[0:3] B26 OE B8 D[0:31], DP[0:3] B28aB28c B29d B29 B9 B29e B29i B28bB28d B23 B30bB30d B12 Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1) Figure 16 provides the timing for the external bus controlled by the UPM. MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 27 Layout Practices CLKOUT B8 A[6:31] B31a B31d B31 CSx B34 B34a B34b B32aB32d B32 BS_A[0:3], BS_B[0:3] B35 B36 B35a B35b B33 GPL_A[0–5], GPL_B[0–5] B33a B32b B32c B31b B31c Figure 16. External Bus Timing (UPM Controlled Signals) Figure 17 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT B38 CSx BS_A[0:3], BS_B[0:3] GPL_A[0–5], GPL_B[0–5] Figure 17. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing 28 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Layout Practices Figure 18 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT B38 CSx BS_A[0:3], BS_B[0:3] GPL_A[0–5], GPL_B[0–5] Figure 18. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing Figure 19 provides the timing for the synchronous external master access controlled by the GPCM. CLKOUT B41 TS B40 A[6:31], TSIZ[0:1], R/W, BURST B22 CSx B42 Figure 19. Synchronous External Master Access Timing (GPCM Handled ACS = 00) MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 29 Layout Practices Figure 20 provides the timing for the asynchronous external master memory access controlled by the GPCM. CLKOUT B39 AS B40 A[6:31], TSIZ[0:1], R/W B22 CSx Figure 20. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00) Figure 21 provides the timing for the asynchronous external master control signals negation. AS B43 CSx, WE[0:3], OE, GPLx, BS[0:3] Figure 21. Asynchronous External Master—Control Signals Negation Timing Table 7 provides interrupt timing for the MPC850. Table 7. Interrupt Timing Num I39 I40 I41 I42 I43 1 Characteristic 1 IRQx valid to CLKOUT rising edge (set up time) IRQx hold time after CLKOUT. IRQx pulse width low IRQx pulse width high IRQx edge-to-edge time 50 MHz Min 6.00 2.00 3.00 3.00 80.00 Max — — — — — 66MHz Min 6.00 2.00 3.00 3.00 121.0 Max — — — — — 80 MHz Unit Min 6.00 2.00 3.00 3.00 100.0 Max — — — — — ns ns ns ns ns The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT. The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has no direct relation with the total system interrupt latency that the MPC850 is able to support 30 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Layout Practices Figure 22 provides the interrupt detection timing for the external level-sensitive lines. CLKOUT I39 I40 IRQx Figure 22. Interrupt Detection Timing for External Level Sensitive Lines Figure 23 provides the interrupt detection timing for the external edge-sensitive lines. CLKOUT I39 I41 IRQx I43 I43 I42 Figure 23. Interrupt Detection Timing for External Edge Sensitive Lines Table 8 shows the PCMCIA timing for the MPC850. Table 8. PCMCIA Timing 50MHz Num Characteristic Min P44 P45 P46 P47 P48 P49 P50 P51 P52 A[6–31], REG valid to PCMCIA strobe asserted. 1 A[6–31], REG valid to ALE negation.1 CLKOUT to REG valid CLKOUT to REG Invalid. CLKOUT to CE1, CE2 asserted. CLKOUT to CE1, CE2 negated. CLKOUT to PCOE, IORD, PCWE, IOWR assert time. CLKOUT to PCOE, IORD, PCWE, IOWR negate time. CLKOUT to ALE assert time 13.00 18.00 5.00 6.00 5.00 5.00 — 2.00 5.00 Max — — 13.00 — 13.00 13.00 11.00 11.00 13.00 Min 21.00 28.00 8.00 9.00 8.00 8.00 — 2.00 8.00 Max — — 16.00 — 16.00 16.00 11.00 11.00 16.00 Min 17.00 23.00 6.00 7.00 6.00 6.00 — 2.00 6.00 Max — — 14.00 — 14.00 14.00 11.00 11.00 14.00 0.750 1.000 0.250 0.250 0.250 0.250 — — 0.250 ns ns ns ns ns ns ns ns 66MHz 80 MHz FFACTOR Unit MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 31 Layout Practices Table 8. PCMCIA Timing (continued) 50MHz Num P53 P54 P55 P56 1 66MHz Min — 6.00 8.00 2.00 Max 16.00 — — — 80 MHz FFACTOR Unit Min — 4.00 8.00 2.00 Max 14.00 — — — 0.250 0.250 — — ns ns ns ns Characteristic Min CLKOUT to ALE negate time PCWE, IOWR negated to D[0–31] invalid.1 WAIT_B valid to CLKOUT rising edge.1 CLKOUT rising edge to WAIT_B invalid.1 — 3.00 8.00 2.00 Max 13.00 — — — PSST = 1. Otherwise add PSST times cycle time. PSHT = 0. Otherwise add PSHT times cycle time. These synchronous timings define when the WAIT_B signal is detected in order to freeze (or relieve) the PCMCIA current cycle. The WAIT_B assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. See PCMCIA Interface in the MPC850 PowerQUICC User’s Manual. Figure 24 provides the PCMCIA access cycle timing for the external bus read. CLKOUT TS P44 A[6:31] P46 REG P48 CE1/CE2 P50 PCOE, IORD P52 ALE B18 D[0:31] B19 P53 P52 P51 P49 P45 P47 Figure 24. PCMCIA Access Cycles Timing External Bus Read 32 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Layout Practices Figure 25 provides the PCMCIA access cycle timing for the external bus write. CLKOUT TS P44 A[6:31] P46 REG P48 CE1/CE2 P50 PCOE, IOWR P52 ALE B8 D[0:31] B9 P53 P52 P51 P54 P49 P45 P47 Figure 25. PCMCIA Access Cycles Timing External Bus Write Figure 26 provides the PCMCIA WAIT signals detection timing. CLKOUT P55 P56 WAIT_B Figure 26. PCMCIA WAIT Signal Detection Timing MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 33 Layout Practices Table 9 shows the PCMCIA port timing for the MPC850. Table 9. PCMCIA Port Timing 50 MHz Num P57 P58 P59 P60 1 66 MHz Min — 26.00 5.00 1.00 Max 19.00 — — — 80 MHz Unit Min — 22.00 5.00 1.00 Max 19.00 — — — ns ns ns ns Characteristic Min CLKOUT to OPx valid HRESET negated to OPx drive 1 — 18.00 5.00 1.00 Max 19.00 — — — IP_Xx valid to CLKOUT rising edge CLKOUT rising edge to IP_Xx invalid OP2 and OP3 only. Figure 27 provides the PCMCIA output port timing for the MPC850. CLKOUT P57 Output Signals HRESET P58 OP2, OP3 Figure 27. PCMCIA Output Port Timing Figure 28 provides the PCMCIA output port timing for the MPC850. CLKOUT P59 P60 Input Signals Figure 28. PCMCIA Input Port Timing 34 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Layout Practices Table 10 shows the debug port timing for the MPC850. Table 10. Debug Port Timing 50 MHz Num D61 D62 D63 D64 D65 D66 D67 Characteristic Min DSCK cycle time DSCK clock pulse width DSCK rise and fall times DSDI input data setup time DSDI data hold time DSCK low to DSDO data valid DSCK low to DSDO invalid 60.00 25.00 0.00 8.00 5.00 0.00 0.00 Max — — 3.00 — — 15.00 2.00 Min 91.00 38.00 0.00 8.00 5.00 0.00 0.00 Max — — 3.00 — — 15.00 2.00 Min 75.00 31.00 0.00 8.00 5.00 0.00 0.00 Max — — 3.00 — — 15.00 2.00 ns ns ns ns ns ns ns 66 MHz 80 MHz Unit Figure 29 provides the input timing for the debug port clock. DSCK D61 D62 D62 D63 D63 Figure 29. Debug Port Clock Input Timing Figure 30 provides the timing for the debug port. DSCK D64 D65 DSDI D66 D67 DSDO Figure 30. Debug Port Timings MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 35 Layout Practices Table 11 shows the reset timing for the MPC850. Table 11. Reset Timing 50 MHz Num R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 Configuration data to HRESET rising edge set up time Configuration data to RSTCONF rising edge set up time Configuration data hold time after RSTCONF negation Configuration data hold time after HRESET negation HRESET and RSTCONF asserted to data out drive RSTCONF negated to data out high impedance. CLKOUT of last rising edge before chip tristates HRESET to data out high impedance. DSDI, DSCK set up DSDI, DSCK hold time SRESET negated to CLKOUT rising edge for DSDI and DSCK sample Characteristic Min CLKOUT to HRESET high impedance CLKOUT to SRESET high impedance RSTCONF pulse width — — 340.00 — 350.00 350.00 0.00 0.00 — — — Max 20.00 20.00 — — — — — — 25.00 25.00 25.00 Min — — 515.00 — 505.00 350.00 0.00 0.00 — — — Max 20.00 20.00 — — — — — — 25.00 25.00 25.00 Min — — 425.00 — 425.00 350.00 0.00 0.00 — — — Max 20.00 20.00 — — — — — — 25.00 25.00 25.00 — — 17.000 — 15.000 — — — — — — ns ns ns ns ns ns ns ns ns ns 66MHz 80 MHz FFACTOR Unit R79 R80 R81 R82 60.00 0.00 160.00 — — — 90.00 0.00 242.00 — — — 75.00 0.00 200.00 — — — 3.000 — 8.000 ns ns ns Figure 31 shows the reset timing for the data bus configuration. HRESET R71 R76 RSTCONF R73 R74 D[0:31] (IN) R75 Figure 31. Reset Timing—Configuration from Data Bus 36 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Layout Practices Figure 32 provides the reset timing for the data bus weak drive during configuration. CLKOUT R69 HRESET R79 RSTCONF R77 D[0:31] (OUT) (Weak) R78 Figure 32. Reset Timing—Data Bus Weak Drive during Configuration Figure 33 provides the reset timing for the debug port configuration. CLKOUT R70 R82 SRESET R80 R81 DSCK, DSDI R80 R81 Figure 33. Reset Timing—Debug Port Configuration Part VII IEEE 1149.1 Electrical Specifications Table 12 provides the JTAG timings for the MPC850 as shown in Figure 34 to Figure 37. Table 12. JTAG Timing 50 MHz Num J82 J83 J84 J85 TCK cycle time TCK clock pulse width measured at 1.5 V TCK rise and fall times TMS, TDI data setup time Characteristic Min 100.00 40.00 0.00 5.00 Max — — 10.00 — Min 100.00 40.00 0.00 5.00 Max — — 10.00 — Min 100.00 40.00 0.00 5.00 Max — — 10.00 — ns ns ns ns 66MHz 80 MHz Unit MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 37 Layout Practices Table 12. JTAG Timing (continued) 50 MHz Num J86 J87 J88 J89 J90 J91 J92 J93 J94 J95 J96 Characteristic Min TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO data invalid TCK low to TDO high impedance TRST assert time TRST setup time to TCK low TCK falling edge to output valid TCK falling edge to output valid out of high impedance TCK falling edge to output high impedance Boundary scan input valid to TCK rising edge TCK rising edge to boundary scan input invalid 25.00 — 0.00 — 100.00 40.00 — — — 50.00 50.00 Max — 27.00 — 20.00 — — 50.00 50.00 50.00 — — Min 25.00 — 0.00 — 100.00 40.00 — — — 50.00 50.00 Max — 27.00 — 20.00 — — 50.00 50.00 50.00 — — Min 25.00 — 0.00 — 100.00 40.00 — — — 50.00 50.00 Max — 27.00 — 20.00 — — 50.00 50.00 50.00 — — ns ns ns ns ns ns ns ns ns ns ns 66MHz 80 MHz Unit TCK J82 J82 J84 J83 J83 J84 Figure 34. JTAG Test Clock Input Timing TCK J85 J86 TMS, TDI J87 J88 TDO J89 Figure 35. JTAG Test Access Port Timing Diagram 38 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA PIO AC Electrical Specifications TCK J91 J90 TRST Figure 36. JTAG TRST Timing Diagram TCK J92 Output Signals J93 Output Signals J95 Input Signals J96 J94 Figure 37. Boundary Scan (JTAG) Timing Diagram Part VIII CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module (CPM) of the MPC850. 8.1 PIO AC Electrical Specifications Table 13. Parallel I/O Timing All Frequencies Table 13 provides the parallel I/O timings for the MPC850 as shown in Figure 38. Num 29 30 31 Characteristic Min Data-in setup time to clock high Data-in hold time from clock high Clock low to data-out valid (CPU writes data, control, or direction) 15 7.5 — Max — — 25 Unit ns ns ns MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 39 IDMA Controller AC Electrical Specifications CLKOUT 29 30 DATA-IN 31 DATA-OUT Figure 38. Parallel I/O Data-In/Data-Out Timing Diagram 8.2 IDMA Controller AC Electrical Specifications Table 14. IDMA Controller Timing All Frequencies Table 14 provides the IDMA controller timings as shown in Figure 39 to Figure 42. Num 40 41 42 43 44 45 46 DREQ setup time to clock high Characteristic Min 7.00 3.00 — — — — 7.00 Max — — 12.00 12.00 20.00 15.00 — Unit ns ns ns ns ns ns ns DREQ hold time from clock high SDACK assertion delay from clock high SDACK negation delay from clock low SDACK negation delay from TA low SDACK negation delay from clock high TA assertion to falling edge of the clock setup time (applies to external TA) CLKOUT (Output) 40 DREQ (Input) 41 Figure 39. IDMA External Requests Timing Diagram 40 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA IDMA Controller AC Electrical Specifications CLKOUT (Output) TS (Output) R/W (Output) 42 DATA 46 TA (Output) 43 SDACK Figure 40. SDACK Timing Diagram—Peripheral Write, TA Sampled Low at the Falling Edge of the Clock CLKOUT (Output) TS (Output) R/W (Output) 42 DATA 44 TA (Output) SDACK Figure 41. SDACK Timing Diagram—Peripheral Write, TA Sampled High at the Falling Edge of the Clock MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 41 Baud Rate Generator AC Electrical Specifications CLKOUT (Output) TS (Output) R/W (Output) 42 DATA 45 TA (Output) SDACK Figure 42. SDACK Timing Diagram—Peripheral Read 8.3 Baud Rate Generator AC Electrical Specifications Table 15. Baud Rate Generator Timing All Frequencies Num 50 51 52 Characteristic Min BRGO rise and fall time BRGO duty cycle BRGO cycle — 40.00 40.00 Max 10.00 60.00 — ns % ns Unit Table 15 provides the baud rate generator timings as shown in Figure 43. 50 BRGOn 51 52 50 51 Figure 43. Baud Rate Generator Timing Diagram 42 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Timer AC Electrical Specifications 8.4 Timer AC Electrical Specifications Table 16. Timer Timing All Frequencies Num 61 62 63 64 65 Characteristic Min TIN/TGATE rise and fall time TIN/TGATE low time TIN/TGATE high time TIN/TGATE cycle time CLKO high to TOUT valid 10.00 1.00 2.00 3.00 3.00 Max — — — — 25.00 ns clk clk clk ns Unit Table 16 provides the baud rate generator timings as shown in Figure 44. CLKOUT 61 TIN/TGATE (Input) 61 65 TOUT (Output) 63 62 64 Figure 44. CPM General-Purpose Timers Timing Diagram 8.5 Serial Interface AC Electrical Specifications Table 17. SI Timing All Frequencies Num 70 71 71a 72 73 Characteristic Min L1RCLK, L1TCLK frequency (DSC = 0) 1, 2 L1RCLK, L1TCLK width low (DSC = 0) 2 L1RCLK, L1TCLK width high (DSC = 0) 3 Table 17 provides the serial interface timings as shown in Figure 45 to Figure 49. Unit Max SYNCCLK/2. 5 — — 15.00 — MHz ns ns ns ns — P + 10 P + 10 — 20.00 L1TXD, L1STn, L1RQ, L1xCLKO rise/fall time L1RSYNC, L1TSYNC valid to L1xCLK edge Edge (SYNC setup time) MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 43 Serial Interface AC Electrical Specifications Table 17. SI Timing (continued) All Frequencies Num 74 75 76 77 78 78A 79 80 80A 81 82 83 83A 84 85 86 87 88 1 2 Characteristic Min L1xCLK edge to L1RSYNC, L1TSYNC, invalid (SYNC hold time) L1RSYNC, L1TSYNC rise/fall time L1RXD valid to L1xCLK edge (L1RXD setup time) L1xCLK edge to L1RXD invalid (L1RXD hold time) L1xCLK edge to L1STn valid L1SYNC valid to L1STn valid L1xCLK edge to L1STn invalid L1xCLK edge to L1TXD valid L1TSYNC valid to L1TXD valid 4 4 Unit Max — 15.00 — — 45.00 45.00 45.00 55.00 55.00 42.00 16.00 or SYNCCLK/2 — — 30.00 — — — 0.00 ns ns ns ns ns ns ns ns ns ns MHz ns ns ns L1TCLK ns ns ns 35.00 — 17.00 13.00 10.00 10.00 10.00 10.00 10.00 0.00 — P + 10 P + 10 — 1.00 42.00 42.00 — L1xCLK edge to L1TXD high impedance L1RCLK, L1TCLK frequency (DSC =1) L1RCLK, L1TCLK width low (DSC =1) L1RCLK, L1TCLK width high (DSC = 1)3 L1CLK edge to L1CLKO valid (DSC = 1) L1RQ valid before falling edge of L1GR setup time2 L1GR hold time L1xCLK edge to L1SYNC valid (FSD = 00) CNT = 0000, BYT = 0, DSC = 0) L1TSYNC4 The ratio SyncCLK/L1RCLK must be greater than 2.5/1. These specs are valid for IDL mode only. 3 Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns. 4 These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later. 44 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Serial Interface AC Electrical Specifications L1RCLK (FE=0, CE=0) (Input) 71 72 L1RCLK (FE=1, CE=1) (Input) RFSD=1 75 L1RSYNC (Input) 73 74 L1RxD (Input) 76 78 L1STn (Output) 79 BIT0 77 70 71a Figure 45. SI Receive Timing Diagram with Normal Clocking (DSC = 0) MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 45 Serial Interface AC Electrical Specifications L1RCLK (FE=1, CE=1) (Input) 72 82 L1RCLK (FE=0, CE=0) (Input) RFSD=1 75 L1RSYNC (Input) 73 74 L1RXD (Input) 76 78 L1ST(4-1) (Output) 79 BIT0 77 83a 84 L1CLKO (Output) Figure 46. SI Receive Timing with Double-Speed Clocking (DSC = 1) 46 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Serial Interface AC Electrical Specifications L1TCLK (FE=0, CE=0) (Input) 71 72 L1TCLK (FE=1, CE=1) (Input) 73 TFSD=0 75 L1TSYNC (Input) 74 80a L1TxD (Output) 80 78 L1STn (Output) 79 BIT0 81 70 Figure 47. SI Transmit Timing Diagram MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 47 Serial Interface AC Electrical Specifications L1RCLK (FE=0, CE=0) (Input) 72 82 L1RCLK (FE=1, CE=1) (Input) TFSD=0 75 L1RSYNC (Input) 73 74 L1TXD (Output) BIT0 80 78a L1ST(4-1) (Output) 78 84 L1CLKO (Output) 79 81 83a Figure 48. SI Transmit Timing with Double Speed Clocking (DSC = 1) 48 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA MOTOROLA 1 73 71 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 71 74 B17 B16 72 77 B17 B16 B15 B14 B13 76 78 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M 81 B15 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M 85 86 87 L1RCLK (Input) L1RSYNC (Input) 80 L1TXD (Output) Figure 49. IDL Timing L1RXD (Input) MPC850 (Rev. A/B/C) Hardware Specifications L1ST(4-1) (Output) L1RQ (Output) L1GR (Input) Serial Interface AC Electrical Specifications 49 SCC in NMSI Mode Electrical Specifications 8.6 SCC in NMSI Mode Electrical Specifications Table 18. NMSI External Clock Timing All Frequencies Table 18 provides the NMSI external clock timing. Num 100 101 102 103 104 105 106 107 108 1 2 Characteristic Min RCLKx and TCLKx frequency 1 (x = 2, 3 for all specs in this table) RCLKx and TCLKx width low RCLKx and TCLKx rise/fall time TXDx active delay (from TCLKx falling edge) RTSx active/inactive delay (from TCLKx falling edge) CTSx setup time to TCLKx rising edge RXDx setup time to RCLKx rising edge RXDx hold time from RCLKx rising edge 2 CDx setup time to RCLKx rising edge 1/SYNCCLK 1/SYNCCLK +5 — 0.00 0.00 5.00 5.00 5.00 5.00 Max — — ns ns Unit 15.00 ns 50.00 ns 50.00 ns — — — — ns ns ns ns The ratios SyncCLK/RCLKx and SyncCLK/TCLKx must be greater than or equal to 2.25/1. Also applies to CD and CTS hold time when they are used as an external sync signal. Table 19 provides the NMSI internal clock timing. Table 19. NMSI Internal Clock Timing All Frequencies Num 100 102 103 104 105 106 107 108 1 2 Characteristic Min RCLKx and TCLKx frequency 1 (x = 2, 3 for all specs in this table) RCLKx and TCLKx rise/fall time TXDx active delay (from TCLKx falling edge) RTSx active/inactive delay (from TCLKx falling edge) CTSx setup time to TCLKx rising edge RXDx setup time to RCLKx rising edge RXDx hold time from RCLKx rising edge 2 0.00 — 0.00 0.00 40.00 40.00 0.00 40.00 Max SYNCCLK/3 — 30.00 30.00 — — — — Unit MHz ns ns ns ns ns ns ns CDx setup time to RCLKx rising edge The ratios SyncCLK/RCLKx and SyncCLK/TCLK1x must be greater or equal to 3/1. Also applies to CD and CTS hold time when they are used as an external sync signals. 50 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA SCC in NMSI Mode Electrical Specifications Figure 50 through Figure 52 show the NMSI timings. RCLKx 102 106 RXDx (Input) 107 108 CDx (Input) 102 101 100 107 CDx (SYNC Input) Figure 50. SCC NMSI Receive Timing Diagram TCLKx 102 102 101 100 TXDx (Output) 103 105 RTSx (Output) 104 104 CTSx (Input) 107 CTSx (SYNC Input) Figure 51. SCC NMSI Transmit Timing Diagram MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 51 Ethernet Electrical Specifications TCLKx 102 102 101 100 TXDx (Output) 103 RTSx (Output) 104 105 CTSx (Echo Input) 107 104 Figure 52. HDLC Bus Timing Diagram 8.7 Ethernet Electrical Specifications Table 20. Ethernet Timing All Frequencies Num 120 121 122 123 124 125 126 127 128 129 130 131 132 CLSN width high RCLKx rise/fall time (x = 2, 3 for all specs in this table) RCLKx width low RCLKx clock period 1 Characteristic Min 40.00 — 40.00 80.00 20.00 5.00 10.00 100.00 — 40.00 99.00 10.00 10.00 Max — 15.00 — 120.00 — — — — 15.00 — 101.00 50.00 50.00 ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Table 20 provides the Ethernet timings as shown in Figure 53 to Figure 55. RXDx setup time RXDx hold time RENA active delay (from RCLKx rising edge of the last data bit) RENA width low TCLKx rise/fall time TCLKx width low TCLKx clock period1 TXDx active delay (from TCLKx rising edge) TXDx inactive delay (from TCLKx rising edge) 52 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Ethernet Electrical Specifications Table 20. Ethernet Timing (continued) All Frequencies Num 133 134 138 139 1 2 Characteristic Min TENA active delay (from TCLKx rising edge) TENA inactive delay (from TCLKx rising edge) CLKOUT low to SDACK asserted 2 2 Unit Max 50.00 50.00 20.00 20.00 ns ns ns ns 10.00 10.00 — — CLKOUT low to SDACK negated The ratios SyncCLK/RCLKx and SyncCLK/TCLKx must be greater or equal to 2/1. SDACK is asserted whenever the SDMA writes the incoming frame destination address into memory. CLSN(CTSx) (Input) 120 Figure 53. Ethernet Collision Timing Diagram RCLKx 121 121 124 RXDx (Input) 125 126 127 RENA(CDx) (Input) 122 123 Last Bit Figure 54. Ethernet Receive Timing Diagram MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 53 SMC Transparent AC Electrical Specifications TCLKx 128 131 TxDx (Output) 132 133 TENA(RTSx) (Input) 134 128 130 129 RENA(CDx) (Input) (NOTE 2) NOTES: 1. Transmit clock invert (TCI) bit in GSMR is set. 2. If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the CSL bit is set in the buffer descriptor at the end of the frame transmission. Figure 55. Ethernet Transmit Timing Diagram 8.8 SMC Transparent AC Electrical Specifications Table 21. Serial Management Controller Timing All Frequencies Num 150 151 151a 152 153 154 155 1 Figure 21 provides the SMC transparent timings as shown in Figure 56. Characteristic Min SMCLKx clock period 1 SMCLKx width low SMCLKx width high SMCLKx rise/fall time SMTXDx active delay (from SMCLKx falling edge) SMRXDx/SMSYNx setup time SMRXDx/SMSYNx hold time 100.00 50.00 50.00 — 10.00 20.00 5.00 Max — — — 15.00 50.00 — — Unit ns ns ns ns ns ns ns The ratio SyncCLK/SMCLKx must be greater or equal to 2/1. 54 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA SPI Master AC Electrical Specifications SMCLKx 152 152 151 151a 150 SMTXDx (Output) 154 155 SMSYNx 154 155 SMRXDx (Input) NOTE: 1. This delay is equal to an integer number of character-length clocks. NOTE 153 Figure 56. SMC Transparent Timing Diagram 8.9 SPI Master AC Electrical Specifications Table 22. SPI Master Timing All Frequencies Num 160 161 162 163 164 165 166 167 Characteristic Min MASTER cycle time MASTER clock (SCK) high or low time MASTER data setup time (inputs) Master data hold time (inputs) Master data valid (after SCK edge) Master data hold time (outputs) Rise time output Fall time output 4 2 50.00 0.00 — 0.00 — — Max 1024 512 — — 20.00 — 15.00 15.00 tcyc tcyc ns ns ns ns ns ns Unit Table 22 provides the SPI master timings as shown in Figure 57 and Figure 58. MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 55 SPI Master AC Electrical Specifications SPICLK (CI=0) (Output) 161 161 SPICLK (CI=1) (Output) 163 162 SPIMISO (Input) msb 166 Data 165 167 SPIMOSI (Output) msb Data lsb lsb 164 166 msb msb 167 167 160 166 Figure 57. SPI Master (CP = 0) Timing Diagram SPICLK (CI=0) (Output) 161 161 SPICLK (CI=1) (Output) 163 162 SPIMISO (Input) msb 166 Data 165 167 SPIMOSI (Output) msb Data lsb lsb 164 166 msb msb 167 167 160 166 Figure 58. SPI Master (CP = 1) Timing Diagram 56 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA SPI Slave AC Electrical Specifications 8.10 SPI Slave AC Electrical Specifications Table 23 provides the SPI slave timings as shown in Figure 59 and Figure 60. Table 23. SPI Slave Timing All Frequencies Num 170 171 172 173 174 175 176 177 178 179 180 181 182 Slave cycle time Slave enable lead time Slave enable lag time Slave clock (SPICLK) high or low time Slave sequential transfer delay (does not require deselect) Slave data setup time (inputs) Slave data hold time (inputs) Slave access time Slave SPI MISO disable time Slave data valid (after SPICLK edge) Slave data hold time (outputs) Rise time (input) Fall time (input) Characteristic Min 2 15.00 15.00 1 1 20.00 20.00 — — — 0.00 — — Max — — — — — — — 50.00 50.00 50.00 — 15.00 15.00 tcyc ns ns tcyc tcyc ns ns ns ns ns ns ns ns Unit MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 57 SPI Slave AC Electrical Specifications SPISEL (Input) 172 174 SPICLK (CI=0) (Input) 173 173 SPICLK (CI=1) (Input) 177 180 SPIMISO (Output) msb 175 176 SPIMOSI (Input) msb Data Data 179 181 182 lsb msb lsb 181 182 178 Undef msb 182 170 181 171 Figure 59. SPI Slave (CP = 0) Timing Diagram 58 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA I2C AC Electrical Specifications SPISEL (Input) 172 171 SPICLK (CI=0) (Input) 173 173 SPICLK (CI=1) (Input) 177 180 SPIMISO (Output) Undef 175 176 SPIMOSI (Input) msb msb 179 181 182 Data lsb msb Data lsb 182 178 msb 182 181 181 170 174 Figure 60. SPI Slave (CP = 1) Timing Diagram 8.11 I2C AC Electrical Specifications Table 24 provides the I2C (SCL < 100 KHz) timings. Table 24. I2C Timing (SCL < 100 KHZ) All Frequencies Num 200 200 202 203 204 205 206 207 Characteristic Min SCL clock frequency (slave) SCL clock frequency (master) 1 Bus free time between transmissions Low period of SCL High period of SCL Start condition setup time Start condition hold time Data hold time 0.00 1.50 4.70 4.70 4.00 4.70 4.00 0.00 Max 100.00 100.00 — — — — — — KHz KHz µs µs µs µs µs µs Unit MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 59 I2C AC Electrical Specifications Table 24. I2C Timing (SCL < 100 KHZ) (CONTINUED) All Frequencies Num 208 209 210 211 1 Characteristic Min Data setup time SDL/SCL rise time SDL/SCL fall time Stop condition setup time 250.00 — — 4.70 Max — 1.00 300.00 — Unit ns µs ns µs SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2). The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1. Table 25 provides the I2C (SCL > 100 KHz) timings. Table 25. I2C Timing (SCL > 100 KHZ) All Frequencies Num 200 200 202 203 204 205 206 207 208 209 210 211 1 Characteristic SCL clock frequency (slave) SCL clock frequency (master) 1 Expression Min fSCL fSCL 0 BRGCLK/16512 1/(2.2 * fSCL) 1/(2.2 * fSCL) 1/(2.2 * fSCL) 1/(2.2 * fSCL) 1/(2.2 * fSCL) 0 1/(40 * fSCL) — — 1/2(2.2 * fSCL) Max BRGCLK/48 BRGCLK/48 — — — — — — — 1/(10 * fSCL) 1/(33 * fSCL) — Unit Hz Hz s s s s s s s s s s Bus free time between transmissions Low period of SCL High period of SCL Start condition setup time Start condition hold time Data hold time Data setup time SDL/SCL rise time SDL/SCL fall time Stop condition setup time SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2). The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1. 60 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA I2C AC Electrical Specifications Figure 61 shows the I2C bus timing. SDA 202 205 SCL 206 209 210 211 203 207 204 208 Figure 61. I2C Bus Timing Diagram Part IX Mechanical Data and Ordering Information Table 26 provides information on the MPC850 derivative devices. Table 26. MPC850 Derivatives Device MPC850 MPC850DE MPC850SAR 1 2 Ethernet Support N/A Yes Yes Number of SCCs 1 One Two Two 32-Channel HDLC Support N/A N/A N/A 64-Channel HDLC Support 2 N/A N/A Yes Serial Communication Controller (SCC) 50 MHz version supports 64 time slots on a time division multiplexed line using one SCC MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 61 Pin Assignments and Mechanical Dimensions of the PBGA Table 27 identifies the packages and operating frequencies available for the MPC850. Table 27. MPC850 Package/Frequency/Availability Package Type 256-Lead Plastic Ball Grid Array (ZT suffix) Frequency (MHz) 50 Temperature (Tj) 0°C to 95°C Order Number XPC850ZT50B XPC850DEZT50B XPC850SRZT50B XPC850ZT66B XPC850DEZT66B XPC850SRZT66B XPC850ZT80B XPC850DEZT80B XPC850SRZT80B XPC850CZT50B XPC850DECZT50B XPC850SRCZT50B XPC850CZT66B XPC850DECZT66B XPC850SRCZT66B XPC850CZT80B XPC850DECZT80B XPC850SRCZT80B 66 0°C to 95°C 80 0°C to 95°C 256-Lead Plastic Ball Grid Array (CZT suffix) 50 -40°C to 95°C 66 80 9.1 Pin Assignments and Mechanical Dimensions of the PBGA The original pin numbering of the MPC850 conformed to a Motorola proprietary pin numbering scheme that has since been replaced by the JEDEC pin numbering standard for this package type. To support customers that are currently using the non-JEDEC pin numbering scheme, two sets of pinouts, JEDEC and non-JEDEC, are presented in this document. 62 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Pin Assignments and Mechanical Dimensions of the PBGA Figure 62 shows the non-JEDEC pinout of the PBGA package as viewed from the top surface. T PC14 PB28 PB27 PC12 TCK PB24 PB23 PA8 PA7 VDDL PA5 PC7 PC4 PD14 PD10 PD8 R PC15 PA14 PA13 PA12 TMS TDI PC11 PB22 PC9 PB19 PA4 PB16 PD15 PD12 PD7 PD6 P PA15 PB30 PB29 PC13 PB26 TRST N/C PC10 PA6 PB18 PC5 PD13 PD9 PD4 PD5 N/C N A8 A7 PB31 N/C TDO PB25 PA9 N/C PC8 PB17 PC6 PD11 PD3 IR Q7 IRQ1 IRQ0 M A11 A9 A12 A6 D12 D13 D8 D0 L A15 A14 A13 A10 D23 D27 D4 D1 K A27 A19 A16 A17 D17 D10 D9 D11 J VDDL A20 A21 N/C GND D15 D14 D2 D3 H A29 A23 A25 A24 D22 D18 D16 D5 G A28 A30 A22 A18 D25 D20 D19 VDDL F A31 TSIZ0 A26 WE3 VDDH D28 D24 D21 D6 E WE1 TSIZ1 N/C GPLA0 D26 D31 D29 D7 D WE0 WE2 GPLA3 CS5 CS0 GPLA4 TS IRQ2 IPB7 IPB2 MODCK1 TEXP DP1 DP2 D30 CLKOUT C GPLA1 GPLA2 CS6 WR GPLA5 TEA BG IPB5 IPB1 IPB6 N/C RSTCONF W AITB DP0 DP3 N/C B CS4 CS7 CS2 GPLB4 BI BR BU RST IPB4 ALEB IR Q4 MODCK2 HRESET SRESET PORESET XFC VDDSYN A N/C 16 CS3 15 CS1 14 BDIP 13 TA 12 BB 11 IRQ6 10 IPB3 9 IPB0 8 VDDL EXTCLKEXTAL 7 6 5 V XTAL KAPWR VSSSYN1SSSYN 4 3 2 1 Figure 62. Pin Assignments for the PBGA (Top View)—non-JEDEC Standard MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 63 Pin Assignments and Mechanical Dimensions of the PBGA Figure 63 shows the JEDEC pinout of the PBGA package as viewed from the top surface. U PC14 PB28 PB27 PC12 TCK PB24 PB23 PA8 PA7 VDDL PA5 PC7 PC4 PD14 PD10 PD8 T PC15 PA14 PA13 PA12 TMS TDI PC11 PB22 PC9 PB19 PA4 PB16 PD15 PD12 PD7 PD6 R PA15 PB30 PB29 PC13 PB26 TRST N/C PC10 PA6 PB18 PC5 PD13 PD9 PD4 PD5 N/C P A8 A7 PB31 N/C TDO PB25 PA9 N/C PC8 PB17 PC6 PD11 PD3 IR Q7 IRQ1 IRQ0 N A11 A9 A12 A6 D12 D13 D8 D0 M A15 A14 A13 A10 D23 D27 D4 D1 L A27 A19 A16 A17 D17 D10 D9 D11 K VDDL A20 A21 N/C GND D15 D14 D2 D3 J A29 A23 A25 A24 D22 D18 D16 D5 H A28 A30 A22 A18 D25 D20 D19 VDDL G A31 TSIZ0 A26 WE3 VDDH D28 D24 D21 D6 F WE1 TSIZ1 N/C GPLA0 D26 D31 D29 D7 E WE0 WE2 GPLA3 CS5 CS0 GPLA4 TS IRQ2 IPB7 IPB2 MODCK1 TEXP DP1 DP2 D30 CLKOUT D GPLA1 GPLA2 CS6 WR GPLA5 TEA BG IPB5 IPB1 IPB6 N/C RSTCONF W AITB DP0 DP3 N/C C CS4 CS7 CS2 GPLB4 BI BR BU RST IPB4 ALEB IR Q4 MODCK2 HRESET SRESET PORESET XFC VDDSYN B N/C 17 CS3 16 CS1 15 BDIP 14 TA 13 BB 12 IRQ6 11 IPB3 10 IPB0 9 VDDL EXTCLKEXTAL 8 7 6 V XTAL KAPWR VSSSYN1SSSYN 5 4 3 2 Figure 63. Pin Assignments for the PBGA (Top View)—JEDEC Standard For more information on the printed circuit board layout of the PBGA package, including thermal via design and suggested pad layout, please refer to AN-1231/D, Plastic Ball Grid Array Application Note available from your local Motorola sales office. 64 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Pin Assignments and Mechanical Dimensions of the PBGA Figure 64 shows the non-JEDEC package dimensions of the PBGA. A D D2 0.35 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C. 4. PRIMARY DATUM C AND THE SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. MILLIMETERS MIN MAX 1.91 2.35 0.50 0.70 1.12 1.22 0.29 0.43 0.60 0.90 23.00 BSC 19.05 REF 19.00 20.00 23.00 BSC 19.05 REF 19.00 20.00 1.27 BSC 256X 0.20 C E E2 4X 0.20 A2 A3 A1 A C SEATING PLANE TOP VIEW B (D1) 15X DIM A A1 A2 A3 b D D1 D2 E E1 E2 e e T R P N M L K J H G F E D C B A SIDE VIEW 15X e (E1) 4X e /2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 256X b 0.30 M M CAB C BOTTOM VIEW 0.15 Figure 64. Package Dimensions for the Plastic Ball Grid Array (PBGA)—non-JEDEC Standard MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications 65 Pin Assignments and Mechanical Dimensions of the PBGA Figure 65 shows the JEDEC package dimensions of the PBGA. A D D2 0.35 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C. 4. PRIMARY DATUM C AND THE SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. MILLIMETERS MIN MAX 1.91 2.35 0.50 0.70 1.12 1.22 0.29 0.43 0.60 0.90 23.00 BSC 19.05 REF 19.00 20.00 23.00 BSC 19.05 REF 19.00 20.00 1.27 BSC 256X 0.20 C E E2 4X 0.20 A2 A3 A1 A C SEATING PLANE TOP VIEW B (D1) 15X DIM A A1 A2 A3 b D D1 D2 E E1 E2 e e U T R P N M L K J H G F E D C B SIDE VIEW 15X e (E1) 4X e /2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 256X b 0.30 M M CAB C BOTTOM VIEW 0.15 CASE 1130-01 ISSUE B Figure 65. Package Dimensions for the Plastic Ball Grid Array (PBGA)—JEDEC Standard 66 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Pin Assignments and Mechanical Dimensions of the PBGA Part X Document Revision History Table 28 lists significant changes between revisions of this document. Table 28. Document Revision History Revision 0.1 Date 11/2001 Change Removed reference to 5 Volt tolerance capability on peripheral interface pins. Replaced SI and IDL timing diagrams with better images. Put into new template, added this revision table. Put in the new power numbers and added Rev. C 0.2 04/2002 67 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors DOCUMENT COMMENTS: FAX (512) 933-2625, Attn: RISC Applications Engineering Information in this document is provided solely to enable system and software implementers to use Motorola products. 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