MPC9443

MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Order Number: MPC9443/D Rev 2, 05/2002 2.5V and 3.3V LVCMOS Clock Fanout Buffer The MPC9443 is a 2.5V and 3.3V compatible 1:16 clock distribution buffer designed for low-voltage high-performance telecom, networking and computing applications. The device supports 3.3V, 2.5V and dual supply voltage (mixed-voltage) applications. The MPC9443 offers 16 low-skew outputs which are divided into 4 individually configurable banks. Each output bank can be individually supplied by 2.5V or 3.3V, individually set to run at 1X or 1/2X of the input clock frequency or be disabled (logic low output state). Two selectable LVPECL compatible inputs support differential clock distribution systems. In addition, one selectable LVCMOS input is provided for LVCMOS clock distribution systems. The MPC9443 is specified for the extended temperature range of –40 to +85°C. Features • Configurable 16 outputs LVCMOS clock distribution buffer MPC9443 LOW VOLTAGE SUPPLY 2.5V AND 3.3V LVCMOS CLOCK FANOUT BUFFER Freescale Semiconductor, Inc... • Compatible to single, dual and mixed 3.3V/2.5V voltage supply • Output clock frequency up to 350 MHz • Designed for high-performance telecom, networking and computer applications • Supports applications requiring clock redundancy FA SUFFIX 48–LEAD LQFP PACKAGE CASE 932–03 • • • • • • Max. output skew of 250 ps (125 ps within one bank) Selectable output configurations per output bank Individually per-bank high–impedance tristate Output disable (stop in logic low state) control 48 ld LQFP package Ambient operating temperature range of –40 to 85°C Functional Description The MPC9443 is a full static design supporting clock frequencies up to 350 MHz. The signals are generated and retimed on-chip to ensure minimal skew between the four output banks. Two independent LVPECL compatible clock inputs are available. This feature supports redundant differential clock sources. In addition, the MPC9443 supports single-ended LVCMOS clock distribution systems. Each of the four output banks can be individually supplied by 2.5V or 3.3V, supporting mixed voltage applications. The FSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each output bank. The MPC9443 output banks are in high–impedance state by deasserting the OEN pins. Asserting OEN will the enable output banks. Please see the Output High–Impedance Control table on page 4 for details. The outputs can be synchronously stopped (logic low state). The outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission lines, each of the MPC9443 outputs can drive one or two traces giving the devices an effective fanout of 1:32 at VCC = 3.3V. The device is packaged in a 7x7 mm2 48-lead LQFP package. © Motorola, Inc. 2002 For More Information On This Product, 1 Go to: www.freescale.com Freescale Semiconductor, Inc. MPC9443 (pulldown) (pullup) (pulldown) (pullup) (pulldown) PCLK0 PCLK0 PCLK1 PCLK1 CCLK 0 0 1 1 Bank A CLK CLK ÷ 2 0 1 QA0 QA1 QA2 QA3 QA4 PCLK_SEL CCLK_SEL (pulldown) (pulldown) 0 1 Bank B QB0 QB1 QB2 FSELA (pulldown) (pulldown) (pulldown) (pulldown) 0 Freescale Semiconductor, Inc... FSELB FSELC FSELD Bank C QC0 QC1 1 QC2 QD0 Bank D 0 QD1 QD2 CLK_STOP OE0 OE1 (pulldown) 1 QD3 QD4 (pulldown) (pulldown) 5 Figure 1. MPC9443 Logic Diagram VCCC VCCB GND GND GND VCC QC0 QC1 QC2 QB0 QB1 QB2 VCCA QA4 QA3 QA2 GND QA1 QA0 VCCA FSELA FSELB FSELC GND 37 38 39 40 41 42 43 44 45 46 47 48 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 1 VCC 2 FSELD 3 CCLK 4 CCLK_SEL 5 GND 6 PCLK0 7 PCLK0 8 VCC 9 PCLK_SEL 13 10 11 12 PCLK1 PCLK1 GND VCCD QD0 QD1 QD2 GND QD3 QD4 VCCD CLK_STOP OE0 OE1 GND MPC9443 Figure 2. 48–Lead Package Pinout (Top View) MOTOROLA For More Informa2 ion On This Product, t Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9443 Table 1: Pin Configuration Pin CCLK PCLK0, PCLK0 PCLK1, PCLK1 FSELA, FSELB, FSELC, FSELD CCLK_SEL PCLK_SEL OE0, OE1 CLK_STOP GND VCCA, VCCB, VCCC, VCCD VCC QA0 to QA4 QB0 to QB2 QC0 to QC2 QD0 to QD4 Output Output Output Output Input Input Input Input Input Input Input Input I/O Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Supply Supply Supply LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS clock inputs LVPECL differential clock input LVPECL differential clock input Output bank divide select input LVCMOS/LVPECL clock input select PCLK0/PCLK1 clock input select Output tristate control Synchronous output enable/disable (clock stop) control Negative voltage supply Positive voltage supply output bank (VCC) Positive voltage supply core (VCC) Bank A outputs Bank B outputs Bank C outputs Bank D outputs Function Freescale Semiconductor, Inc... Table 2: Supported Single and Dual Supply Configurations Supply voltage configuration 3.3V supply Mixed mode supply 2.5V supply a. b. c. d. e. VCCa 3.3V 3.3V 2.5V VCCAb 3.3V 3.3V or 2.5V 2.5V VCCBc 3.3V 3.3V or 2.5V 2.5V VCCCd 3.3V 3.3V or 2.5V 2.5V VCCDe 3.3V 3.3V or 2.5V 2.5V GND 0V 0V 0V VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels VCCC is the positive power supply of the bank C outputs. VCCC voltage defines bank C output levels VCCD is the positive power supply of the bank D outputs. VCCD voltage defines bank D output levels Table 3: Function Table (Controls) Control CCLK_SEL PCLK_SEL FSELA FSELB FSELC FSELD CLK_STOP OE0, OE1 Default 0 0 0 0 0 0 0 00 0 PCLK or PCLK1 active (LVPECL clock mode) PCLK0 active, PCLK1 inactive fQA0:4 = fREF fQB0:2 = fREF fQC0:2 = fREF fQD0:4 = fREF Normal operation 1 CCLK active (LVCMOS clock mode) PCLK1 active, PCLK0 inactive fQA0:4 = fREF ÷ 2 fQB0:2 = fREF ÷ 2 fQC0:2 = fREF ÷ 2 fQD0:4 = fREF ÷ 2 Outputs are synchronously disabled (stopped) in logic low state Asynchronous output enable control. See Table 4. OEN TIMING SOLUTIONS For More Informa3 ion On This Product, t Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MPC9443 Table 4: Output High–Impedance Control (OEN)a OE0 0 0 1 1 a. 0 1 0 1 OE1 QA0 to QA4 Enabled Enabled Enabled Disabled (tristate) QB0 to QB2 Enabled Disabled (tristate) Enabled Disabled (tristate) QC0 to QC2 Enabled Disabled (tristate) Disabled (tristate) Disabled (tristate) QD0 to QD4 Enabled Enabled Disabled (tristate) Disabled (tristate) Total number of enabled outputs 16 10 8 0 OEN will tristate (high impedance) output banks independent on the logic state of the output and the status of CLK_STOP. Table 5: Absolute Maximum Ratingsa Symbol VCC Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC+0.3 VCC+0.3 ±20 ±50 125 Unit V V V mA mA °C Condition Freescale Semiconductor, Inc... VIN VOUT IIN IOUT TS a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Table 6: General Specifications Symbol VTT MM HBM LU CPD CIN Characteristics Output termination voltage ESD protection (Machine model) ESD protection (Human body model) Latch-up immunity Power dissipation capacitance Input capacitance 200 2000 200 10 4.0 Min Typ VCC ÷ 2 Max Unit V V V mA pF pF Per output Condition MOTOROLA For More Informa4 ion On This Product, t Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9443 Table 7: DC Characteristics (VCC = VCCA = VCCB = VCCC = VCCD = 3.3V Symbol VIH VIL VPP VCMRa IIN VOH VOL ZOUT ICCQd a. Characteristics Input High Voltage Input Low Voltage Peak-to-peak Input Voltage Common Mode Range Input Currentb Output High Voltage Output Low Voltage Output Impedance 19 PCLK0, 1 PCLK0, 1 Min 2.0 -0.3 250 1.1 2.4 0.55 0.30 VCC-0.6 200 Typ ± 5%, TA = –40 to +85°C) Max VCC + 0.3 0.8 Unit V V mV V µA V V V Condition LVCMOS LVCMOS LVPECL LVPECL VIN=GND or VIN=VCC IOH=-24 mAc IOL= 24mAc IOL= 12mA W Freescale Semiconductor, Inc... b. c. d. Maximum Quiescent Supply Current 2.0 mA All VCC Pins VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. Input pull-up / pull-down resistors influence input current. The MPC9443 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines (for VCC=3.3V) or one 50Ω series terminated transmission line (for VCC=2.5V). ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 8: AC Characteristics (VCC = VCCA = VCCB = VCCC = VCCD = 3.3V Symbol fref fMAX VPP VCMRb tP, REF tr, tf tPLH tPHL tPLH tPHL tPLZ, HZ tPZL, LZ tS, tH tsk(LH, HL) Input Frequency Maximum Output Frequency Peak-to-peak Input Voltage Common Mode Range Reference Input Pulse Width CCLK Input Rise/Fall Time Propagation Delay PCLK0,1 to any Q PCLK0,1 to any Q CCLK to any Q CCLK to any Q 2.5 2.4 2.1 1.9 ÷1 output ÷2 output PCLK0,1 PCLK0,1 Characteristics Min 0 0 0 500 1.3 1.4 ± 5%, TA = –40 to +85°C)a Max 350 350 175 1000 VCC-0.8 1.0c 5.0 5.2 4.2 4.6 10 10 Unit MHz MHz MHz mV V ns ns ns ns ns ns ns ns ps 125 225 250 2.5 2.1 2.8 2.7 300 400 ps ps ps ns ns ns ns ps ps % % DCREF = 50% 0.8 to 2.0V FSELx=0 FSELx=1 LVPECL LVPECL Condition Typ Output Disable Time Output Enable Time Setup, hold time (reference clock to CLK_STOP) Output-to-output Skewd Within one bank Any output, same output divider Any output, any output divider Device-to-device Skew (LH)e Using PCLK0,1 Using CCLK Device-to-device Skew (LH, HL)f Using PCLK0,1 Using CCLK Output pulse skewg Using PCLK0,1 Using CCLK Output Duty Cycle fQ