SN54LS160A

BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS The LS160A / 161A / 162A / 163A are high-speed 4-bit synchronous counters. They are edge-triggered, synchronously presettable, and cascadable MSI building blocks for counting, memory addressing, frequency division and other applications. The LS160A and LS162A count modulo 10 (BCD). The LS161A and LS163A count modulo 16 (binary.) The LS160A and LS161A have an asynchronous Master Reset (Clear) input that overrides, and is independent of, the clock and all other control inputs. The LS162A and LS163A have a Synchronous Reset (Clear) input that overrides all other control inputs, but is active only during the rising clock edge. BCD (Modulo 10) Asynchronous Reset Synchronous Reset LS160A LS162A Binary (Modulo 16) LS161A LS163A SN54/74LS160A SN54/74LS161A SN54/74LS162A SN54/74LS163A BCD DECADE COUNTERS / 4-BIT BINARY COUNTERS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 • • • • • • Synchronous Counting and Loading Two Count Enable Inputs for High Speed Synchronous Expansion Terminal Count Fully Decoded Edge-Triggered Operation Typical Count Rate of 35 MHz ESD > 3500 Volts CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 TC 15 Q0 14 Q1 13 Q2 12 Q3 11 CET 10 PE 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. *MR for LS160A and LS161A *SR for LS162A and LS163A 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC 1 *R 2 CP 3 P0 4 P1 5 P2 6 P3 8 7 CEP GND PIN NAMES PE P0 – P3 CEP CET CP MR SR Q0 – Q3 TC Parallel Enable (Active LOW) Input Parallel Inputs Count Enable Parallel Input Count Enable Trickle Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Synchronous Reset (Active LOW) Input Parallel Outputs (Note b) Terminal Count Output (Note b) LOADING (Note a) HIGH 1.0 U.L. 0.5 U.L. 0.5 U.L. 1.0 U.L. 0.5 U.L. 0.5 U.L. 1.0 U.L. 10 U.L. 10 U.L. LOW 0.5 U.L. 0.25 U.L. 0.25 U.L. 0.5 U.L. 0.25 U.L. 0.25 U.L. 0.5 U.L. 5 (2.5) U.L. 5 (2.5) U.L. LOGIC SYMBOL 9 3 4 5 6 7 10 2 PE P0 P1 P2 P3 CEP CET CP TC 15 *R Q0 Q1 Q2 Q3 NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. 1 14 13 12 11 VCC = PIN 16 GND = PIN 8 *MR for LS160A and LS161A *SR for LS162A and LS163A FAST AND LS TTL DATA 5-1 SN54/74LS160A • SN54/74LS161A SN54/74LS162A • SN54/74LS163A STATE DIAGRAM LS160A • LS162A 0 1 2 3 4 0 LS161A • LS163A LOGIC EQUATIONS 1 2 3 4 15 5 15 5 14 6 14 6 Count Enable = CEP • CET • PE TC for LS160A & LS162A = CET • Q0 • Q1 • Q2 • Q3 TC for LS161A & LS163A = CET • Q0 • Q1 • Q2 • Q3 Preset = PE • CP + (rising clock edge) Reset = MR (LS160A & LS161A) Reset = SR • CP + (rising clock edge) Reset = (LS162A & LS163A) 13 7 13 7 12 11 10 9 8 12 11 10 9 8 NOTE: The LS160A and LS162A can be preset to any state, but will not count beyond 9. If preset to state 10, 11, 12, 13, 14, or 15, it will return to its normal sequence within two clock pulses. FUNCTIONAL DESCRIPTION The LS160A / 161A / 162A / 163A are 4-bit synchronous counters with a synchronous Parallel Enable (Load) feature. The counters consist of four edge-triggered D flip-flops with the appropriate data routing networks feeding the D inputs. All changes of the Q outputs (except due to the asynchronous Master Reset in the LS160A and LS161A) occur as a result of, and synchronous with, the LOW to HIGH transition of the Clock input (CP). As long as the set-up time requirements are met, there are no special timing or activity constraints on any of the mode control or data inputs. Three control inputs — Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) — select the mode of operation as shown in the tables below. The Count Mode is enabled when the CEP, CET, and PE inputs are HIGH. When the PE is LOW, the counters will synchronously load the data from the parallel inputs into the flip-flops on the LOW to HIGH transition of the clock. Either the CEP or CET can be used to inhibit the count sequence. With the PE held HIGH, a LOW on either the CEP or CET inputs at least one set-up time prior to the LOW to HIGH clock transition will cause the existing output states to be retained. The AND feature of the two Count Enable inputs (CET • CEP) allows synchronous cascading without external gating and without delay accumulation over any practical number of bits or digits. The Terminal Count (TC) output is HIGH when the Count Enable Trickle (CET) input is HIGH while the counter is in its maximum count state (HLLH for the BCD counters, HHHH for the Binary counters). Note that TC is fully decoded and will, therefore, be HIGH only for one count state. The LS160A and LS162A count modulo 10 following a binary coded decimal (BCD) sequence. They generate a TC output when the CET input is HIGH while the counter is in state 9 (HLLH). From this state they increment to state 0 (LLLL). If loaded with a code in excess of 9 they return to their legitimate sequence within two counts, as explained in the state diagram. States 10 through 15 do not generate a TC output. The LS161A and LS163A count modulo 16 following a binary sequence. They generate a TC when the CET input is HIGH while the counter is in state 15 (HHHH). From this state they increment to state 0 (LLLL). The Master Reset (MR) of the LS160A and LS161A is asynchronous. When the MR is LOW, it overrides all other input conditions and sets the outputs LOW. The MR pin should never be left open. If not used, the MR pin should be tied through a resistor to VCC, or to a gate output which is permanently set to a HIGH logic level. The active LOW Synchronous Reset (SR) input of the LS162A and LS163A acts as an edge-triggered control input, overriding CET, CEP and PE, and resetting the four counter flip-flops on the LOW to HIGH transition of the clock. This simplifies the design from race-free logic controlled reset circuits, e.g., to reset the counter synchronously after reaching a predetermined value. MODE SELECT TABLE *SR L H H H H PE X L H H H CET X X H L X CEP X X H X L Action on the Rising Clock Edge ( RESET (Clear) LOAD (Pn → Qn) COUNT (Increment) NO CHANGE (Hold) NO CHANGE (Hold) ) *For the LS162A and *LS163A only. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care FAST AND LS TTL DATA 5-2 SN54/74LS160A • SN54/74LS161A SN54/74LS162A • SN54/74LS163A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 0.4 4.0 8.0 Unit V °C mA mA LS160A and LS161A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage Input LOW Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output HIGH Voltage 54 74 54, 74 VOL Output LOW Voltage Output LOW Voltage 74 Input HIGH Current MR, Data, CEP, Clock PE, CET MR, Data, CEP, Clock PE, CET IIL IOS ICC Input LOW Current MR, Data, CEP, Clock PE, CET Short Circuit Current (Note 1) Power Supply Current Total, Output HIGH Total, Output LOW – 20 0.35 0.5 20 40 0.1 0.2 – 0.4 – 0.8 – 100 31 32 V µA mA 2.5 2.7 54 74 – 0.65 3.5 3.5 0.25 0.4 Min 2.0 0.7 0.8 – 1.5 V V V V Typ Max Unit Ui V V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH , , or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V IIH mA mA mA VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-3 SN54/74LS160A • SN54/74LS161A SN54/74LS162A • SN54/74LS163A LS162A and LS163A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage Input LOW Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output HIGH Voltage 54 74 54, 74 VOL Output LOW Voltage Output LOW Voltage 74 Input HIGH Current Data, CEP, Clock PE, CET, SR Data, CEP, Clock PE, CET, SR IIL IOS ICC Input LOW Current Data, CEP, Clock, PE, SR CET Short Circuit Current (Note 1) Power Supply Current Total, Output HIGH Total, Output LOW – 20 0.35 0.5 20 40 0.1 0.2 – 0.4 – 0.8 – 100 31 32 V µA mA 2.5 2.7 54 74 – 0.65 3.5 3.5 0.25 0.4 Min 2.0 0.7 0.8 – 1.5 V V V V Typ Max Unit Ui V V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = – 18 mA , , VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V IIH mA mA mA VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Limits Symbol S bl fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter P Maximum Clock Frequency Propagation Delay Clock to TC Propagation Delay Clock to Q Propagation Delay CET to TC MR or SR to Q Min 25 Typ 32 20 18 13 18 9.0 9.0 20 35 35 24 27 14 14 28 Max Unit Ui MHz ns ns ns ns VCC = 5.0 V 50 CL = 15 pF Test C di i T Conditions FAST AND LS TTL DATA 5-4 SN54/74LS160A • SN54/74LS161A SN54/74LS162A • SN54/74LS163A AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol S bl tWCP tW ts ts th th trec *CEP, CET or DATA Parameter P Clock Pulse Width Low MR or SR Pulse Width Setup Time, other* Setup Time PE or SR Hold Time, data Hold Time, other Recovery Time MR to CP Min 25 20 20 25 3 0 15 Typ Max Unit Ui ns ns ns ns ns ns ns Test C di i T Conditions VCC = 5.0 V 50 DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs. AC WAVEFORMS tW(H) CP 1.3 V tPHL Q 1.3 V tW(L) 1.3 V tPLH 1.3 V OTHER CONDITIONS: PE = MR (SR) = H CEP = CET = H MR 1.3 V tW trec 1.3 V OTHER CONDITIONS: PE = L P0 = P1 = P2 = P3 = H CP Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 tPHL 1.3 V Figure 1. Clock to Output Delays, Count Frequency, and Clock Pulse Width Figure 2. Master Reset to Output Delay, Master Reset Pulse Width, and Master Reset Recovery Time FAST AND LS TTL DATA 5-5 SN54/74LS160A • SN54/74LS161A SN54/74LS162A • SN54/74LS163A AC WAVEFORMS (continued) COUNT ENABLE TRICKLE INPUT TO TERMINAL COUNT OUTPUT DELAYS The positive TC pulse occurs when the outputs are in the (Q0 • Q1 • Q2 • Q3) state for the LS160 and LS162 and the (Q0 • Q1 • Q2 • Q3) state for the LS161 and LS163. CET 1.3 V tPLH 1.3 V tPHL 1.3 V TC 1.3 V Figure 3 OTHER CONDITIONS: CP = PE = CEP = MR = H CLOCK TO TERMINAL COUNT DELAYS CP The positive TC pulse is coincident with the output state (Q0 • Q1 • Q2 • Q3) state for the LS161 and LS163 and (Q0 • Q1 • Q2 • Q3) for the LS161 and LS163. 1.3 V tPLH 1.3 V 1.3 V tPHL 1.3 V TC 1.3 V Figure 4 OTHER CONDITIONS: PE = CEP = CET = MR = H CP 1.3 V th(H) = 0 1.3 V ts(L) 1.3 V 1.3 V th(L) = 0 1.3 V SETUP TIME (ts) AND HOLD TIME (th) FOR PARALLEL DATA INPUTS The shaded areas indicate when the input is permitted to change for predictable output performance. P0 • P1 • P2 • P3 ts(H) Q0 • Q1 • Q2 • Q3 Figure 5 OTHER CONDITIONS: PE = L, MR = H SETUP TIME (ts) AND HOLD TIME (th) FOR COUNT ENABLE (CEP) AND (CET) AND PARALLEL ENABLE (PE) INPUTS The shaded areas indicate when the input is permitted to change for predictable output performance. 1.3 V th (L) = 0 1.3 V PARALLEL LOAD (See Fig. 5) Q RESPONSE TO PE RESET Q RESPONSE TO SR COUNT OR LOAD Q OTHER CONDITIONS: PE = H, MR = H ts(H) 1.3 V CP th(H) = 0 1.3 V COUNT MODE (See Fig. 7) CEP ts(H) CET 1.3 V ts(H) CP ts(L) SR or PE 1.3 V th(H) = 0 1.3 V th(H) = 0 1.3 V COUNT ts(L) 1.3 V th(L) = 0 1.3 V ts(L) 1.3 V HOLD 1.3 V th(L) = 0 1.3 V HOLD Figure 6 Figure 7 FAST AND LS TTL DATA 5-6