SN54LS374J

OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 / 74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The SN54 / 74LS374 is a high-speed, low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN54 / 74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all Motorola TTL families. SN54/74LS373 SN54/74LS374 OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT LOW POWER SCHOTTKY 20 1 J SUFFIX CERAMIC CASE 732-03 • • • • • • • Eight Latches in a Single Package 3-State Outputs for Bus Interfacing Hysteresis on Latch Enable Edge-Triggered D-Type Inputs Buffered Positive Edge-Triggered Clock Hysteresis on Clock Input to Improve Noise Margin Input Clamp Diodes Limit High Speed Termination Effects LOADING (Note a) 20 1 N SUFFIX PLASTIC CASE 738-03 PIN NAMES 20 HIGH D0 – D7 LE CP OE O0 – O7 Data Inputs Latch Enable (Active HIGH) Input Clock (Active HIGH going edge) Input Output Enable (Active LOW) Input Outputs (Note b) 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 (25) U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 (7.5) U.L. DW SUFFIX SOIC CASE 751D-03 1 ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC NOTES: a) 1 TTL Units Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 7.5 U.L. for Military (54) and 25 U.L. for Commercial (74) Temperature Ranges. The Output HIGH drive factor is 25 U.L. for Military (54) and 65 U.L. for Commercial (74) Temperature Ranges. CONNECTION DIAGRAM DIP (TOP VIEW) SN54 / 74LS373 VCC 20 O7 19 D7 18 D6 17 O6 16 O5 15 D5 14 D4 13 O4 12 LE 11 VCC 20 O7 19 D7 18 SN54 / 74LS374 D6 17 O6 16 O5 15 D5 14 D4 13 O4 12 CP 11 1 OE 2 O0 3 D0 4 D1 5 O1 6 O2 7 D2 8 D3 9 O3 10 GND NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 OE 2 O0 3 D0 4 D1 5 O1 6 O2 7 D2 8 D3 9 O3 10 GND FAST AND LS TTL DATA 5-521 SN54/74LS373 • SN54/74LS374 TRUTH TABLE LS373 Dn H L X X LE H H L X OE L L L H On H L Q0 Z* Dn H L X X LS374 LE OE L L H On H L Z* H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance * Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE). LOGIC DIAGRAMS SN54LS / 74LS373 3 4 7 8 13 14 17 18 D0 D LATCH ENABLE LE 11 OE Q G D1 D Q G D2 D Q G D3 D Q G D4 D Q G D5 D Q G D6 D Q G D7 D Q G VCC = PIN 20 GND = PIN 10 = PIN NUMBERS 1 O0 2 5 O1 6 O2 9 O3 12 O4 15 O5 16 O6 19 O7 SN54LS / 74LS374 3 11 4 7 8 13 14 17 18 D0 CP D QQ CP D QQ D1 CP D QQ D2 CP D QQ D3 CP D QQ D4 CP D QQ D5 CP D QQ D6 CP D QQ D7 CP OE 1 2 O0 5 O1 6 O2 9 O3 12 O4 15 O5 16 O6 19 O7 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 1.0 – 2.6 12 24 Unit V °C mA mA FAST AND LS TTL DATA 5-522 SN54/74LS373 • SN54/74LS374 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54 74 54, 74 VOL IOZH IOZL IIH IIL IOS ICC Output LOW Voltage 74 Output Off Current HIGH Output Off Current LOW Input HIGH Current Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 30 0.35 0.5 20 – 20 20 0.1 – 0.4 – 130 40 V µA µA µA mA mA mA mA 2.4 2.4 54 74 – 0.65 3.4 3.1 0.25 0.4 Min 2.0 0.7 0.8 – 1.5 Typ Max Unit V V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 12 mA IOL = 24 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VOUT = 2.7 V VCC = MAX, VOUT = 0.4 V VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits LS373 Symbol fMAX tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay, Data to Output Clock or Enable to Output Output Enable Time Output Disable Time 12 12 20 18 15 25 12 15 18 18 30 30 28 36 20 25 15 19 20 21 12 15 28 28 28 28 20 25 Min Typ Max Min 35 LS374 Typ 50 Max Unit MHz ns ns ns ns CL = 5.0 pF CL = 45 pF, RL = 667 Ω Test Conditions AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits LS373 Symbol tW ts th Clock Pulse Width Setup Time Hold Time Parameter Min 15 5.0 20 Max Min 15 20 0 LS374 Max Unit ns ns ns DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to LE transition from HIGH-to-LOW in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the LE transition from HIGH-to-LOW that the logic level must be maintained at the input in order to ensure continued recognition. FAST AND LS TTL DATA 5-523 SN54/74LS373 AC WAVEFORMS tW LE 1.3 V tW ts th Dn tPLH OUTPUT tPHL Figure 1 OE tPZL VOUT 1.3 V 1.3 V 1.3 V tPLZ 1.3 V VOL 0.5 V OE tPZH VOUT 1.3 V 1.3 V tPHZ 1.3 V VOH 1.3 V 0.5 V Figure 2 Figure 3 AC LOAD CIRCUIT VCC SWITCH POSITIONS RL SYMBOL tPZH tPZL SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed SW1 TO OUTPUT UNDER TEST tPLZ tPHZ 5.0 kΩ CL* SW2 * Includes Jig and Probe Capacitance. Figure 4 FAST AND LS TTL DATA 5-524 SN54/74LS374 AC WAVEFORMS tWH CP 1.3 V ts Dn tPLH OUTPUT 1.3 V 1.3 V tPHL 1.3 V tWL 1.3 V 1.3 V th OE tPZL VOUT 1.3 V 1.3 V 1.3 V tPLZ ≈ 1.3 V VOL 0.5 V Figure 6 Figure 5 OE tPZH VOUT 1.3 V tPHZ 1.3 V 1.3 V ≥ VOH ≈ 1.3 V 0.5 V Figure 7 AC LOAD CIRCUIT VCC SWITCH POSITIONS RL SYMBOL tPZH tPZL SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed SW1 TO OUTPUT UNDER TEST tPLZ tPHZ 5.0 kΩ CL* SW2 * Includes Jig and Probe Capacitance. Figure 8 FAST AND LS TTL DATA 5-525 Case 751D-03 DW Suffix 20-Pin Plastic SO-20 (WIDE) -A20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: MILLIMETER. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. -B1 10 P 0.25 (0.010) M B M 5. 751D 01, AND 02 OBSOLETE, NEW STANDARD 751D 03. 10 PL G R X 45° C K M -T- SEATING PLANE M D 20 PL 0.25 (0.010) T B S F J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 7.40 2.35 0.35 0.50 12.95 7.60 2.65 0.49 0.90 INCHES MIN MAX 0.499 0.292 0.093 0.014 0.020 0.510 0.299 0.104 0.019 0.035 1.27 BSC 0.25 0.10 0 0.32 0.25 7 0.050 BSC 0.010 0.004 0 0.012 0.009 7 ° ° ° ° 10.05 0.25 10.55 0.75 0.395 0.010 0.415 0.029 A S Case 732-03 J Suffix 20-Pin Ceramic Dual In-Line NOTES: 1. LEADS WITHIN 0.25 mm (0.010) DIA., TRUE POSITION AT SEATING PLANE, AT MAXIMUM 20 1 11 2. MATERIAL CONDITION. DIM L TO CENTER OF LEADS WHEN FORMED PARALLEL. 10 3. DIM A AND B INCLUDES MENISCUS. B A F C L N H D SEATING PLANE J M G K DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 23.88 6.60 3.81 0.38 1.40 25.15 7.49 5.08 0.56 1.65 INCHES MIN MAX 0.940 0.260 0.150 0.015 0.055 0.990 0.295 0.200 0.022 0.065 2.54 BSC 0.51 0.20 3.18 1.27 0.30 4.06 0.100 BSC 0.020 0.008 0.125 0.050 0.012 0.160 7.62 BSC 0 ° 15 ° 0.300 BSC 0 ° 15 ° 0.25 1.02 0.010 0.040 Case 738-03 N Suffix 20-Pin Plastic -A20 1 11 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: INCH. DIMENSION L" TO CENTER OF LEAD WHEN FORMED PARALLEL. B C L 4. DIMENSION B" DOES NOT INCLUDE MOLD FLASH. 5. 738 02 OBSOLETE, NEW STANDARD 738 03. -TSEATING PLANE K E G F D 20 PL 0.25 (0.010) M N M J 20 PL 0.25 (0.010) T A M M T B M DIM A B C D E F G J K L M N MILLIMETERS MIN MAX 25.66 6.10 3.81 0.39 27.17 6.60 4.57 0.55 INCHES MIN MAX 1.010 0.240 0.150 0.015 1.070 0.260 0.180 0.022 1.27 BSC 1.27 1.77 0.050 BSC 0.050 0.070 2.54 BSC 0.21 2.80 0.38 3.55 0.100 BSC 0.008 0.110 0.015 0.140 7.62 BSC 0 ° 15 ° 0.300 BSC 0 ° 15 ° 0.51 1.01 0.020 0.040 FAST AND LS TTL DATA 5-526 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. 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JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. tPZL Closed Open ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. SYMBOL SW1 SW2 tPLZ Closed Closed Closed Closed tPHZ ◊ FAST AND LS TTL DATA 5-527