SN74LS175N

QUAD D FLIP-FLOP The LSTTL / MSI SN54 / 74LS175 is a high speed Quad D Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW. The LS175 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families. SN54/74LS175 QUAD D FLIP-FLOP LOW POWER SCHOTTKY • • • • • • Edge-Triggered D-Type Inputs Buffered-Positive Edge-Triggered Clock Clock to Output Delays of 30 ns Asynchronous Common Reset True and Complement Output Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Q3 15 Q3 14 D3 13 D2 12 Q2 11 Q2 10 CP 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 16 1 J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 1 MR 2 Q0 3 Q0 4 D0 5 D1 6 Q1 7 Q1 8 GND PIN NAMES LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L. 16 1 D SUFFIX SOIC CASE 751B-03 D0 – D3 CP MR Q0 – Q3 Q0 – Q3 Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input True Outputs (Note b) Complemented Outputs (Note b) 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC NOTES: a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. LOGIC SYMBOL 4 5 12 13 LOGIC DIAGRAM MR CP D3 1 9 13 D2 12 D1 5 D0 4 9 CP D0 D1 D2 D3 DQ CP Q CD 14 15 DQ CP Q CD 11 10 DQ CP Q CD 6 7 DQ CP Q CD 3 2 1 MR Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 3 2 6 7 11 10 14 15 VCC = PIN 16 Q3 Q3 GND = PIN 8 = PIN NUMBERS Q2 Q2 Q1Q1 Q0 Q0 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-327 SN54/74LS175 FUNCTIONAL DESCRIPTION The LS175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW to HIGH Clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The LS175 is useful for general logic applications where a common Master Reset and Clock are acceptable. TRUTH TABLE Inputs (t = n, MR = H) D L H Outputs (t = n+1) Note 1 Q L H Q H L Note 1: t = n + 1 indicates conditions after next clock. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 0.4 4.0 8.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.4 – 100 18 0.35 0.5 20 IIH IIL IOS ICC V µA mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 – 0.65 3.5 0.8 – 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-328 SN54/74LS175 AC CHARACTERISTICS (TA = 25°C) Limits Symbol fMAX tPLH tPHL tPLH tPHL Parameter Maximum Input Clock Frequency Propagation Delay, MR to Output Propagation Delay, Clock to Output Min 30 Typ 40 20 20 13 16 30 30 25 25 Max Unit MHz ns ns VCC = 5.0 V CL = 15 pF Test Conditions AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol tW ts th trec Parameter Clock or MR Pulse Width Data Setup Time Data Hold Time Recovery Time Min 20 20 5.0 25 Typ Max Unit ns ns ns ns VCC = 5.0 V Test Conditions AC WAVEFORMS 1/fmax tw CP 1.3 V ts(H) ts(L) th(H) 1.3 V 1.3 V tPLH Q 1.3 V tPHL Q 1.3 V 1.3 V MR 1.3 V tW 1.3 V trec 1.3 V CP Q tPHL 1.3 V tPLH Q 1.3 V 1.3 V 1.3 V th(L) 1.3 V tPHL 1.3 V tPLH 1.3 V D * *The shaded areas indicate when the input is permitted to *change for predictable output performance. Figure 1. Clock to Output Delays, Clock Pulse Width, Frequency, Setup and Hold Times Data to Clock Figure 2. Master Reset to Output Delay, Master Reset Pulse Width, and Master Reset Recovery Time DEFINITIONS OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs. FAST AND LS TTL DATA 5-329 -A- Case 751B-03 D Suffix 16-Pin Plastic SO-16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: MILLIMETER. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. 751B 01 IS OBSOLETE, NEW STANDARD 751B 03. 16 9 -B1 8 P 8 PL 0.25 (0.010) M B M R X 45° G -TD 16 PL 0.25 (0.010) M C SEATING PLANE K T B S M F J A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 3.80 1.35 0.35 0.40 10.00 4.00 1.75 0.49 1.25 INCHES MIN MAX 0.386 0.150 0.054 0.014 0.016 0.393 0.157 0.068 0.019 0.049 1.27 BSC 0.19 0.10 0 0.25 0.25 7 0.050 BSC 0.008 0.004 0 0.009 0.009 7 ° ° ° ° 5.80 0.25 6.20 0.50 0.229 0.010 0.244 0.019 Case 648-08 N Suffix 16-Pin Plastic -A16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: INCH. DIMENSION L" TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B" DOES NOT INCLUDE MOLD FLASH. 5. 6. ROUNDED CORNERS OPTIONAL. 648 01 THRU 07 OBSOLETE, NEW STANDARD 648 08. B 1 8 F S C -TK SEATING PLANE L H G D 16 PL 0.25 (0.010) M J M T A M DIM A B C D F G H J K L M S MILLIMETERS MIN MAX 18.80 6.35 3.69 0.39 1.02 19.55 6.85 4.44 0.53 1.77 INCHES MIN MAX 0.740 0.250 0.145 0.015 0.040 0.770 0.270 0.175 0.021 0.070 2.54 BSC 1.27 BSC 0.21 2.80 7.50 0 0.38 3.30 7.74 10 0.100 BSC 0.050 BSC 0.008 0.110 0.295 0 0.015 0.130 0.305 10 ° ° ° ° 0.51 1.01 0.020 0.040 -A16 9 Case 620-09 J Suffix 16-Pin Ceramic Dual In-Line NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. -B1 8 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. C L 5. 620 01 THRU 08 OBSOLETE, NEW STANDARD 620 09. -TSEATING PLANE K E F D 16 PL 0.25 (0.010) M N G T A S M J 16 PL 0.25 (0.010) M T B S DIM A B C D E F G J K L M N MILLIMETERS MIN MAX 19.05 6.10 19.55 7.36 4.19 0.39 0.53 INCHES MIN MAX 0.750 0.240 0.770 0.290 0.165 0.015 0.021 1.27 BSC 1.40 1.77 0.050 BSC 0.055 0.070 2.54 BSC 0.23 0.27 5.08 7.62 BSC 0 0.100 BSC 0.009 0.011 0.200 0.300 BSC 0 ° 15 ° ° 15 ° 0.39 0.88 0.015 0.035 FAST AND LS TTL DATA 5-330 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. 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ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. ◊ FAST AND LS TTL DATA 5-331