SN74LS221D

DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS Each multivibrator of the LS221 features a negative-transition-triggered input and a positive-transition-triggered input either of which can be used as an inhibit input. Pulse triggering occurs at a voltage level and is not related to the transition time of the input pulse. Schmitt-trigger input circuitry for B input allows jitter-free triggering for inputs as slow as 1 volt/ second, providing the circuit with excellent noise immunity. A high immunity to VCC noise is also provided by internal latching circuitry. Once triggered, the outputs are independent of further transitions of the inputs and are a function of the timing components. The output pulses can be terminated by the overriding clear. Input pulse width may be of any duration relative to the output pulse width. Output pulse width may be varied from 35 nanoseconds to a maximum of 70 s by choosing appropriate timing components. With R ext = 2.0 kΩ and C ext = 0, a typical output pulse of 30 nanoseconds is achieved. Output rise and fall times are independent of pulse length. Pulse width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications, pulse stability will only be limited by the accuracy of external timing components. Jitter-free operation is maintained over the full temperature and VCC ranges for greater than six decades of timing capacitance (10 pF to 10 µF), and greater than one decade of timing resistance (2.0 to 70 kΩ for the SN54LS221, and 2.0 to 100 kΩ for the SN74LS221). Pulse width is defined by the relationship: tw(out) = CextRext ln 2.0 ≈ 0.7 Cext Rext; where tW is in ns if Cext is in pF and Rext is in kΩ . If pulse cutoff is not critical, capacitance up to 1000 µF and resistance as low as 1.4 kΩ may be used. The range of jitter-free pulse widths is extended if VCC is 5.0 V and 25°C temperature. SN54/74LS221 DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 • SN54LS221 and SN74LS221 is a Dual Highly Stable One-Shot • Overriding Clear Terminates Output Pulse • Pin Out is Identical to SN54/ 74LS123 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC (TOP VIEW) VCC 16 1 Rext/ 1 Cext Cext 15 14 Q Q CLR 1Q 13 2Q 12 2 CLR 11 2B 10 2A 9 VCC CLR Q Q 4 1Q 5 2Q 6 2 Cext 8 7 2 Rext/ GND Cext Cext Rext + R/C FUNCTION TABLE (EACH MONOSTABLE) INPUTS CLEAR L X X H H *° OUTPUTS B X X L ° H H MAXIMUM OUTPUT PULSE LENGTH 49 s 70 s Q L L L Q H H H A X H X L ± L 1 1A 2 1B 3 1 CLR *See operational notes — Pulse Trigger Modes TYPE SN54LS221 SN74LS221 positive logic: Low input to clear resets Q low and positive logic: Q high regardless of dc levels at A positive logic: or B inputs. TYPICAL POWER DISSIPATION 23 mW 23 mW FAST AND LS TTL DATA 5-380 SN54/74LS221 OPERATIONAL NOTES Once in the pulse trigger mode, the output pulse width is determined by tW = RextCextIn2, as long as Rext and Cext are within their minimum and maximum valves and the duty cycle is less than 50%. This pulse width is essentially independent of VCC and temperature variations. Output pulse widths varies typically no more than ±0.5% from device to device. If the duty cycle, defined as being 100 • tW where T is the T input period of the input pulse, rises above 50%, the output pulse width will become shorter. If the duty cycle varies between low and high valves, this causes the output pulse width to vary in length, or jitter. To reduce jitter to a minimum, Rext should be as large as possible. (Jitter is independent of Cext). With Rext = 100K, jitter is not appreciable until the duty cycle approaches 90%. Although the LS221 is pin-for-pin compatible with the LS123, it should be remembered that they are not functionally identical. The LS123 is retriggerable so that the output is dependent upon the input transitions once it is high. This is not the case for the LS221. Also note that it is recommended to externally ground the LS123 Cext pin. However, this cannot be done on the LS221. The SN54LS/74LS221 is a dual, monolithic, non-retriggerable, high-stability one shot. The output pulse width, tW can be varied over 9 decades of timing by proper selection of the external timing components, Rext and Cext. Pulse triggering occurs at a voltage level and is, therefore, independent of the input slew rate. Although all three inputs have this Schmitt-trigger effect, only the B input should be used for very long transition triggers (≥1.0 µV/s). High immunity to VCC noise (typically 1.5 V) is achieved by internal latching circuitry. However, standard VCC bypassing is strongly recommended. The LS221 has four basic modes of operation. Clear Mode: If the clear input is held low, irregardless of the previous output state and other input states, the Q output is low. Inhibit Mode: If either the A input is high or the B input is low, once the Q output goes low, it cannot be retriggered by other inputs. Pulse Trigger Mode: A transition of the A or B inputs as indicated in the functional truth table will trigger the Q output to go high for a duration determined by the tW equation described above; Q will go low for a corresponding length of time. The Clear input may also be used to trigger an output pulse, but special logic preconditioning on the A or B inputs must be done as follows: Following any output triggering action using the A or B inputs, the A input must be set high OR the B input must be set low to allow Clear to be used as a trigger. Inputs should then be set up per the truth table (without triggering the output) to allow Clear to be used a trigger for the output pulse. If the Clear pin is routinely being used to trigger the output pulse, the A or B inputs must be toggled as described above before and between each Clear trigger event. Once triggered, as long as the output remains high, all input transitions (except overriding Clear) are ignored. Overriding Clear Mode: If the Q output is high, it may be forced low by bringing the clear input low. FAST AND LS TTL DATA 5-381 SN54/74LS221 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 0.4 4.0 8.0 Unit V °C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VT+ VT– VT+ VT– VIH VIL VIK VOH Parameter Positive-Going Threshold Voltage at C Input Negative-Going Threshold Voltage at C Input Positive-Going Threshold Voltage at B Input Negative-Going Threshold Voltage at B Input Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Voltage 54 Output HIGH Voltage 74 54 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Input A Input B Clear Short Circuit Current (Note 1) Power Supply Current Quiescent Triggered – 20 4.7 19 – 0.4 – 0.8 – 0.8 – 100 11 27 0.35 0.5 20 IIH V µA mA 2.7 3.4 0.25 0.4 V V 2.5 3.4 0.8 – 1.5 V V VCC = MIN, IOH = MAX IOL = 4.0 mA IOL = 8.0 mA 54 74 0.7 0.8 2.0 0.7 V 54 74 0.7 0.7 Min Typ 1.0 0.8 0.8 1.0 0.9 0.9 2.0 Max 2.0 Unit V V V V V V V VCC = MIN Guaranteed Input HIGH Voltage for A Input Guaranteed Input LOW Voltage for A Input VCC = MIN, IIN = – 18 mA VCC = MIN VCC = MIN VCC = MIN Test Conditions VCC = MIN VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V IIL mA VCC = MAX, VIN = 0.4 V IOS ICC mA VCC = MAX VCC = MAX mA Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-382 SN54/74LS221 AC CHARACTERISTICS (VCC = 5.0 V, TA = 25°C) Symbol tPLH From (Input) A B A tPHL tPHL tPLH B Clear Clear To (Output) Q Q Q Q Q Q 70 20 tW(out) A or B Q or Q 600 6.0 670 6.9 750 7.5 ms Limits Min Typ 45 35 50 40 35 44 120 47 Max 70 ns 55 80 ns 65 55 65 150 70 ns ns ns CL = 15 pF, See Figure 1 Cext = 80 pF, Rext = 2.0 Ω Cext = 0, Rext = 2.0 kΩ Cext = 100 pF, Rext = 10 kΩ Cext = 1.0 µF, Rext = 10 kΩ Cext = 80 pF, Rext = 2.0 Ω Unit Test Conditions AC SETUP REQUIREMENTS (VCC = 5.0 V, TA = 25°C) Limits Symbol Parameter Rate of Rise or Fall of Input Pulse dv/dt Schmitt, B Logic Input, A Input Pulse Width tW ts Rext Cext Clear-Inactive-State Setup Time 54 External Timing Resistance 74 External Timing Capacitance Output Duty Cycle RT = 2.0 kΩ RT = MAX Rext 50 90 % 1.4 0 100 1000 A or B, tW(in) Clear, tW (clear) 40 40 15 1.4 70 ns kΩ µF ns 1.0 1.0 V/s V/µs Min Typ Max Unit FAST AND LS TTL DATA 5-383 SN54/74LS221 AC WAVEFORMS tW(in) B INPUT 3V 1.3 V 0V 3V CLEAR tPLH Q OUTPUT tPHL Q OUTPUT A INPUT IS LOW. tPLH tPHL 0V VOH VOL VOH VOL ≥60 ns TRIGGER FROM B, THEN CLEAR — CONDITION 1 3V B INPUT 0V 3V 1.3 V CLEAR 0V VOH Q OUTPUT VOL A INPUT IS LOW. ≥ 60 ns TRIGGER FROM B, THEN CLEAR — CONDITION 2 3V B INPUT 0V 3V 0V TRIGGERED Q OUTPUT NOT TRIGGERED A INPUT IS LOW. tW(out) VOH VOL ≥ 50 ns CLEAR ≥0 ts CLEAR OVERRIDING B, THEN TRIGGER FROM B B INPUT 3V 0V 3V 1.3 V 0V VOH VOL ≥ 50 ns CLEAR ≥ 50 ns Q OUTPUT A INPUT IS LOW. TRIGGERING FROM POSITIVE TRANSITION OF CLEAR Figure 1 FAST AND LS TTL DATA 5-384 -A- Case 751B-03 D Suffix 16-Pin Plastic SO-16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: MILLIMETER. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. 751B 01 IS OBSOLETE, NEW STANDARD 751B 03. 16 9 -B1 8 P 8 PL 0.25 (0.010) M B M R X 45° G -TD 16 PL 0.25 (0.010) M C SEATING PLANE K T B S M F J A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 3.80 1.35 0.35 0.40 10.00 4.00 1.75 0.49 1.25 INCHES MIN MAX 0.386 0.150 0.054 0.014 0.016 0.393 0.157 0.068 0.019 0.049 1.27 BSC 0.19 0.10 0 0.25 0.25 7 0.050 BSC 0.008 0.004 0 0.009 0.009 7 ° ° ° ° 5.80 0.25 6.20 0.50 0.229 0.010 0.244 0.019 Case 648-08 N Suffix 16-Pin Plastic -A16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: INCH. DIMENSION L" TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B" DOES NOT INCLUDE MOLD FLASH. 5. 6. ROUNDED CORNERS OPTIONAL. 648 01 THRU 07 OBSOLETE, NEW STANDARD 648 08. B 1 8 F S C -TK SEATING PLANE L H G D 16 PL 0.25 (0.010) M J M T A M DIM A B C D F G H J K L M S MILLIMETERS MIN MAX 18.80 6.35 3.69 0.39 1.02 19.55 6.85 4.44 0.53 1.77 INCHES MIN MAX 0.740 0.250 0.145 0.015 0.040 0.770 0.270 0.175 0.021 0.070 2.54 BSC 1.27 BSC 0.21 2.80 7.50 0 0.38 3.30 7.74 10 0.100 BSC 0.050 BSC 0.008 0.110 0.295 0 0.015 0.130 0.305 10 ° ° ° ° 0.51 1.01 0.020 0.040 -A16 9 Case 620-09 J Suffix 16-Pin Ceramic Dual In-Line NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. -B1 8 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. C L 5. 620 01 THRU 08 OBSOLETE, NEW STANDARD 620 09. -TSEATING PLANE K E F D 16 PL 0.25 (0.010) M N G T A S M J 16 PL 0.25 (0.010) M T B S DIM A B C D E F G J K L M N MILLIMETERS MIN MAX 19.05 6.10 19.55 7.36 4.19 0.39 0.53 INCHES MIN MAX 0.750 0.240 0.770 0.290 0.165 0.015 0.021 1.27 BSC 1.40 1.77 0.050 BSC 0.055 0.070 2.54 BSC 0.23 0.27 5.08 7.62 BSC 0 0.100 BSC 0.009 0.011 0.200 0.300 BSC 0 ° 15 ° ° 15 ° 0.39 0.88 0.015 0.035 FAST AND LS TTL DATA 5-385 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. 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ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. ◊ FAST AND LS TTL DATA 5-386