HF920GSE

HF920 The Future of Analog IC Technology 900V, Fixed-Frequency, Offline Regulator w/ Ultra-Low Standby Power Consumption DESCRIPTION FEATURES The HF920 is a flyback regulator with a monolithic, 900V MOSFET. The HF920 provides excellent power regulation in AC/DC applications that require high reliability, such as smart meters, large appliances, industrial controls, and products powered by poor AC grids. The HF920 requires a minimal number of external components.  The HF920 uses peak-current-mode control to provide excellent transient response and easy loop compensation. When the output power falls below a given level, the regulator enters burst mode. The IC consumption is also specially optimized. As a result, the HF920 achieves very low power consumption during standby conditions. MPS’s proprietary, 900V, monolithic process enables an over-temperature protection (OTP) that is on the same silicon as the 900V power MOSFET, offering the most precise thermal protection. The HF920 also offers a full suite of protection features such as VCC under-voltage lockout (UVLO), overload protection (OLP), over-voltage protection (OVP), and short-circuit protection (SCP). The HF920 is designed to minimize electromagnetic interference for power line communications (PLC) in home and building automation applications. The operating frequency is programmed externally with a single resistor, so the power supply’s radiated energy can be designed to block interference to the PLC. In addition to the programmable frequency, the HF920 employs frequency jittering that reduces the noise level and EMI filter cost greatly. Frequency-doubling mode operation can be enabled through a simple external set-up. With this special operation mode, the switching frequency is doubled when the converter runs into an over-power condition. In this way, the converter is able to handle up to a 50% decrease of the transformer inductance caused by external magnetizing interference. HF920 Rev. 1.02 12/3/2018                 Monolithic 900V/15Ω MOSFET and HighVoltage Current Source Fixed Switching Frequency, Programmable up to 150kHz Current-Mode Control Scheme Frequency Jittering Low Standby Power Consumption via Active Burst Mode 185VAC), cut the capacitor values in half. Very low DC input voltages can cause thermal problems under heavy-load conditions. It is recommended that the minimum DC voltage is higher than 70V. Estimate the minimum DC voltage with the following procedure. First, estimate the input power (Pin) with Equation (2): Pin  VO  IO  (2) Where VO is the output voltage, IO is the rated output current, and η is the estimated efficiency. Generally, η is between 0.75 and 0.85 depending on the input range and output application. Then, the linear part of the DC input voltage (VDC) can be expressed with Equation (3): VDC (t)  VAC(peak )2  2  Pin t Cin (3) HF920 Rev. 1.02 12/3/2018 The same type of capacitors should be chosen for C1 and C2 to balance their voltages. Each capacitor endures half of the bus voltage, but due to the capacitance distribution (typically ± 20% for electrolytic capacitors), their voltage varies in mass production. In this case, R1 to R4 should be used as the voltage balancing resistors. To balance the voltage on C1 and C2, R1 to R4 should have the same value. R1 to R4 should be a 1206 package size to meet the voltage rating requirement. The R1 to R4 values should also be large enough for energy savings. For example, the total value of R1 to R4 is 20MΩ, which consumes about 18mW at a 600VDC bus voltage. Voltage Stress on the Primary MOSFET At t1, the DC bus voltage reaches its minimum value, and the AC input starts charging the input capacitor. t1 can be calculated with Equation (4): VDC(t1) = VAC(t1) Figure 6: Input Stacked Capacitor Circuit Typically, the maximum voltage stress on the primary MOSFET is design to be less than 90% of its breakdown voltage for reliable operation. (4) www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.HF920 17 HF920 – 900V, FIXED-FREQUENCY, OFFLINE SWITCHING REGULATOR The maximum voltage stress occurs when the primary MOSFET turns off and can be calculated with Equation (5): VDS(max)  VBUS(max)  N(VO  VF )  Vspike (5) Where VF is the rectifier diode’s forward voltage, VO is the output voltage, N is the primary-tosecondary turns ratio, and Vspike is the voltage spike caused by the transformer’s primary leakage inductance. According to Equation (5), voltage stress can be reduced either by choosing a small N or Vspike. However, a small N leads to larger secondary stress, which means there is a trade-off to make. A small Vspike requires a strong snubber to suppress the voltage spike. The input circuit should be designed to guarantee a proper VBUS(max) (i.e.: using suppression components to protect it from surge). Primary-Side Inductor Design (Lm) Typically, the converter is designed to operate in continuous conduction mode (CCM) under a low input voltage for universal input applications. With a built-in slope compensation function, the HF920 supports stable CCM control when the duty cycle exceeds 50%. Set the ratio (KP) of the primary inductor ripple current amplitude vs. the peak current value to 0 < KP ≤ 1, where a smaller KP means a deeper CCM, and KP = 1 stands for boundary conduction mode (BCM) and discontinuous conduction mode (DCM). Figure 7 shows the relevant waveforms. A larger primary inductance leads to a smaller KP, which reduces the RMS current but increases the transformer size. For most HF920 applications, an optimal KP value is between 0.8 and 1, considering the wide input range. For CCM at a minimum input, the converter duty cycle can be determined with Equation (6): D (VO  VF )  N (VO  VF )  N  VDC(min) (6) Where VF is the secondary diode’s forward voltage, and N is the transformer turns ratio. The MOSFET turn-on time can be calculated with Equation (7): TON  D fS (7) Where fS is the operating frequency. The input average current, ripple current, peak current, and valley current of the primary side are calculated using Equation (8), Equation (9), Equation (10), and Equation (11): IAV  Pin VDC(min) Iripple  K P  Ipeak Ipeak  IAV KP (1  )D 2 Ivalley  (1  K P )  Ipeak (8) (9) (10) (11) Estimate Lm using Equation (12): Lm  VDC(min)  TON Iripple (12) Current-Sense Resistor Figure 8 shows the peak current control waveform with slope compensation. Figure 8: Peak Current Control Waveform with Slop Compensation Figure 7: Typical Primary Current Waveform HF920 Rev. 1.02 12/3/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.HF920 18 HF920 – 900V, FIXED-FREQUENCY, OFFLINE SWITCHING REGULATOR When the sum of the sense resistor voltage and the slope compensation voltage reaches the peak current limit (VCS), the HF920 turns off the internal MOSFET. VCS equals the maximum current-set point (VCSL) under full load. Considering the margin, use 0.95 x VCSL for designs. The voltage on the sense resistor can be calculated using Equation (13): Vsense  0.95  VCSL  SRamp  TON (13) Where SRAMP is the slope compensation ramp in proportion to fS. Typically, SRAMP = 21mV/μs when RFSET = 200kΩ. The value of the sense resistor is calculated using Equation (14): R sense  Vsense Ipeak (14) The current-sense resistor should be chosen with an appropriate power rating. Its power loss can be calculated with Equation (15):  Ipeak  Ivalley 2 1 2 (15) Psense      Ipeak  Ivalley    D  Rsense 2 12     Input Over-Voltage Protection on PRO A typical input OVP circuitry of the HF920 is shown in Figure 9. The input OVP point can be calculated with Equation (16): VINOVP R5  R6  R7  R8  VPRO  R8 (16) For resistors R5 to R7, 1206 packages should be used to meet the voltage rating requirement. The total value should be larger than 10MΩ for energy-saving purposes. Switching noise may couple to these large resistors and disturb the PRO protection. It is recommended to connect a bypass ceramic capacitor to PRO. Place this capacitor as close to the IC as possible. Thermal Performance Optimization The HF920 is dedicated to high input voltage applications. However, the high input voltage can cause a greater switching loss on the MOSFET, which can lead to poor thermal performance. Measures should be taken to reduce the switching loss when designing these applications. First, try to use a lower switching frequency if possible. Then use a small transformer turns ratio to minimize the reflected voltage on the primary winding. Thus, VDS is reduced. Finally, reduce the turn-on loss, since the turn-on loss composes a large part of the switching loss. Turn-on loss is the product of the turn-on current spike and VDS. Reducing the turn-on loss can be achieved by reducing VDS or the turn-on current spike. Reducing VDS by using a small turns ratio is discussed above. Another way of reducing VDS when the MOSFET turns on is to set the HF920 to work under deep DCM. In deep DCM, the VDS oscillation is fully damped, so there is no chance of turning on at the high peak value. The turn-on current spike is caused by a parasitic capacitor and output diode reverse recovery. DCM operation helps prevent the output diode’s reverse recovery. The transformer structure should be designed to achieve minimum parasitic capacitance of each winding and between the primary and secondary windings. Figure 9: Input Over-Voltage Protection Set-Up HF920 Rev. 1.02 12/3/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.HF920 19 HF920 – 900V, FIXED-FREQUENCY, OFFLINE SWITCHING REGULATOR PCB Layout Guidelines Efficient PCB layout is critical for achieving reliable operation, good EMI performance, and good thermal performance. For best results, refer to Figure 10 and follow the guidelines below. 1. Minimize the power stage switching stage loop area. This includes the input loop (C8– C6-T1–U2–R21/R22–C8), the auxiliary winding loop (T1–D6–R16–C11–T1), the output loop (T1–D6–C9–T1, T1–D1–C1–T1, and T1–D2–C3–T1), and the RCD loop (T1– D5–R5/R7/C4–T1). 2. Ensure that the power loop ground does not pass through the control circuit ground. If a heat sink is used, connect it to the primary GND plane to improve EMI and thermal dissipation. 3. Place the control circuit capacitors (for FB, PRO, and VCC) close to the IC to decouple the switching noise. 4. Enlarge the GND pad near the IC for good thermal dissipation. 5. Keep the EMI filter far away from the switching point. 6. Ensure enough clearance distance to meet the insulation requirement. Bottom Figure 10: Recommended Layout Design Example Table 2 is a design example using the application guidelines for the given specifications. Table 2: Design Example 85 to 420VAC VIN 13.5V VOUT1 0.3A IOUT1 8V VOUT2 0.05A IOUT2 8V VOUT3 0.05A IOUT3 50kHz fS The detailed application schematic is shown in Figure 11. The typical performance and circuit waveforms are shown in the Typical Performance Characteristics section. For more device applications, please refer to the related evaluation board datasheets. Top HF920 Rev. 1.02 12/3/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.HF920 20 HF920 – 900V, FIXED-FREQUENCY, OFFLINE SWITCHING REGULATOR TYPICAL APPLICATION CIRCUIT EE16 Lm=2.5mH N1:N2:N3:N4:N5:N6=22:170:26:16:16:26 D1 NC VOUT3 N1 L FR1 C2 10 C1 47uF/25V ES1D/200V/1A L 1 10/1W D3 R3 CX1 NC 1N4007 LX1 R5 R6 5.1M/1206 R7 200k/1206 NC VOUT2 2 C8 22uF/400V 24mH D7 1N4007 5 4 330pF/200V/0805 D6 MBRS3200/200V/3A N6 6 D8 1N4007 PRO R16 5.1/1206 R20 13.5V/0.35A GND1(L) R13 2k/1% 1nF/250V R14 97.6k/1% U1 C12 U2 1 2 3 PRO R15 200K VOUT1 C10 0.1uF/50V CY1 BAV21W/200V/0.2A 93.1k/1% C16 1nF/16V C9 470uF/35V D9 R12 5.1M/1206 N 8V/50mA C7 51/1206 N3 R4 6.8k/1% L R11 NC D5 S1ML/1kV/1A R10 5.1M/1206 1uF/25V GND2 R9 3 CX2 8V/50mA C5 C3 47uF/25V ES1D/200V/1A N4 7 1nF/630V/1206 NC 0.22uF/275V R1 6.8k/1% GND3 8 C4 R8 D2 1uF/25V N2 1N4007 C6 22uF/400V 0.22uF/275V 85VAC to 420VAC R2 5.1M/1206 D4 N5 9 C15 1nF/16V 4 VCC D 8 0.1uF/50V C11 22uF/50V R17 10k/1% FSET PRO FB S GND HF920GSE EL817B 6 C14 2.2nF/16V 5 R22 5.1/1%/1206 R21 3.3/1%/1206 R19 300k/1% C13 22nF/50V U3 TLV431AFTA/1.24V R18 9.76k/1% Figure 11: Typical Application Schematic 1T NC N5 1T N4 1T A B N6 1T N5 N3 1T N6 N2 1T N1 1T a) Connection Diagram b) Winding Diagram Figure 12: Transformer Structure HF920 Rev. 1.02 12/3/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.HF920 21 HF920 – 900V, FIXED-FREQUENCY, OFFLINE SWITCHING REGULATOR Table 3: Winding Order Tape (T) Winding Terminal Start → End Wire Size (Ф) Turns (T) 1 N1 1 → NC 0.15mm*2 22 1 N2 2→1 0.15mm*1 170 1 N3 4→3 0.1mm*1 26 1 N6 5→6 0.3mm TIW *1 26 1 N4 10 → 9 0.16mm TIW *1 16 1 N5 A→B 0.16mm TIW *1 16 HF920 Rev. 1.02 12/3/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.HF920 22 HF920 – 900V, FIXED-FREQUENCY, OFFLINE SWITCHING REGULATOR FLOW CHART HF920 Rev. 1.02 12/3/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.HF920 23 HF920 – 900V, FIXED-FREQUENCY, OFFLINE SWITCHING REGULATOR EVOLUTION OF THE SIGNALS IN PRESENCE OF FAULTS HF920 Rev. 1.02 12/3/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.HF920 24 HF920 – 900V, FIXED-FREQUENCY, OFFLINE SWITCHING REGULATOR PACKAGE INFORMATION SOIC8-7A HF920 Rev. 1.02 12/3/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.HF920 25 HF920 – 900V, FIXED-FREQUENCY, OFFLINE SWITCHING REGULATOR PACKAGE INFORMATION (continued) SOIC14-11 NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. HF920 Rev. 1.02 12/3/2018 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved.HF920 26