HFC0100
Quasi-Resonant Controller
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The HFC0100 is a peak current mode controller
with green mode operation. It offers high
efficiency across over the entire line and load
range, and meet stringent worldwide energy
efficiency requirements.
The HFC0100 is integrated with a high-voltage
current source, and its valley detector ensures
minimum drain-source voltage switching (quasiresonant operation). When the output power
falls below a set level, the controller enters
burst mode.
The HFC0100 features protection features
including thermal shutdown (TSD), VCC undervoltage lockout (UVLO), overload protection
(OLP), and over-voltage protection (OVP).
The HFC0100 is available in a compact SOIC-8
package.
Universal Main Input Voltage (85VAC to
265VAC)
Quasi-Resonant Operation
Valley Switching for High Efficiency and EMI
Minimization
Active Burst Mode for Low Standby Power
Consumption
Internal High-Voltage Current Source
High Level of Integration Decreases
Required External Component Count
Maximum Frequency Limit
Internal Soft Start
Internal 250nS Leading-Edge Blanking
Thermal Shutdown (Auto-Restart with
Hysteresis)
VCC Under-Voltage Lockout with Hysteresis
(UVLO)
Over-Voltage Protection
Overload Protection
Available in an SOIC-8 Package
APPLICATIONS
Battery Chargers for Cell Phones, Digital
Cameras, Video Cameras, Electric Shavers,
Emergency Lighting Systems, etc.
Standby Power Supplies for CRT TVs,
Projection TVs, LCD TVs, PDP TVs,
Desktop PCs, Audio Systems, etc.
SMPS for Ink Jet Printers, DVD
Players/Recorders, VCRs, CD Players, SetTop Boxes, Air Conditioners, Refrigerators,
Washing Machines, Dishwashers, NB
Adapters, etc.
All MPS parts are lead-free, halogen free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are
registered trademarks of Monolithic Power Systems, Inc. or its subsidiaries.
HFC0100 Rev. 1.05
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1
HFC0100 – QUASI-RESONANT CONTROLLER
TYPICAL APPLICATION
T1
*
+
+
*
RTN
*
HV
4
5
Drive
N/C
3
6
CS
VCC
2
7
GND
VSD
1
8
FB
HFC0100 Rev. 1.05
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10/28/2021
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2
HFC0100 – QUASI-RESONANT CONTROLLER
ORDERING INFORMATION
Part Number*
HFC0100HS
Package
SOIC-8
Top Marking
HFC0100
Ambient Temperature (TA)
-40C to +125C
*For Tape & Reel, add suffix –Z (e.g. HFC0100HS–Z).
For RoHS compliant packaging, add suffix –LF (e.g. HFC0100HS–LF–Z).
PACKAGE REFERENCE
TOP VIEW
VSD
1
8
FB
VCC
2
7
GND
NC
3
6
CS
HV
4
5
Drive
SOIC-8
ABSOLUTE MAXIMUM RATINGS
(1)
HV breakdown voltage ............... -0.7V to +700V
VCC, DRV to GND .......................... -0.3V to +22V
FB, CS, VSD to GND ...................... -0.3V to +7V
Continuous power dissipation…(TA = 25°C) (2)
………………………………………………...1.3W
Junction temperature ................................ 150°C
Thermal shutdown .................................... 150°C
Thermal shutdown hysteresis ..................... 50°C
Lead temperature ...................................... 260°C
Storage temperature ................-60°C to +150°C
ESD Ratings
Human body model (all pins except HV) ..... 2kV
Machine model ............................................ 200V
Thermal Resistance (4)
θJA
θJC
SOIC-8 .................................... 96 ....... 45 ... C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX) - TA) / θJA. Exceeding the maximum allowable power
dissipation can cause excessive die temperature, and the
regulator may go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
Recommended Operation Conditions (3)
Operating VCC range ........................... 8V to 20V
Maximum junction temp (TJ) ................... 125°C
HFC0100 Rev. 1.05
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10/28/2021
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3
HFC0100 – QUASI-RESONANT CONTROLLER
ELECTRICAL CHARACTERISTICS
Typical values at TJ = 25°C, unless otherwise noted.
Parameter
Start-Up Current Source (HV Pin)
Symbol
HV charging current
ICHARGE
HV leakage current
ILEAK
Breakdown voltage
VBR
Supply Voltage Management (VCC Pin)
VCC upper level at which the internal
VCCH
high-voltage current source stops
VCC lower level at which the internal
VCCL
high-voltage current source triggers
VCC recharge level at which the
VCCP
protection occurs
Internal IC consumption, 1nF load on
ICC1
the DRIVE pin
Internal IC consumption, latch-off
ICC2
phase
Feedback Management (FB Pin)
Internal pull-up resistor
RFB
Internal pull-up voltage
VUP
FB pin to current limit division ratio
IDIV
Internal soft-start time
tSS
FB decreasing level at which the
VBURL
controller enters burst mode
FB increasing level at which the
VBURH
controller exits burst mode
Overload set point
VOLP
Valley Switching Management (VSD Pin)
Valley switching threshold voltage
VVSD
Valley switching hysteresis
VHYS
VVSDH
VSD clamp voltage
VVSDL
Valley switching propagation delay
tVSD
Minimum off time
tMIN
Restart time after last valley detection
tRESTART
transition
OVP sampling delay
tOVPS
VSD OVP reference level
VOVP
Internal impedance
RINT
Current-Sense Management (CS Pin)
Leading-edge blanking time
tLEB
Driving Signal (DRIVE Pin)
Sourcing resistor
RH
Sinking resistor
RL
Conditions
VCC = 6V,
VHV = 400V
With auxiliary
supply,
VHV = 400V,
VCC = 13V
Min
Typ
Max
Unit
1.4
2
2.6
mA
20
μA
700
V
10.6
11.8
13
V
7.2
8
8.8
V
5.5
V
fSW = 100kHz,
VCC = 12V
2.0
mA
VCC = 6V
450
μA
10
4.5
3
2.4
kΩ
V
ms
0.5
V
0.7
V
3.7
V
High State;
Ipin2=3.0mA
Low State;
Ipin2=-2.0mA
Pull down from 2V
to -100mV
40
55
10
70
mV
mV
7
7.5
8
-0.8
-0.65
-0.5
100
160
200
ns
6.6
7.8
9
μs
V
4.6
μs
3.5
6
24
μs
V
kΩ
250
ns
17
7
Ω
Ω
HFC0100 Rev. 1.05
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10/28/2021
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4
HFC0100 – QUASI-RESONANT CONTROLLER
PIN FUNCTIONS
Pin #
Name
1
VSD
2
VCC
3
4
5
6
7
NC
HV
DRIVE
CS
GND
8
FB
Description
Auxiliary flyback signal input. This pin ensures discontinuous operation and valley
switching. It also offers fixed over-voltage protection (OVP) detection.
Supply voltage. This pin is connected to an external bulk capacitor (typically 22μF) and a
ceramic capacitor (typically 0.1μF).
No connection. This pin ensures an adequate creepage distance.
Input for the start-up current unit.
Driving signal output.
Current-sense input.
Ground.
Feedback. This pin sets the peak current limit. Connect an optocoupler to FB. A 3.7V
feedback voltage (VFB) triggers overload protection, and a 0.5V VFB triggers burst mode
operation.
HFC0100 Rev. 1.05
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5
HFC0100 – QUASI-RESONANT CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
3400
1000
3000
800
2600
FS=100kHz
FS=60kHz
700
600
1800
8.5
11.8
8.3
11.6
8.1
11.4
11.2
0
25
50
12
10
7.9
9
TEMPERATURE (oC)
0
25
50
8
-40 -20
85 105 125
TEMPERATURE (oC)
Over Load Set Point
Vs Temperature
60
TMIN (us)
VOLP (V)
VVSD (mV)
0
25
50
85 105 125
50
TEMPERATURE (OC)
30
-40 -20
85 105 125
8.5
8
7.5
40
3.4
-40 -20
50
9
70
3.6
25
Minimum Off Time
Vs Temperature
80
3.8
0
TEMPERATURE (oC)
Valley Switching Threshold
Voltage Vs Temperature
4
0 25 50 85 105 125
TEMPERATURE (oC)
11
7.5
-40 -20
85 105 125
1.5
Pin FB Internal Pull Up
Resistor Vs Temperature
Vcc Lower Level at which
the Internal High Voltage
Current Source Triggers Vs
Temperature
7.7
11
-40 -20
2
1
-40 -20
10 11 12 13 14 15 16 17 18
VCC (V)
Vcc Upper Level at which
the Internal High Voltage
Current Source Stops Vs
Temperature
2.5
FS=60kHz
1000
10 11 12 13 14 15 16 17 18
VCC (V)
VCCL (V)
VCCH (V)
12
FS=100kHz
2200
1400
500
400
3
ICHARGE (mA)
1100
900
Charging Current From Pin
HV (Vcc=6V, VHV=400V) Vs
Temperature
IC Consumption Vs
Vcc (1nF Output Load)
ICC1 (uA)
ICC1 (uA)
IC Consumption Vs
Vcc (No Output Load)
0
25
50
85 105 125
TEMPERATURE (OC)
7
-40 -20
0
25
50
85 105 125
TEMPERATURE (OC)
HFC0100 Rev. 1.05
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6
HFC0100 – QUASI-RESONANT CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = 25°C, unless otherwise noted.
Pin VSD OVP reference level
Vs Temperature
OVP Sampling Delay
Vs Temperature
6.2
4
30
28
6.1
VREF (V)
3.6
3.4
26
6
24
5.9
3.2
3
-40 -20 0 25 50 85 105 125
TEMPERATURE (OC)
Sourcing Resistor
Vs Temperature
22
5.8
-40 -20
20
-40 -20
0 25 50 85 105 125
TEMPERATURE (OC)
Sinking Resistor
Vs Temperature
30
20
600
25
15
550
20
10
15
5
10
-40 -20
0
25
50
85 105 125
TEMPERATURE (OC)
800
VBURH(mV)
TSAMPLE (us)
3.8
Pin VSD Internal Impedance
Vs Temperature
0 25 50 85 105 125
TEMPERATURE (OC)
FB Decreasing Level
at which the controller
enter the Burst Mode
Vs Temperature
500
450
0
-40 -20
0
25
50
85 105 125
TEMPERATURE (OC)
400
-40 -20
0
25
50
85 105 125
TEMPERATURE (OC)
FB Increasing Level
at which the controller
leave the Burst Mode
Vs Temperature
VBURH(mV)
750
700
650
600
-40 -20
0
25
50
85 105 125
TEMPERATURE (OC)
HFC0100 Rev. 1.05
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7
HFC0100 – QUASI-RESONANT CONTROLLER
FUNCTIONAL BLOCK DIAGRAM
Figure 1: Functional Block Diagram
HFC0100 Rev. 1.05
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10/28/2021
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8
HFC0100 – QUASI-RESONANT CONTROLLER
OPERATION
The HFC0100 incorporates all the necessary
features needed for a reliable switch-mode
power supply. Its valley detection feature
ensures
minimum
drain-source
voltage
switching (quasi-resonant operation). When the
output power falls below a set level, the
regulator enters the burst mode. An internal
minimum off time limit prevents the frequency
from exceeding 150kHz.
Start-Up
Initially, the IC is self-supplied from the internal
high-voltage current source unit, which draws
from the HV pin. The IC starts switching and
turns off the internal high-voltage current source
unit as soon as the voltage on the VCC pin
reaches the VCCH threshold (11.8V).
To start up the IC, the VCC ramping up slew
rate should be slower than 2V/ms before VCC
reaches 2V. Taking into account the internal
current source capability, a minimum 4.7µF
capacitor is required. In addition, the VCC
capacitor should be able to maintain the VCC
level over VCCL (8V) before the FB level down to
VOLP (3.7V). This ensures that the start-up
process is not interrupted by overload
protection (OLP) detection.
Quasi-Resonant Operation
The HFC0100 operates in discontinuous
conduction mode (DCM). Valley detection
ensures
minimum
drain-source
voltage
switching (quasi-resonant operation).
As a result, there are virtually no primary switch
turn-on losses and no secondary diode
recovery losses. This helps reduce EMI noise.
The voltage conditions for valley detection can
be calculated with Equation (1):
(VDS Vin )x
Naux
24k
55mV
x
Npri 24k R VSD
(1)
Where VDS is the drain-source voltage of the
primary FET, VIN is the input voltage, NAUX is the
auxiliary winding turns of the transformer, and
NPRI is the primary winding turns of the
transformer.
The valley detector sends out a valley signal to
turn on the primary FET.
Figure 3 shows a typical drain-source voltage
waveform with valley switching.
VDS
100V/div
Valley Switching
4us/div
Figure 3: VDS with Valley Switching
To ensure the switching frequency remains
below the EN55022 start limit (150kHz), the
HFC0100 employs a 7.8μs internal minimum off
time limit (see Figure 4).
Figure 2 shows the valley detection unit.
+
2
Vcc
RVSD
1
VSD
55mV
HFC0100
Figure 2: Valley Detection
VDS
100V/div
Toff≥7.8uS
2us/div
Figure 4: Minimum Off Time Limit
HFC0100 Rev. 1.05
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9
HFC0100 – QUASI-RESONANT CONTROLLER
VCC Under-Voltage Lockout (UVLO)
When VCC falls below the UVLO threshold (VCCL
- 8V), the HFC0100 stops switching. The
internal high-voltage current source unit also
restarts, and the VCC external bulk capacitor is
recharged by it.
Figure 5 shows the typical waveform with VCC
under-voltage lockout.
The auxiliary
winding takes over
To avoid an accidental mistrigger due to the
oscillation of the leakage inductance and the
parasitic capacitance, the OVP sampling has a
tOVPS blanking time (typically 3.5μs) (see Figure
7).
VVSD
VCCH = 11.8V
VCC
If the OVP circuit is triggered, the HFC0100
stops switching and latches off. The controller
remains latched off until VCC falls to 3V, e.g.
when the user unplugs the power supply from
the main supply and replugs it in.
Sampling Here
VCCL = 8V
On
Internal
Current
Source
Off
0V
Driving
Signal
tOVPS
Figure 7: tOVPS Blanking Time
Figure 5: VCC Under-Voltage Lockout
Over-Voltage Protection (OVP)
If positive plateau of the auxiliary winding
voltage is proportional to the output voltage
(VOUT), then over-voltage protection (OVP) is
triggered and the HFC0100 uses the auxiliary
winding voltage instead of directly monitoring
VOUT.
Figure 6 shows the OVP sample unit.
VFB is continuously monitored. If VFB exceeds
the threshold (VOLP = 3.7V), the HFC0100 shuts
off the switching cycle. The device enters a safe
low-power mode operation that prevents any
serious thermal or stress damage to the part.
Once the fault is removed, the devices resumes
normal operation.
+
2
Vcc
RVSD
1
VSD
During start-up or load transient, VFB can rise
high enough temporarily to mistrigger overload
protection (OLP). To prevent this, the OLP
circuit is designed to be triggered only after VCC
falls below (VCCL = 8V).
6V
HFC0100
Figure 6: OVP Sample Unit
VOUT can be calculated with Equation (2):
VO
N aux
24kΩ
6V
N SEC 24kΩ R VSD
Overload Protection (OLP)
The maximum output power is limited by the
maximum switching frequency and the
maximum primary peak current. If the output
consumes more than the maximum output
power, VOUT is drawn below the set point. This
reduces the current through the optocoupler
LED, which also reduces the transistor current,
thus increases the FB voltage (VFB).
(2)
Where VOUT is the output voltage, NAUX is the
auxiliary winding turns of the transformer, and
NSEC is the secondary winding turns of the
transformer.
HFC0100 Rev. 1.05
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10
HFC0100 – QUASI-RESONANT CONTROLLER
Burst Operation
To minimize the power dissipation under noload and light-load conditions, the HFC0100
enters burst mode operation.
As the load decreases, VFB decreases. The
HFC0100 stops switching if VFB drops below the
threshold (VBURL = 0.5V). VOUT then starts to
drop at a rate that is proportional to the load,
which causes VFB to rise again. Once VFB
exceeds the threshold (VBURH = 0.7V), switching
resumes. VFB then falls and rises repeatedly.
Burst mode operation alternately enables and
disables switching cycle of the MOSFET,
thereby reducing switching loss under no-load
and light-load conditions.
Figure 8 shows the typical FB and DRIVE
waveform during the burst mode.
VBURH:0.7V
Current Limit Setting
The switching current is sensed by the resistor
series between the source of the FET and
ground. The current limit is determined by the
FB signal, calculated with Equation (3):
VLIMIT
VFB VFB
IDIV
3
(3)
To limit the maximum output power, the current
limit is clamped at 1V when VFB is above 3.3V.
Leading-Edge Blanking Time
In order to avoid premature termination of the
switching pulse due to the parasitic capacitance,
an internal leading-edge blanking (LEB) unit is
employed between the CS pin and the current
comparator input. During this blanking time
(tLEB), the path from the CS pin to the current
comparator input is blocked. Figure 9 shows the
leading-edge blanking time.
VLIMIT
VBURL:0.5V
VFB
200mV/div
tLEB = 250ns
VDrive
5V/div
40us/div
Figure 8: Burst Mode
Thermal Shutdown (TSD)
To protect the device from serious thermal
damage, the HFC0100 shuts down switching if
the inner temperature exceeds 150°C. Once the
inner temperature drops below 100°C, the
device resumes normal operation.
Soft Start
To reduce stress on the primary MOSFET and
secondary diode during start-up and to
smoothly establish VOUT, the HFC0100 has an
internal soft-start circuit that increases the
current comparator inverting the input voltage
and the MOSFET current slowly after the
device starts up. The pulse width is
progressively increased to establish the correct
working conditions for the transformers,
inductors, and capacitors.
t
Figure 9: Leading-Edge Blanking Time
Over-Power Compensation
In the case of current sensing, the FET turning
is delayed due to the control circuit’s
propagation delay. The delay time (tDELAY) is the
inherent characteristic of the control circuit (see
Figure 10).
HFC0100 Rev. 1.05
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11
HFC0100 – QUASI-RESONANT CONTROLLER
ILIMI T
ILIMIT2
ILIMIT1
ILIMIT
△I1△I2
t
tD ELA Y
tD ELA Y tD ELA Y
tD ELA Y
Figure 10: Current Limit Propagation Delay
This delay can cause an overshoot of the peak
current. △ I2 is greater than △ I1 due to the
greater rising ratio (the higher the input voltage,
the greater the rising ratio).
The propagation delay is set by the feedforward
resistor (see Figure 11). This method allows the
user to add an offset voltage at the CS pin (the
higher the input voltage, the greater the offset
voltage).
VBULK
RFEEDFORWARD
HFC0100
Current Comparator
T1
Q1
R1
6
CS
VREF
C1
RSENSE
Figure 11: Over-Power Compensation
Figure 12 on page 13 shows the HFC0100’s
control flowchart. Figure 13 on page 14 shows
the signal evolution in the presence of faults in
the HFC0100.
HFC0100 Rev. 1.05
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12
HFC0100 – QUASI-RESONANT CONTROLLER
Start
Y
Internal high-voltage
current source on
Shut down
internal high-voltage
current source
Y
VCC >
11.8V
N
VCC decreases
to 5.5V
Shut off the
switching pulse
Y
VCC <
8V
Y
Y
OTP =
logic
high?
N
Soft Start
VCC <
3V?
N
Latch off the
switching pulse
N
Y
OVP =
logic
high?
N
Thermal
Monitor
Monitor VCC
Pin VSD
Monitor
Monitor VFB
Y
VFB < 0.5V
0.5V < VFB < 3.7V
Burst Mode
Operation
Y
VFB >
0.7V
VFB > 3.7V
QR Mode Operation
N
tOFF <
7.8µs
N
Y
Constraint tOFF_MIN ≥
7.8µ s
VCC < 8V?
and
OLP = logic
high
Y
N
Continuous fault
monitoring
OLP = logic high
UVLO, OTP, and OLP are auto-retry,
OVP is latch-off.
To unlatch the device, unplug it from the
main input.
Figure 12: Control Flowchart
HFC0100 Rev. 1.05
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13
HFC0100 – QUASI-RESONANT CONTROLLER
VCC
Start-Up
Regulation
occurs here
Over-voltage
occurs here
Unplug from
main input Normal
Operation
Normal
Operation
Normal
Operation
11.8V
8.5V
5.5V
Driver
Pulses
Driver
High-Voltage
Current Source
On
Off
IFAULT Flag
Normal
Operation
OVP fault
occurs here
Normal
Operation
OLP fault
occurs here
Normal
Operation
OTP fault
occurs here
Normal Operation
Figure 13: Signal Evolution in the Presence of Faults
HFC0100 Rev. 1.05
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14
HFC0100 – QUASI-RESONANT CONTROLLER
PACKAGE INFORMATION
SOIC-8
0.189(4.80)
0.197(5.00)
8
0.050(1.27)
0.024(0.61)
5
0.063(1.60)
0.150(3.80)
0.157(4.00)
PIN 1 ID
1
0.228(5.80)
0.244(6.20)
0.213(5.40)
4
TOP VIEW
RECOMMENDED LAND PATTERN
0.053(1.35)
0.069(1.75)
SEATING PLANE
0.004(0.10)
0.010(0.25)
0.013(0.33)
0.020(0.51)
0.0075(0.19)
0.0098(0.25)
SEE DETAIL "A"
0.050(1.27)
BSC
SIDE VIEW
FRONT VIEW
0.010(0.25)
x 45o
0.020(0.50)
GAUGE PLANE
0.010(0.25) BSC
0o-8o
0.016(0.41)
0.050(1.27)
DETAIL "A"
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AA.
6) DRAWING IS NOT TO SCALE.
HFC0100 Rev. 1.05
www.MonolithicPower.com
10/28/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2021 MPS. All Rights Reserved.
15
HFC0100 – QUASI-RESONANT CONTROLLER
REVISION HISTORY
Revision #
Revision Date
1.0
01/05/2011
1.01
02/13/2011
1.02
1.03
11/25/2015
11/28/2017
1.04
08/06/2019
1.05
10/28/2021
Description
Initial Release
Updated the MOSFET BV voltage from 650V to
700V.
Limited the tVSD minimum value to 100ns.
Corrected the top marking.
Added some application key points in the Start-Up
section: “To start up the IC, the VCC ramping up
slew rate should be slower than 2V/ms before VCC
reaches 2V. Taking into account the internal current
source capability, a minimum 4.7µF capacitor is
required.”
Added some application key points in the Start-Up
section: “In addition, the VCC capacitor should be
able to maintain the VCC level over VCCL (8V) before
the FB level down to VOLP (3.7V). This ensures that
the start-up process is not interrupted by overload
protection (OLP) detection.” Changed the typical
VCC threshold for OLP triggering from 8.5V to 8V.
Grammar and formatting updates
Pages
Updated
3, 4
4
3
9
9, 10, 13
All
Notice: The information in this document is subject to change without notice. Users should warrant and guarantee that thirdparty Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
HFC0100 Rev. 1.05
www.MonolithicPower.com
10/28/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2021 MPS. All Rights Reserved.
16
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