MP1038
Full Bridge
CCFL Controller
Monolithic Power Systems
DESCRIPTION
FEATURES
The MP1038 is a fixed operating frequency
inverter controller that controls four external
N-Channel power MOSFETs in a full-bridge
configuration. The inverter is designed to power
one or more cold cathode fluorescent lamps
(CCFL) to backlight liquid crystal displays. Its
full-bridge architecture converts unregulated DC
input voltages to the nearly pure sine waves
required to ignite and operate CCFL.
•
For reliable lamp ignition, the operating frequency
is set by an external resistor and during startup, is
temporarily swept toward the unloaded resonant
frequency of the tank. The built-in burst oscillator
can be synchronized with an external clock to
minimize display scan interference. Burst mode or
analog mode dimming is controlled with an
external analog signal. Built-in fault management
features include an open lamp regulator, a
transformer secondary peak current regulator,
and a dual-mode fault timer. The secondary
over-current timeout can be shortened with
external components. Built-in current limits for the
external switches protect against inadvertent
shorts. The MP1038 is available in TSSOP28 and
SOIC28 packages.
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Controls Four External, Low Cost, N-Channel
MOSFETs
Fixed Operating Frequency
Input Voltage Range of 10V to 32V
Lamp Current and Voltage Regulation
Full-Wave Sense Amp
Analog and Burst Mode Dimming Control
Integrated Burst Mode Oscillator and Modulator
Soft On and Soft Off Burst Envelope
Open Lamp Protection
Secondary Over-Current Protection
Dual-mode, Fault Timer
Thermal Shutdown with Hysteresis
Available in TSSOP28 and SOIC28 Packages
APPLICATIONS
•
•
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Desktop LCD Flat Panel Displays
Flat Panel Video Displays
LCD TVs and Monitors
, “MPS”, “Monolithic Power Systems”, and “The Future of Analog IC
Technology” are Registered Trademarks of Monolithic Power Systems, Inc.
The MP1038 is covered by US Patents 6,683,422, 6,316,881, and 6,114,814.
Other Patents Pending.
TYPICAL APPLICATION
1
2
3
4
5
6
8
9
10
DBRT
ABRT
ENSYNC
LOK
11
12
13
14
PGL
LI
LGL
LV
VCCL
COMP
OUTL
AG
UGL
FT
BTL
LCS
LCC
MP1038
7
SI
PRL
PGR
BRC
LGR
BRS
VCCR
DBRT
OUTR
ABRT
UGR
ENSYNC
BTR
LOK
PRR
28
GND
27
26
25
24
23
22
21
20
19
18
17
16
15
VPS
MP1038_TA01
10/07, Rev. 1.4
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1
MP1038 – FULL BRIDGE CCFL CONTROLLER
ABSOLUTE MAXIMUM RATINGS (1)
PACKAGE REFERENCE
Input Voltage VPRR, VPRL ............................... 35V
Logic Inputs ................................... -0.3V to 6.5V
Inputs SI, LI, LV .................................-5V to +5V
Junction Temperature...............................150°C
Power Dissipation...................................... 0.6W
Junction Temperature...............................150°C
Lead Temperature (Solder) ......................260°C
Operating Frequency..............................150kHz
Storage Temperature ...............-55°C to +150°C
Recommended Operating Conditions
(2)
Input Voltage VPRR, VPRL .................... 10V to 32V
Analog Brightness Voltage VABRT ....... 0V to 1.2V
Digital Brightness Voltage VDBRT ........ 0V to 1.2V
Enable Voltage VEN ............................ 0V to 5.0V
Operating Frequency.............. 20kHz to 100kHz
Operating Frequency (Typical) .................60kHz
Operating Temperature .............-20°C to + 85°C
Thermal Resistance
Part Number*
Package
Temperature
MP1038EM
MP1038EY
TSSOP28
SOIC28
-20ºC to +85ºC
-20ºC to +85ºC
*
For Tape & Reel, add suffix –Z (eg. MP1038EM–Z)
For Lead Free, add suffix –LF (eg. MP1038EM-LF-Z)
(3)
ΘJA (TSSOP28)...................................... 82°C/W
ΘJC (TSSOP28) ..................................... 20°C/W
ΘJA (SOIC28) ......................................... 60°C/W
ΘJC (SOIC28)......................................... 30°C/W
Notes:
1) The device is not guaranteed to function outside of its
operating conditions.
2) Exceeding these ratings may damage the device.
3) Measured on approximately 1” square of 1 oz copper.
ELECTRICAL CHARACTERISTICS
VPRR = VPRL = 17.5V,VBRC = VLCC = GND, TA = 25C, unless otherwise noted.
Parameter
Output
Gate Pull-Down
Gate Pull-Up
Damper On Resistance
ENSYNC
Threshold
Hysteresis
Sync Timing
Sync Minimum Pulse Width
Sync Maximum Pulse Width
Sync Rate
DBRT Logic Input Threshold
DBRT Logic Input Hysteresis
10/07, Rev. 1.4
Symbol
Condition
Min
Typ
RGD
RGU
RON
1.6
34
1.1
VTH
VTH_HYS
1.35
0.3
tSYNC(MIN)
tSYNC(MAX)
fSYNC
VTH
VTH_HYS
1
10
200
2.1
0.4
VBRS = VCC
VBRS = VCC
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1.8
Max
Units
Ω
Ω
kΩ
2.0
2.3
V
V
µs
µs
Hz
V
V
2
MP1038 – FULL BRIDGE CCFL CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VPRR = VPRL = 17.5V,VBRC = VLCC = GND, TA = 25C, unless otherwise noted.
Parameter
Brightness Control Range
DBRT Full Scale
ABRT Full Scale
Burst Rate Generator
Source Current
Lower Threshold
Upper Threshold
Supply Current
Supply Current (enabled)
Supply Current (disabled)
Operating Frequency
Accuracy of f0
Sweep Range
Control Input Current
Frequency Set Voltage
Lamp Current Feedback
Magnitude
Symbol
Min
VDBRT
VABRT
ISRC(BRS)
VV(BRS)
VP(BRS)
IPR
IPR
f0
|VLI|
Typ
Max
1.2
1.2
VBRS = 2V
V
V
140
2.35
3.5
165
2.5
3.7
uA
V
V
2
10
mA
µA
KHz
%
1.10
1.4
1
50
3
1.6
-1
1.2
1.30
µA
V
1.134
0.36
1.20
0.40
1.33
3
62
1.266
0.44
V
V
Vrms
%
kΩ
VTH(LV)
1.15
1.20
1.25
V
VTH(SI)
1.15
1.20
1.25
V
Vt(FT)
1.15
1.25
ISINK(FT)
ISO(FT)+
ISP(FT)+
1.20
-1
1
55
V
µA
µA
µA
VCOMP
ICOMP+
ICOMP-
0.56
20
60
VLI
VLI
VABRT > 1.2 V
VABRT = 0 V
VABRT > 1.2 V
Units
115
2.2
3.3
R3 = 100kΩ
FMAX/f0
ILCC
VLCS
Sine Equivalent
Accuracy
Input Resistance
Open Lamp Voltage Feedback
Threshold (peak)
Secondary Peak Current Threshold
Fault Timer
Threshold
Sink Current
Open lamp source current
Secondary over-current source current
Comp
Clamp Voltage
Reference Current
Decay Current
Output (VCCR and VCCL)
Voltage
Current
Shutdown Temperature
Hysteresis
10/07, Rev. 1.4
Condition
VLI< 0 V
End of Burst
VCC
ICC
TSD
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5.7
6.0
5
140
20
V
µA
µA
6.3
V
mA
C
C
3
MP1038 – FULL BRIDGE CCFL CONTROLLER
PIN FUNCTIONS
For TSSOP28 and SOIC28 devices
Pin #
Name
1
SI
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Description
Secondary Current Feedback Input. Connect a current sense resistor from the cold end of
the secondary winding to ground. Connect this pin to the junction of the resistor and the
secondary winding. If the voltage at SI exceeds +1.2V, a pulse of current will pull down on
the COMP pin to attempt to regulate the secondary current and the Fault Timer will be
started.
LI
Lamp Current Feedback Input. Connect this pin to the cold end of the lamp and shunt a
sense resistor to ground. The sense amplifier will sink a current from the COMP pin
proportional to the absolute value of the voltage at this pin. (In regulation the average of the
absolute value of the voltage at this pin is determined by the voltage at the ABRT pin).
LV
Lamp Voltage Feedback Input. Connect a capacitive voltage divider from the hot end of the
lamp to ground. Connect this pin to the tap on the divider and shunt a bias resistor to
ground. If the voltage at LV exceeds +1.2 V, a pulse of current will pull down on the COMP
pin to attempt to regulate the lamp voltage and the Fault Timer will be started.
COMP
Feed back Compensation Node. Connect a compensation capacitor from this pin to ground.
AG
Analog Ground.
FT
Fault Timing. Connect a timing capacitor from this pin to AG to set the fault timeout period.
LCS
Lamp operating Clock Set. Connect a resistor from this pin to AG. This resistor sets the
operating frequency of the MP1038.
LCC
Lamp Clock Control. LCC provides compensation when the operating clock is swept in order
to strike the lamp. Connect a resistor in series with a capacitor from LCC to AG. Connect a
smaller capacitor directly from LCC to AG. Connect only a single capacitor to AG, if some
sweeping of the operating clock can be tolerated during open lamp conditions. Connect LCC
to AG to force the operating clock to the selected value at all times.
BRC
Burst Repetition rate Control. BRC provides compensation when the burst repetition rate is
to be synchronized to an external clock. Connect a resistor in series with a capacitor from
BRC to AG. Connect a smaller capacitor directly from BRC to AG. If the burst repetition rate
is not to be synchronized to an external clock, connect BRC to AG.
BRS
Burst Repetition rate Setting. If the burst repetition rate is to be synchronized to an external
clock, connect a capacitor from BRS to AG. If the burst rate generator is free-run and not be
synchronized with an external clock, connect a resistor in parallel with a capacitor from BRS
to AG. If the burst is to be controlled by an external logic signal, connect BRS to VCC and
apply the logic signal to the DBRT pin.
DBRT
Burst-Mode (Digital) Brightness Control Input. The voltage range of 0V to 1.2V at DBRT
linearly sets the burst-mode duty cycle from minimum 10% to 100%. If burst dimming is not
used tie DBRT to VCC.
ABRT
Analog Brightness Control Input. The voltage range of 0V to 1.2V at ABRT sets 3:1 dimming
range for the lamp current. If analog dimming is not used, tie ABRT to VCC.
ENSYNC Enable and Sync Composite Input. Pull ENSYNC high to turn on the MP1038, pull ENSYNC
low to turn it off. To synchronize the burst repetition rate to an external clock, apply the
synchronizing clock signal with low-going pulse width of 1-10us to this pin. Once the
MP1038 has aligned the burst oscillator to the sync signal, each burst will start at the lowgoing edge of the sync pulse.
LOK
Lamp OK Flag Output (open drain). Connect this pin to a pull-up resistor to logic high. This
pin will not be activated during normal operation (including burst mode) nor when the
MP1038 is disabled. This pin will be pulled low when a fault (open lamp or secondary
over-current) is detected.
PRR
Input Power Rail, Right-Side. Connect PRR directly to the drain of the high-side, right-side,
external power MOSFET.
10/07, Rev. 1.4
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4
MP1038 – FULL BRIDGE CCFL CONTROLLER
PIN FUNCTIONS (continued)
For TSSOP28 and SOIC28 devices
Pin #
16
Name
BTR
17
UGR
18
OUTR
19
VCCR
20
LGR
21
22
PGR
PRL
23
BTL
24
UGL
25
OUTL
26
VCCL
27
LGL
28
PGL
10/07, Rev. 1.4
Description
Output Bootstrap, Right-Side. BTR provides gate bias for the right-side high-side MOSFET.
Connect a capacitor from BTR to OUTR.
High-Side MOSFET Gate Output, Right-Side. Connect UGR to the gate of the high-side,
right-side, external power MOSFET.
Bridge Output, Right-Side. Connect OUTR to the source of the right-side, high-side
MOSFET and the drain of the low-side, right-side MOSFET.
Voltage Rail Output, Right-Side. VCCR allows bypassing the bias supply for the control
circuitry. Bypass VCCR with a 0.47uF capacitor. Connect to VCCL.
Low-Side MOSFET Gate Output, Right-Side. Connect LGR to the gate of the low-side,
right-side MOSFET.
Power Ground, Right-Side. Connect PGR to the source of the low-side, right-side MOSFET.
Input Power Rail, Left-Side. Connect PRL directly to the drain of the high-side, left-side,
external power MOSFET.
Output Bootstrap, Left-Side. BTL provides gate bias for the left-side high-side MOSFET.
Connect a capacitor from BTL to OUTL.
High-Side MOSFET Gate Output, Left-Side. Connect UGL to the gate of the high-side,
left-side, external power MOSFET.
Bridge Output, Left-Side. Connect OUTL to the source of the left-side, high-side MOSFET
and the drain of the left-side, low-side MOSFET.
Voltage Rail Output, Left-Side. VCCL allows bypassing the bias supply for the control
circuitry. Bypass VCCL with a 0.47uF capacitor. Connect to VCCR.
Low-Side MOSFET Gate Output, Left-Side. Connect LGL to the gate of the low-side,
left-side MOSFET.
Power Ground, Left-Side. Connect PGL to the source of the low-side, left-side MOSFET.
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5
MP1038 – FULL BRIDGE CCFL CONTROLLER
OPERATION
VPS
1
R8
3
SI
LV
1.2V
1.2V
C2
R2
C1
R3
VPS
R4
6
FT
2
LI
12
ABRT
4
COMP
7
LCS
8
LCC
FAULT
MANAGEMENT
LEVEL
SHIFT
ERROR
AMP
LAMP
PWM
LAMP
CLOCK
C3 C4
R6
10
BRS
C7
C5
R5
9
BRC
C6
PRL
22
UGL
24
BTL
23 C10
OUTL
25
LGL
27
PGL
28
VCCL
CONTROL LOGIC
R1
VPS
LEVEL
SHIFT
BURST
RATE
GENERATOR
R10
D1
R7
ENSYNC
11
DBRT
14
LOK
5
AG
BURST
PWM
VCCR
C12
R9
PRR
15
UGR
17
BTR
16 C8
C13
OUTR
18
C14
LGR
20
PGR
21
VCCR
13
26 C11
19 C9
SI LV
LI
MP1038_BD01
Figure 1—MP1038 Block Diagram
DESIGN INFORMATION
The The MP1038 is a fixed operating frequency
inverter controller specifically designed to drive
a cold cathode fluorescent lamp (CCFL) used
as a backlight for liquid crystal displays.
Designed to run off 10V to 32V input supplies,
the MP1038 can drive up to 30 lamps (150W)
via four (4) external N-Channel MOSFETs. Its
full bridge architecture converts unregulated DC
input voltages to the nearly pure sine waves
required to ignite and operate CCFLs. Operating
frequency is set by an external resistor to
minimize the possibility of interference with the
refresh rate of the display.
To ensure ignition of the lamp, the operating
frequency is swept temporarily to the unloaded
resonant frequency of the tank. Regulated lamp
current and maximum peak transformer
secondary current are set by external resistors.
10/07, Rev. 1.4
Regulated open lamp voltage is set by an
external capacitive voltage divider. Soft startup
of the lamp minimizes the peak transformer
secondary voltage. The MP1038 implements burst
mode dimming of the lamp and features softon-soft-off control of the lamp current envelope
that is virtually independent of supply voltage.
Burst repetition rate and duty cycle can either
be determined by driving the MP1038 with an
external logic signal or by choosing an external
resistor and capacitor to set the burst rate and
modulating the duty cycle with a DC control
voltage on DBRT.
Loop gain is compensated for variations in
supply voltage and the full-wave lamp current
sense amplifier provides superior output pulse
symmetry, loop response time, and phase
margin.
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6
MP1038 – FULL BRIDGE CCFL CONTROLLER
Careful management of limit conditions
provides graceful reduction of lamp power at
low supply voltages but allows the loop to
recover quickly from an abrupt step in supply
voltage. System fault management facilities
include an on-chip open-lamp regulator, a
transformer secondary peak current regulator,
and a dual-mode fault timer.
By regulating the peak current in the
transformer secondary winding, UL1950 can be
met for most systems. When the MP1038 is
regulating open lamp voltage, it ignores the
burst control and runs continuously to ensure
either the lamp has a chance to re-ignite or the
fault timer can smoothly and accurately time out.
If the MP1038 detects an open lamp condition
for a time that exceeds the timer interval, it will
shut down until the part is turned off and then
turned on again. Similarly, the MP1038 will shut
down if it detects an over-current condition in
the secondary for about 2% of the open lamp
timer interval. If required, the secondary overcurrent timeout can be shortened with external
components. On-chip current limit and thermal
shutdown protect the MP1038 in case of output
fault conditions. In the event that the die
temperature exceeds about 140°C, the MP1038
will cease operation until the die temperature
has fallen below about 120°C and then will
make a normal restart.
Higher phase delay will lead to higher primary
RMS current and therefore higher transformer
temperature. With ZCS, A & D conduction start
at the zero crossing of IPRI.
The MP1038 does not utilize ZVS or ZCS. It
implements fast switching to reduce switching
loss and operates at the condition that IPRI and
VPRI in phase to reduce primary RMS current.
Therefore, higher efficiency than ZVS or ZCS is
achieved.
VPS
A
B
VPRI
IPRI
A,D
D
B,C
ZVS
0
ZCS
0
MP1038
0
IPRI:
MP1038_F02_VIPRI
Figure 2—VPRI vs. IPRI
FEATURE DESCRIPTION
All reference designators refer to Figure 1,
unless otherwise designated.
High Efficiency Operation
There are two major power losses in a CCFL
inverter: switching loss of switches and cooper
loss of the transformer winding. To reduce
switching loss, Zero Current Switching (ZCS as
described in US patent 6,114,814) or Zero Voltage
Switching (ZVS) are commonly implemented.
As shown in Figure 2, ZCS and ZVS require
primary current IPRI lagging primary voltage VPRI.
With ZVS, since D1 can only conduct at the
negative phase of IPRI, the beginning of A & D
conduction will only happen at the negative
phase of IPRI.
10/07, Rev. 1.4
C
D1
+
VPRI:
VPS
Brightness Control
The MP1038 can operate in four modes:
Analog Mode, Burst Mode with a DC input,
Burst Mode with an external PWM or Analog
and Burst Mode. The four modes are
dependent on the pin connections defined
under Pin Functions.
Choosing the required burst repetition
frequency can be achieved by an RC
combination, as defined in component selection.
The MP1038 has a soft-on and soft-off feature
to reduce noise, when using burst mode
dimming. Analog dimming and Burst dimming
are independent of each other and may be
used together to obtain a wider dimming range.
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7
MP1038 – FULL BRIDGE CCFL CONTROLLER
Table 1—Function Mode
Function
Pin Connection
ABRT
Analog Mode 0 – 1.2V
DBRT
BRS
Ratio
VCC
R6
C7
3:1
Burst Mode
R6
VCC
0 – 1.2V
with DC
C7
Input Voltage
Burst Mode
VCC
PWM
VCC
with External
Source
R6
Analog and
0 – 1.2V 0 – 1.2V
C7
Burst Mode
Analog and
Burst Mode
0 – 1.2V PWM
VCC
with External
Source
10:1
Set by
Customer
30:1
Set by
Customer
Brightness Polarity
Burst: 100% duty cycle is at 1.2V
Analog: 1.2V is maximum brightness
Fault Protection
Open Lamp: The LV pin (#3) is used to detect
whether an open lamp condition has occurred.
If the voltage at LV exceeds +1.2V, a pulse of
current will pull down on the COMP pin to
regulate the lamp voltage. The Fault Timer will
be started with a 1μA current source injecting
into C2 at the FT pin, while the fault condition
persists. If the voltage at the FT pin exceeds
1.2V, then the chip will shut down.
Excessive Secondary Current (Shorted Lamp):
The SI pin (#1) is used to detect whether
excessive secondary current has occurred. If a
fault condition occurs that increases the
secondary current, then the voltage at SI will be
greater than 1.2V. A pulse of current will pull
down on the COMP pin to regulate the
secondary current. The Fault Timer will be
started with a 55μA current source injecting into
C2 at the FT pin, while the fault condition
persists.
If the voltage at the FT pin exceeds 1.2V, then
the chip will shut down and needs to be
re-enabled.
Fault Timer: The timing for the fault timer will
depend on the sourcing current, as described
above, and the capacitor C2 on the FT pin. The
user can program the time for the voltage to
rise after the chip detects a “real“ fault. When a
fault is triggered, then the internal voltage (VCC)
will collapse from 6V to 0V. If no fault is
detected a 1μA current sink will keep FT to 0V.
Startup
For reliable ignition of the lamp, the operating
frequency is swept temporarily toward the
unloaded resonant frequency of the tank during
startup. This guarantees the strike voltage of
the lamp at any temperature due to a resonant
topology for switching the outputs and
eliminates the need for external ramp timing
circuits to ensure startup. Once the strike
voltage is achieved, the switching frequency is
gradually adjusted to the preset fixed value.
The operating frequency before the lamp strikes
can be swept as much as 140% of the preset
frequency value.
Chip Enable
The chip has an ON/OFF function, which is
controlled by the ENSYNC pin (#13). The
enable signal goes directly to a Schmitt trigger.
The chip will turn ON with an ENSYNC = High
and OFF with an ENSYNC = Low.
The Burst waveform can be synchronized to an
external reference clock. To do this, remove R6
and combine a low-going synchronization signal
with the enable signal at the ENSYNC pin. The
synchronizing pulses should be 1µs - 10µs wide
and should occur at the desired burst repetition
frequency.
APPLICATION INFORMATION
Pin 1 (SI), R1:
Secondary Short Protection: The R1 is used for
feedback to the SI pin to detect excessive
secondary current. The value for R1 is calculated
as 1.2V divided by the secondary peak current.
10/07, Rev. 1.4
Pin 2 (LV): C13, C14 and R8:
Open Lamp protection: The regulated open
lamp voltage is proportional to the C14 and C13
ratio. C13 has to be rated at 3kV and is typically
between 5 to 22pF. The value of C14
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8
MP1038 – FULL BRIDGE CCFL CONTROLLER
is set by the customer to achieve the required
open lamp voltage detection value.
R3 =
C14 = C13 × 1.18 × V(MAX )rms
For R3 = 100kΩ, operating clock will be 50kHz.
The value of bias resistor R8 is typically 100kΩ
(not critical).
Pin 2 (LI), R2:
Lamp Current Regulation: The R2 is used for
feedback to the LI pin to regulate the lamp
current. The value for R2 is calculated as 1.33V
divided by the lamp rms current (assuming
VABRT is greater than 1.2V). For RMS 6mA lamp
current, R2 value is 220Ω.
Pin 6 (FT), C2:
The C2 is used to set the fault timer. This
capacitor will determine when the chip will
reach the fault threshold value.
Open Lamp Time Out:
C2 (nF ) =
t OPEN LAMP × 1μA
1.2 V
For a C2 = 820nF, then the time out for open
lamp will be 0.98 sec.
Secondary Overcurrent Timeout: When the
MP1038 is regulating secondary overcurrent (SI
feedback), the source current in the Fault Timer
(FT) cap is approximately 55uA. This causes
the SI timeout to be about 1/55 of the Open
Lamp (LV) timeout. To reduce the SI timeout
further, modify the network at the FT pin as
shown in Figure 3.
FT
C2A
C2B
MP1038_F03_TOTA
Figure 3—Timout Adjustment
For a C2B = 10nF, then the time out for
secondary short will be 0.2ms.
Note: The open lamp time out will remain the
same value as defined by C2A.
Pin 7 (LCS), R3:
R3 is used to set the lamp operating clock. The
value for R3 is calculated by
10/07, Rev. 1.4
5e 9
fο
Pin 8 (LCC):
This is lamp clock control compensation pin and
needs a lag lead lag capacitor/resistor network.
Pin 9 (BRC):
This is burst rate control compensation pin and
needs a lag lead lag capacitor/resistor network.
Pin 4 (COMP), C1:
C1 is feedback compensation capacitor that
connects between COMP and AG. A 1.5nF or
2.2nF cap is recommended. This cap should be
X7R ceramic. The value of C1 affects the softon rise time and soft-off fall time.
Pin 14 (Lamp OK), R7:
Lamp OK (LOK) is a normally high logic signal.
If a fault occurs, the signal will go low. The R7
is a pull-up resistor connected between a logic
high and the LOK pin. If SI or LV voltage trips
the fault timer this pin will go low. A 10kΩ or
greater is recommended for this resistor.
Pin 15 (PRR), Pin 21 (PGR), Pin 22 (PRL), Pin
28 (PGL):
These pins are used to sense the voltages
across the external power transistors. These
voltages are used by the MP1038 to protect the
power transistors in the event of an accidental
short from the output of the bridge to ground or
the positive rail. It also detects the zero
crossings of the AC current in the primary of the
power transformer. PRR and PRL should make
a Kelvin connection to the drains of the highside power MOSFETs in the output bridge.
PGR and PGL should make a Kelvin
connection to the sources of the low-side power
MOSFETs in the output bridge.
Pin 18 (OUTR), Pin 25 (OUTL), C12, R9:
OUTR and OUTL pins are used to sense the
voltage at the output of the full bridge. They
also are the point of access for the output
dampers. OUTR and OUTL should make a
Kelvin connection to the sources of the highside MOSFETs and the drains of the low-side
MOSFETs in the output bridge.
The primary transformer current flows through
capacitor C12. Its value is typically 2.2μF.
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9
MP1038 – FULL BRIDGE CCFL CONTROLLER
This capacitor should be ceramic and has a
ripple current rating greater than the primary
current. It is more optimal to use two parallel
1μF ceramic caps for minimal ESR losses. R9
is used to ensure that the bridge outputs are at
0V prior to startup. Typically R9 = 1kΩ.
Pin 16 (BTR), Pin 23 (BTL), C8, C10:
BTR and BTL are the bias supplies for the level
shift of the upper MOSFETs. C8 and C10
should be 22nF and made of X7R ceramic
material.
brightness. Ensure that tMIN is long enough that
the lamp does not extinguish.
These values are determined as follows:
Select a Minimum Duty Cycle, DMIN, where:
DMIN = t MIN × fBurst
DMIN =
If operating in Free-Running mode:
Pin 19 (VCCR), Pin 26 (VCCL), C9, C11:
These capacitors bypass the 5V gate supply for
the low-side switches. They also supply power
to the MP1038. These pins should be bypassed
with a 0.47µF ceramic X7R capacitor.
R6 =
IMPORTANT–For All Applications, VCCR and VCCL
must be connected together and connected to
ENSYNC via the resistor/diode (R10, D1), see Figure 1.
Pin 13 (ENSYNC):
ENSYNC is a composite of the Enable and the
Burst Oscillator Synchronization function. This
pin will enable and disable the chip when the
enable function is used.
To synchronize the Burst Oscillator to an
external signal, remove R6 from BRS pin and
apply a 1μs to 10µs pulse with a falling edge
trigger and a repetition rate of 200Hz. The Burst
Oscillator will then be synchronized with this
signal and start a burst on its falling edge.
Pin 11 (DBRT):
This pin is used for burst brightness control.
The DC voltage on this pin will control the burst
percentage on the output. The signal is filtered for
optimal operation. A voltage ranging from 0 to
1.2V on DBRT will correspond to a Burst Duty
Cycle of 10% to 100% respectively.
For direct Pulse Width Modulation of the burst
signal, connect BRS to VCC and connect DBRT
with a logic level PWM signal. A logic High is
Burst On and a logic Low is Burst Off.
Pin 10 (BRS): C7, R6:
BRS is used to set the Burst Repetition Rate.
C7 and R6 will set the burst repetition rate and
the minimum burst time: tMIN. Set tMIN to achieve
the minimum required system
10/07, Rev. 1.4
t FALL
(t FALL + t RISE )
⎡⎛
⎤
⎞
1
⎟⎟ Vbg ⎥
⎢ ⎜⎜
⎢ ⎝ DMIN − 1⎠
⎥
⎢
⎛ Vp + Vv ⎞ ⎥
⎢ γ+⎜
⎟⎥
2
⎝
⎠ ⎥⎦
⎢⎣
lb
⎞
⎛
1
⎟⎟ + 10k
R6 ~ 9.88k ⎜⎜
⎝ DMIN − 1⎠
For DMIN = 0.1 and R6 = 176k
1 − DMIN
C7 =
fb × R6 × γ
For DMIN = 0.1, R6 = 176k, fb = 200Hz, then C7
= 63nf
DMIN = Minimum Burst Duty Cycle
Vbg = Vp - Vv (~1.2V)
Vp = peak BRS voltage (~3.6V)
Vv = valley BRS voltage (~2.4V)
⎛3⎞
γ = ln⎜ ⎟ ≈ 0.405
⎝ 2⎠
Ib = BRS sink current (~160µA)
fb = burst repetition rate
If operating in Synchronous mode:
C7 =
lb × t MIN
Vbg
tMIN = Minimum Burst Time
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10
MP1038 – FULL BRIDGE CCFL CONTROLLER
PACKAGE INFORMATION
TSSOP28
0.0256(0.650)TYP
0.004(0.090)
0.010(0.250)
GATE PLANE
PIN 1
IDENT.
0.169
0.177
0.004(0.090)
0.244
0.260
(4.300)
(4.500)
0o-8o
(6.200)
(6.600)
0.030(0.750)
0.018(0.450)
0.030(0.750)
DETAIL "A"
0.039(1.000)REF
SEE DETAIL "B"
0.030(0.750)
SEE DETAIL "A"
0.337 (9.600)
0.386 (9.800)
0.075(0.190)
0.012(0.300)
0.032(0.800)
0.041(1.050)
0.033(0.850)
0.047(1.200)
0.007(0.190)
0.012(0.300)
SEATING PLANE
0.002(0.050)
0.006(0.150)
0.004(0.090)
0.008(0.200)
0.004(0.090)
0.006(0.160)
0.007(0.190)
0.010(0.250)
NOTE:
1) Control dimension is in inches. Dimension in bracket is millimeters.
DETAIL "B"
SOIC28
0.689
0.706
0.026 REF
0.020
0.040
7°BSC
0.025
R = 0.035
0.291
0.299
0.014
0.020
0.050BSC
0° - 8°
0.398
0.414
0.096
0.104
0.009
0.011
0.004
0.012
NOTICE: MPS believes the information in this document to be accurate and reliable. However, it is subject to change without
notice. Contact MPS for current specifications. MPS encourages users of its products to ensure that third party Intellectual
Property rights are not infringed upon when integrating MPS products into any application. MPS cannot assume any legal
responsibility for any said applications.
MP1038 Rev. 1.4
10/10/07
© 2004 MPS, Inc.
Monolithic Power Systems, Inc.
983 University Avenue, Building A, Los Gatos, CA 95032 USA
Tel: 408-357-6600 ♦ Fax: 408-357-6601 ♦ www.MonolithicPower.com
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