MP1530
Triple Output Step-Up
Plus Linear Regulators for TFT Bias
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP1530 combines a triple output step-up
converter with linear regulators to provide a
complete DC/DC solution. It is designed to
power TFT LCD panels from a regulated 3.3V
or 5V supply.
This
device
integrates
a
1.4MHz
fixed-frequency step-up converter with positive
and negative linear regulators. The step-up
converter switch node drives two charge
pumps, which supply powers to their respective
linear regulators. The positive and negative
linear regulator inputs can withstand up to 38V
and down to -20V, respectively.
A single on/off control enables all 3 outputs.
The outputs are internally sequenced at startup
for ease of use. An internal soft-start prevents
input overload at startup. Cycle-by-cycle current
limiting reduces component stress.
The MP1530 is available in a tiny 3x3mm, 16pin QFN package or a 16-pin TSSOP package.
EVALUATION BOARD REFERENCE
Board Number
Dimensions
EV0055
2.4”X x 2.3”Y x 0.4”Z
TYPICAL APPLICATION
2.7 to 5.5V Operating Input Range
2.8A Switch Current Limit
3 Outputs In a Single Package
Step-Up Converter up to 22V
Positive 20mA Linear Regulator
Negative 20mA Linear Regulator
250mΩ Internal Power MOSFET Switch
Up to 95% Efficiency
1.4MHz Fixed Frequency
Internal Power-On Sequencing
Adjustable Soft-Start/Fault Timer
Cycle-by-Cycle Over Current Protection
Under Voltage Lockout
Ready Flag
16-Pin, QFN (3x3mm) or TSSOP Packages
APPLICATIONS
TFT LCD Displays
Portable DVD Players
Tablet PCs
Car Navigation Displays
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Power Systems, Inc.
VIN
3.3V/5V
Efficiency vs
Load Current
(Step-Up Converter Only)
100
TO
SW
IN
RDY
EN
SW
COMP
FB1
VMAIN
IN2
MP1530
VGL
IN3
GL
FB2
GH
FB3
MP1530 Rev. 1.41
5/25/2011
80
PGND
VIN = 3.3V
70
60
50
40
30
20
REF
GND
VGH
EFFICIENCY (%)
CT
OFF ON
VIN = 5.0V
90
VMAIN = 13V
1
10
100
LOAD CURRENT (mA)
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© 2011 MPS. All Rights Reserved.
1000
1
MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS
ORDERING INFORMATION
Part Number
Top Marking
Free Air Temperature (TA)
MP1530DQ*
Package
QFN16 (3x3mm)
B8
-40C to +85C
MP1530DM**
TSSOP16
M1530DM
-40C to +85C
* For Tape & Reel, add suffix –Z (g. MP1530DQ–Z).
For RoHS compliant packaging, add suffix –LF (e.g. MP1530DQ–LF–Z)
* *For Tape & Reel, add suffix –Z (g. MP1530DM–Z).
For RoHS compliant packaging, add suffix –LF (e.g. MP1530DM–LF–Z)
PACKAGE REFERENCE
TOP VIEW
PGND
IN3
GH
IN2
16
15
14
13
TOP VIEW
SW
1
12
GL
CT
2
11
EN
RDY
3
10
FB3
FB1
9
4
5
6
7
8
COMP
IN
GND
REF
FB2
QFN16
ABSOLUTE MAXIMUM RATINGS (1)
IN Supply Voltage .......................... –0.3V to +6V
SW Voltage .................................. –0.3V to +25V
IN2, GL Voltage ........................... +0.3V to –25V
IN3, GH Voltage ........................... –0.3V to +40V
IN2 to IN3 Voltage ....................... –0.3V to +60V
All Other Pins ................................. –0.3V to +6V
(2)
Continuous Power Dissipation (TA = +25°C)
QFN16 (3 x 3mm)…………………………....2.1W
TSSOP16
………………… ………....1.4W
Junction Temperature ...............................125C
Lead Temperature ....................................260C
Storage Temperature ............. –65C to +150C
Recommended Operating Conditions (2)
Input Voltage ................................... 2.7V to 5.5V
Main Output Voltage ...........................VIN to 22V
IN2, GL Voltage ................................ 0V to –20V
MP1530 Rev. 1.41
5/25/2011
RDY
1
16
CT
FB1
2
15
SW
COMP
3
14
PGND
IN
4
13
IN3
GND
5
12
GH
REF
6
11
IN2
FB2
7
10
GL
FB3
8
9
EN
TSSOP16
IN3, GH Voltage .................................. 0V to 38V
Maximum Junction Temp. (TJ) .............. +125C
Thermal Resistance
(3)
θJA
θJC
QFN16 (3 x 3mm) ................... 60 ...... 12 ... C/W
TSSOP16 ................................ 90 ...... 30 ... C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on approximately 1” square of 1 oz copper.
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2
MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS
ELECTRICAL CHARACTERISTICS (5)
VIN = 5V, TA = +25C, unless otherwise noted.
Parameter
Symbol Condition
Input Voltage Range
IN Undervoltage Lockout Threshold
IN Undervoltage Lockout Hysteresis
VIN
VUVLO
VEN HIGH
Thermal Shutdown
Units
5.5
2.65
V
V
mV
VEN 0.3V
VEN > 2V, VFB1 = 1.4V
EN Rising
0.5
1
μA
1.3
1.6
mA
V
V
mV
μA
1.6
100
1
fSW
DM
1
85
CCT = 10nF
CCT = 10nF
AvEA
GmEA
1.22
–25
VFB1 = VFB3 = 1.25V
VFB2 = 0V
IREF = 50μA
0μA < IREF < 200μA
1.22
VIN = 5V
VIN = 3V
SW On Resistance
SW Current Limit
SW Leakage Current
GL Dropout Voltage (6)
GH Dropout Voltage (6)
GL Leakage Current
GH Leakage Current
2.7
2.25
Max
0.3
Regulator #2 Turn-On/Turn-Off Delay
Error Amplifier
Error Amplifier Voltage Gain
Error Amplifier Transconductance
COMP Maximum Output Current
FB1, FB3 Regulation Voltage
FB2 Regulation Voltage
FB1, FB3 Input Bias Current
FB2 Input Bias Current
Reference (REF)
REF Regulation Voltage
REF Load Regulation
Output Switch (SW)
Typ
100
IN Shutdown Current
IN Quiescent Current
EN Input High Voltage
EN Input Low Voltage
EN Hysteresis
EN Input Bias Current
Oscillator
Switching Frequency
Maximum Duty Cycle
Soft Start Period
IN Rising
Min
ILIM
2.8
VSW = 22V
VGL = –10V, IGL = –20mA
VGH = 20V, IGH = 20mA
VIN2 = –15V, VGL = GND
VIN3 = 25V, VGH = GND
1.4
90
6
3
6
MHz
%
ms
μs
ms
400
1000
±100
1.25
0
±100
±100
V/V
μA/V
μA
V
mV
nA
nA
1.25
1
250
400
3.6
0.5
1.28
+25
1.28
1.2
V
%
1
0.3
1
1
1
mΩ
mΩ
A
μA
V
V
μA
μA
160
C
Notes:
5) Typical values are guaranteed by design, not production tested.
6) Dropout Voltage is the input to output differential at which the circuit ceases to regulate against further reduction in input voltage.
MP1530 Rev. 1.41
5/25/2011
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3
MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS
TYPICAL PERFORMANCE CHARACTERISTICS
Circuit of Figure 3, VIN = 5V, VMAIN = 13V, IMAIN = 200mA, VGL = -8.5V, IGL = 10mA, VGH = 27V,
IGH = 10mA, TA = +25C, unless otherwise noted.
Efficiency vs
Load Current
Step-Up Converter
Load Regulation
(Step-Up Converter Only)
13.005
100
VIN=5V
13.000
80
12.995
VIN=3.3V
VMAIN (V)
EFFICIENCY (%)
90
70
60
50
12.985
12.980
12.975
40
30
12.990
12.970
VMAIN=7.5V
1
10
100
LOAD CURRENT (mA)
1000
12.965
27.05
-8.475
27.03
-8.485
27.01
-8.495
26.99
-8.505
26.97
VGH (V)
VGL (V)
-8.465
-8.525
26.93
26.91
-8.545
26.89
-8.555
26.87
0
10
20
30
IGL (mA)
40
50
26.85
Power-On Sequence
VEN
5V/div.
VMAIN
5V/div.
VGL
10V/div.
0
10
20
30
IGH (mA)
40
50
Power-On Sequence
VCT
1V/div.
VMAIN
5V/div.
VGL
10V/div.
VGH
10V/div.
VGH
10V/div.
10ms/div.
MP1530 Rev. 1.41
5/25/2011
1000
26.95
-8.535
-8.565
10
100
IMAIN (mA)
Positive Linear Regulator
Load Regulation
Negative Linear Regulator
Load Regulation
-8.515
1
10ms/div.
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© 2011 MPS. All Rights Reserved.
4
MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Circuit of Figure 3, VIN = 5V, VMAIN = 13V, IMAIN = 200mA, VGL = -8.5V, IGL = 10mA, VGH = 27V,
IGH = 10mA, TA = +25C, unless otherwise noted.
Load Transient on
VMAIN
Normal Operation
IMAIN = 20mA - 200mA Step
IMAIN
200mA/div.
VSW
5V/div.
VMAIN AC
50mV/div.
VMAIN AC
100mV/div.
IINDUCTOR
0.5A/div.
400ns/div.
Reference Voltage vs
Temperature
Fault Timer
VMAIN Shorted to VIN
1.256
1.254
1.252
VREF (V)
VMAIN
5V/div.
VCT
1V/div.
VGL
10V/div.
1.250
1.248
1.246
1.244
1.242
1.240
VGH
20V/div.
1.238
-50
2ms/div.
0
50
100
TEMPERATURE (°C)
150
Oscillator Frequency vs
Temperature
1.50
FREQUENCY (MHz)
1.47
1.44
1.41
1.38
1.35
1.32
1.29
1.26
-50
MP1530 Rev. 1.41
5/25/2011
0
50
100
TEMPERATURE (°C)
150
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5
MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS
PIN FUNCTIONS
QFN
Pin #
TSSOP
Pin #
1
15
SW
2
16
CT
3
1
4
2
5
3
6
4
7
5
8
6
9
7
10
8
11
9
12
10
13
11
MP1530 Rev. 1.41
5/25/2011
Name Description
RDY
Step-Up Converter Power Switch Node. Connect an inductor between the input source
and SW, and connect a rectifier from SW to the main output to complete the step-up
converter. SW is the drain of the internal 250mΩ N-Channel MOSFET switch.
Timing Capacitor for Power Supply Soft-Start and Power-On Sequencing. A capacitor
from CT to GND controls the soft-start and sequencing turn-on delay periods. See
Power-On Sequencing and Start Up Timing Diagram.
Regulators Not Ready. During startup RDY will be left high. Once the turn-on sequence
is complete, this pin will be pulled low if all FB voltages exceed 80% of their specified
thresholds. After all regulators are turned-on, a fault in any regulator that causes the
respective FB voltage to fall below 80% of its threshold will cause RDY to go high after
approximately 15μs. If the fault persists for more than approximately 6ms (for CCT=10nF),
the entire chip will shut down. See Fault Sensing and Timer.
Step-Up Converter Feedback Input. FB1 is the inverting input of the internal error
FB1 amplifier. Connect a resistive voltage divider from the output of the step-up converter to
FB1 to set the step-up converter output voltage.
Step-Up Converter Compensation Node. COMP is the output of the error amplifier.
COMP Connect a series RC network to compensate the regulation control loop of the step-up
converter.
Internal Power Input. IN supplies the power to the MP1530. Bypass IN to PGND with a
IN
10μF or greater capacitor.
GND Signal Ground.
Reference Output. REF is the 1.25V reference voltage output. Bypass REF to GND with
REF a 0.1μF or greater capacitor. Connect REF to the low-side resistor of the negative linear
regulator feedback string.
Negative Linear Regulator Feedback Input. Connect the FB2 feedback resistor string
FB2 between GL and REF to set the negative linear regulator output voltage. FB2 regulation
threshold is GND.
Positive Linear Regulator Feedback Input. Connect the FB3 feedback resistor string
FB3 between GH and GND to set the positive linear regulator output voltage. FB3 regulation
threshold is 1.25V.
On/Off Control Input. Drive EN high to turn on the MP1530, drive EN low to turn it off. For
automatic startup, connect EN to IN. Once the MP1530 is turned on, it sequences the
EN
outputs on (See Power-On Sequencing). When turned off, all outputs are immediately
disabled.
Negative Linear Regulator Output. GL is the output of the negative linear regulator. GL
GL can supply up to 20mA to the load. Bypass GL to GND with a 1μF or greater, low-ESR,
ceramic capacitor.
Negative Linear Regulator Input. IN2 is the input of the negative linear regulator. Drive
IN2 IN2 with an inverting charge pump powered from SW. IN2 can go as low as -20V. For
QFN package, connect the exposed pad to IN2 pin.
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6
MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS
PIN FUNCTIONS (continued)
QFN
Pin #
TSSOP
Pin #
14
12
15
13
16
14
Pad
MP1530 Rev. 1.41
5/25/2011
Name
Description
Positive Linear Regulator Output. GH is the output of the positive linear regulator. GH
can supply as much as 20mA to the load. Bypass GH to GND with a 1μF or greater,
low-ESR, ceramic capacitor.
Positive Linear Regulator Input. IN3 is the input to the positive linear regulator. Drive
IN3
IN3 with a doubling, tripling, or quadrupling charge pump from SW. IN3 voltage can go
as high as 38V.
Power Ground. PGND is the source of the internal 250mΩ N-Channel MOSFET
PGND
switch. Connect PGND to GND as close to the MP1530 as possible.
Exposed No internal electrical connections. Solder it to the lowest potential (IN2 pin) plane
pad
to reduce thermal resistance.
GH
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7
MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS
BLOCK DIAGRAM
IN
REF
REFERENCE
VREF
+
GM
SW
--
FB1
PULSE-WIDTH
MODULATOR
COMP
OSCILLATOR
0.8VREF
+
--
SOFT-START
FAULT TIMER
&
SEQUENCING
0.2VREF
+
PGND
0.8VREF
+
--
--
VREF
EN
--
CT
FB2
+
+
FB3
IN3
--
IN2
GH
RDY
GL
GND
Figure 1—Functional Block Diagram
MP1530 Rev. 1.41
5/25/2011
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© 2011 MPS. All Rights Reserved.
8
MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS
OPERATION
The MP1530 is a step-up converter with two
integrated linear regulators to power TFT LCD
panels. Typically the linear regulators are
powered from charge-pumps driven from the
switch node (SW). The user can set the positive
charge-pump to be a doubler, tripler, or
quadrupler to achieve the required linear
regulator input voltage for the selected output
voltage. Typically the negative charge-pump is
configured as a 1x inverter.
Step-Up Converter
The step-up, fixed-frequency, 1.4MHz converter
employs a current-mode control architecture
that maximizes loop bandwidth to provide fasttransient responses needed for TFT LCD
drivers. High switching frequency allows for
smaller inductors and capacitors minimizing
board space and thickness.
Linear Regulators
The positive linear regulator (GH) uses a
P-Channel pass element to drop the input
voltage down to the regulated output voltage.
The feedback of the positive linear regulator is
a conventional error amplifier with the
regulation threshold at 1.25V.
The negative linear regulator (GL) uses a
N-Channel pass element to raise the negative
input voltage up to the regulated output voltage.
The feedback threshold for the negative linear
regulator is ground. The resistor string goes
from REF (1.25V) to FB2 and from FB2 to GL to
set the negative output voltage.
The difference between the voltage at IN3 and
the voltage at IN2 is limited to 60V abs. max.
Fault Sensing and Timer
Each of the 3 outputs has an internal
comparator that monitors its respective output
voltage by measuring the voltage at its
respective FB input. When any FB input
indicates that the output voltage is below
approximately 80% of the correct regulation
voltage, the fault timer enables and the RDY
pin goes high.
MP1530 Rev. 1.41
5/25/2011
The fault timer uses the same CT capacitor as
the soft-start sequencer. If any fault persists to
the end of the fault timer (One CT cycle is 6ms
for a 10nF capacitor), all outputs are disabled.
Once the outputs are shut down due to the fault
timer, the MP1530 must be re-enabled by either
cycling EN or by cycling the input power.
If the fault persists for less than the fault timer
period, RDY will be pulled low and the part will
function as though no fault has occurred.
Power-On Sequencing and Soft-Start
The MP1530 automatically sequences its
outputs at startup. When EN goes from low to
high, or if EN is held high and the input voltage
IN rises above the under-voltage lockout
threshold, the outputs turn on in the following
sequence:
1. Step-up Converter
2. Negative Linear Regulator (GL)
3. Positive Linear Regulator (GH)
Each output turns on with a soft-start voltage
ramp. The soft-start ramp period is set by the
timing capacitor connected between CT and
GND. A 10nF capacitor at CT sets the soft-start
ramp period to 6ms. The timing diagram is
shown in Figure 2.
After the MP1530 is enabled, the power-on
reset spans three periods of the CT ramp. First
the step-up converter is powered up with
reference to the CT ramp and allowed one
period of the CT ramp to settle. Next the
negative linear regulator (GL) is soft-started by
ramping REF, which coincides with the CT
ramp, and also allowed one CT ramp period to
settle.
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9
MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS
The positive linear regulator (GH) is then softstarted and allowed to settle in one period of CT
ramp. Nine periods of the CT ramp have
occurred since the chip enabled. If all outputs
are in regulation (>80%), the CT will stop
ramping and be held at ground.
The RDY pin will be pulled down to an active
low. If any output remains below regulation
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