MP1530DM-LF

MP5505A 7V, 4A, High-Efficiency Energy Storage and Management Unit The Future of Analog IC Technology FEATURES DESCRIPTION The MP5505A is a lossless energy storage and management unit targeted at solid-state and hard-disk drive applications. Its highly integrated input current limit and energy storage and release management makes the system solution very compact. The internal input-current-limit block with dv/dt control prevents inrush current during system start-up; the bus voltage start-up slew rate is programmable. Also, it includes a power-on-reset function for hot-swapping. MPS’ patented energy storage and release management control circuit minimizes the storage capacitor requirement. It pumps the input voltage to a higher storage voltage and releases the energy over a hold-up time to the system in the case of an input outage. The storage voltage and the release voltage are both programmable for different system applications. The MP5505A requires a minimal number of readily available, standard, external components and is available in a QFN-20 (3mm x 4mm) package.             Wide 2.7V to 7V Operating Input Range Input Current Limiter with Integrated 50mΩ MOSFET Up to 4.5A Input Current Limit Reverse-Current Protection 6V Bus Clamping Voltage Power-On-Reset Adjustable dv/dt Slew Rate for Bus Voltage Start-Up Internal 30mΩ Disconnect Switch Internal 70mΩ and 60mΩ Power Switches for Energy Storage and Release Management Circuits Thermal Protection EN and Power Good Indicators Available in a QFN-20 (3mm x 4mm) Package APPLICATIONS    Solid-State Drives Hard-Disk Drives Power Back-Up/Battery Hold-Up Supplies All MPS parts are lead-free, halogen free, and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION VSTORAGE Release DC/DCs VSTORAGE =12V, VRELEASE=4.2V R1 105k C2 22μF VB 5VIN SW TVS optional for spike OFF VBO VIN C1 0.1μF D2 ENCH ON EN L1 4.7μH R11 200k FBS R12 14k ILIM PGIN R7 1k TPOR PGS DVDT C3 100nF C4 10nF PGND CST AGND D1 Optional STRG MP5505A ICH R6 200k C6 100nF BST FBB R2 24.3k C5 1μF C7 VB 5V/div VSTORAGE 5V/div VIN 5V/div PGs 5V/div MP5505A Rev. 1.11 www.MonolithicPower.com 5/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 1 MP5505A – ENERGY STORAGE AND MANAGEMENT UNIT ORDERING INFORMATION Part Number* MP5505AGL Package QFN-20 (3mmx4mm) Top Marking See Below * For Tape & Reel, add suffix –Z (e.g. MP5505AGL–Z); TOP MARKING MP: MPS prefix; Y: year code; W: week code: 5505A: first five digits of the part number; LLL: lot number; PACKAGE REFERENCE TOP VIEW VIN VB VBO 20 19 18 DVDT 1 17 ICH TPOR 2 16 FBS ILIM 3 15 FBB PGIN 4 14 AGND PGS 5 13 NC EN 6 12 CST ENCH 7 11 BST 8 9 10 PGND SW STRG QFN-20 (3mmx4mm) MP5505A Rev. 1.11 www.MonolithicPower.com 5/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 2 MP5505A – ENERGY STORAGE AND MANAGEMENT UNIT ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance (4) Supply Voltage VIN ....................................... 8.0V VSTRG................................................ -0.3V to 35V VSW ...................................... -0.3V to VSTRG+0.3V VBST...................................... -0.3V to VSTRG+6.5V VCST ................................................. -0.3V to 40V All Other Pins ............................... –0.3V to 6.5 V Continuous Power Dissipation (TA = +25°C) (2) ............................................................... 2.6W Junction Temperature ............................... 150°C Lead Temperature .................................... 260°C Operating Temperature ............. –40°C to +85°C QFN-20 (3mmx4mm) .............. 48 ....... 10 ... °C/W Recommended Operating Conditions (3) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) The maximum power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-to-ambient thermal resistance θJA, and the ambient temperature TA. The maximum continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation will produce an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB. Supply Voltage VIN ............................. 2.7V to 7V Bus Voltage VB ................................... 2.7V to 6V Storage Voltage VSTRG ........................ VIN to 30V Operating Junction Temp. (TJ). -40°C to +125°C MP5505A Rev. 1.11 www.MonolithicPower.com 5/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 3 MP5505A – ENERGY STORAGE AND MANAGEMENT UNIT ELECTRICAL CHARACTERISTICS VIN = 5.0V, TA = 25°C, unless otherwise noted. Parameter Input-Supply Voltage Range Supply Current (Shutdown) Supply Current (Quiescent) Thermal Shutdown (6) Thermal Shutdown Hysteresis (6) VIN Under-Voltage Lockout Threshold Rising VIN Under-Voltage Lockout Threshold Hysteresis EN/ENCH UVLO Threshold Rising EN/ENCH UVLO Threshold Falling Current-Limit FET ON Resistance Continuous Current Limit Off-State Leakage Current Symbol Max Units 7 2 2 150 V μA mA °C THYS 30 °C INUVR 2.5 2.7 V 0.4 0.5 V 1.2 V VIN IS IQ TSD Typ VEN=0V VEN/ENCH=2V, VFBB/FBS=1V 0.3 ENR 0.4 ENF RDSON (7) ILIM ILEAK VCLAMP Rise Time (dv/dt) τR Internal RESET Delay Time τD Charge Peak Current @ Boost Mode Min 2.7 INUVHYS Clamping Voltage Pre-Charge Current Condition VIN=5V, IB=0.5A 50 65 VIN=3.3V, IB=0.5A RILIM=1.07kΩ RILIM=1.2kΩ RILIM=1.4kΩ VIN=6V, VB=0V or VB=6V, VIN=0V VIN=7V DVDT Pin Floating Cdv/dt=10nF Cdv/dt=100nF TPOR Pin Floating CTPOR=100nF CTPOR=500nF 68 4.6 4.1 3.7 83 -10% +10% 0.5 ICH_PRE ICH V ICH Pin Floating RICH=100kΩ RICH=200kΩ Boost Disconnect Switch Ron Rdison Energy Management HS Ron RHon Energy Management LS Ron RLon Feedback Voltage VFBB, VFBS Feedback Current IFBB VFBB=VFBS=0.79V 0.77 6 0.9 10 100 0.4 100 500 130 500 400 200 30 70 60 0.79 MP5505A Rev. 1.11 www.MonolithicPower.com 5/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. mΩ A 10% 2 μA +10% 1.5 V ms ms mA mA 35 0.81 50 mΩ mΩ mΩ V nA 4 MP5505A – ENERGY STORAGE AND MANAGEMENT UNIT ELECTRICAL CHARACTERISTICS (continued) VIN = 5.0V, TA = 25°C, unless otherwise noted. Parameter Symbol PGS High Threshold PGH_S PGS Low Threshold PGL_S PGS Delay PGD_S PGS Sink-Current Capability VPG_S PGS Leakage Current IPGS_L PGIN High Threshold PGH_IN PGIN Low Threshold PGL_IN PGIN Delay PGD_IN PGIN Sink-Current Capability VPG_IN PGIN Leakage Current IPGIN_L Buck-Mode DumpingIDUMP Current Limit Release-Buck Switching fs_RLS Frequency VB Under-Voltage Lockout INUVBR Threshold, Rising(5) VB Under-Voltage Lockout INUVBHYS Threshold, Hysteresis(5) Condition Min Typ 0.95 0.9 20 Sink 4mA VPGS=3.3V Max 0.3 120 1.03 1 4 Sink 4mA VPGIN=3.3V 0.3 120 Units VFBS VFBS μs V nA VFBB VFBB μs V nA 5 A 500 kHz 1.8 2.2 2.5 V 0.15 0.25 0.35 V Notes: 5) VB UVLO is applied to energy storage and release circuitry. 6) Guaranteed by design. 7) Refer to TPC curve for Current-Limit FET On Resistance value under different temperature and load condition. MP5505A Rev. 1.11 www.MonolithicPower.com 5/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 5 MP5505A – ENERGY STORAGE AND MANAGEMENT UNIT TYPICAL PERFORMANCE CHARACTERISTICS VIN = 5V, VSTORAGE = 12V, VRELEASE=4.2V, L = 4.7µH, TA = 25°C, unless otherwise noted. 100 80 60 40 20 0 100 100 80 80 60 60 40 40 20 20 0 -50 -25 0 25 50 75 100 125 150 0 0 0.5 1 1.5 2 2.5 3 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 3.5 MP5505A Rev. 1.11 www.MonolithicPower.com 5/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 6 MP5505A – ENERGY STORAGE AND MANAGEMENT UNIT TYPICAL PERFORMANCE CHARACTERISTICS (continued) Performance waveforms are tested on the evaluation board of the Design Example section. VIN = 5V, VSTORAGE = 12V, VRELEASE=4.2V, L = 4.7µH, TA = 25°C, unless otherwise noted. VSTORAGE Charge VSTORAGE 5V/div VB 5V/div VSTORAGE Release VB 5V/div VSTORAGE 5V/div VIN 5V/div PGs 5V/div VIN 5V/div PGs 5V/div Release Time Release Time Release Time Pb=5W, C Storage=2200 F Pb=8W, C Storage=2200 F Pb=12W, C Storage=2200 F VB 5V/div VB 5V/div VB 5V/div VSTORAGE 5V/div PGs 5V/div VSTORAGE 5V/div PGs 5V/div VSTORAGE 5V/div PGs 5V/div IB 1A/div IB 2A/div IB 2A/div VB 5V/div Release Time Release Time Release Time Pb=5W, C Storage=1000 F Pb=5W, C Storage=2200 F Pb=5W, C Storage=4400 F VB 5V/div VB 5V/div VSTORAGE 5V/div PGs 5V/div VSTORAGE 5V/div PGs 5V/div VSTORAGE 5V/div PGs 5V/div IB 1A/div IB 1A/div IB 1A/div MP5505A Rev. 1.11 www.MonolithicPower.com 5/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 7 MP5505A – ENERGY STORAGE AND MANAGEMENT UNIT PIN FUNCTIONS QFN-20 (3mm×4mm) Name Description Pin # Slew-Rate Control Pin for VB Voltage during Start-Up. Connect a capacitor from DVDT 1 DVDT to GND to program a different VB charge-up slew rate. Leave DVDT open for the default soft-start time (around 0.9ms from 0V to VIN). Power-On-Reset Delay Time for VB Start-Up. When VIN and EN are ready (after the programmable delay time), VB starts to charge-up. Connect a capacitor between TPOR 2 TPOR and GND to select a different delay time. Leave TPOR open for the default power-onreset delay time (0.4ms). Input-Current-Limit Setting. Connect a resistor between ILIM and GND to adjust the 3 ILIM current limit of the input-current limiter. ILIM CANNOT be left open. VB Power Good Indicator. PGIN is an open-drain output. PGIN goes high if the FBB 4 PGIN voltage exceeds 1.03×VFBB (0.813V, typically). PGIN goes low if the FBB voltage drops below 1.0×VFBB (0.79V). Storage Voltage Power Good Indicator. PGS is an open-drain output. PGS goes high if 5 PGS the FBS voltage exceeds 0.95×VFBS (0.75V). PGS goes low if the FBS voltage drops below 0.9×VFBS (0.71V). ON/OFF Control pin for MP5505A. When EN is pulled low, all functions of MP5505A are 6 EN disabled (for both the input-current limiter and the charge/release circuitry). Make sure EN voltage is high during release. ON/OFF Control Pin for the Charge/Release Circuitry. When ENCH is pulled down, the 7 ENCH release circuitry is disabled. *Note that ENCH needs to be kept high to achieve energy release. 8 PGND Power Ground. Switch Output for the Charge/Release Circuitry. Connect a small inductor between SW 9 SW and VBO. Storage Voltage. Connect the appropriate storage capacitors for energy storage and 10 STRG release operation. Bootstrap Pin for the Charge/Release Circuitry. The internal bi-directional switcher 11 BST requires a bootstrap capacitor (100nF) from BST to SW to supply the high-side switch driver voltage during release. High-Side Switch Driving Voltage Storage. MP5505A supports energy even when 12 CST storage voltage is close to the VB regulated voltage. 13 NC No Connection. 14 AGND IC Signal Ground. 15 FBB Bus-Voltage Feedback Sense. FBB sets the bus-release voltage. 16 FBS Storage-Voltage Feedback Sense. FBS sets the storage voltage. Boost-Mode Current Limit Adjustment. ICH CANNOT be pulled to VCC or pulled to an 17 ICH external voltage source. 18 VBO Internal Boost. The input voltage after passing through the input isolation FET. Internal-Bus Voltage. Requires a 22μF to 47μF ceramic capacitor as close to VB as 19 VB possible. Input-Supply Voltage. The MP5505A operates from an unregulated 2.7V to 7V input. Place a 0.1µF (or larger) ceramic capacitor as close to VIN as possible. A TVS diode at 20 VIN input is necessary if the VIN voltage spike is high. Refer to the “Selecting Input Capacitor and TVS” section for additional details. MP5505A Rev. 1.11 www.MonolithicPower.com 5/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 8 MP5505A – ENERGY STORAGE AND MANAGEMENT UNIT FUNCTIONAL BLOCK DIAGRAM VBO VB SW BST CST VIN STRG HS Drive FBB ICH I LIM FBS T POR dvdt PGIN PGS EN ENCH LS Drive Control for Current Limit &Energy Management Circuit FBS GND Figure 1. Functional Block Diagram MP5505A Rev. 1.11 www.MonolithicPower.com 5/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 9 MP5505A – ENERGY STORAGE AND MANAGEMENT UNIT OPERATION The MP5505A is an energy storage and management unit in a QFN-20 (3mm×4mm) package. It provides a very compact and efficient energy management solution for typical solid-state drive or hard-disk drive applications. MPS patented lossless energy storage and release management circuits use a bi-directional buck/boost converter to achieve optimal energy transfer and provide the most cost-effective energy storage solution. The integrated boost converter raises the energy-storage voltage level. The storage feedback resistor divider sets the storage voltage. If the input shuts down suddenly, the internal buck converter transfers the energy from the storage capacitor to the bus and holds the bus voltage when the system consumes the energy from the storage capacitor. The buck converter can work in 100% duty cycle operation to deplete fully the stored energy. Start-Up When VIN starts-up, the VB bus voltage is charged from 0 to VIN (nearly). The VB rising slew rate is controlled by DVDT capacitance. This function avoids the input-inrush current and provides protection to the whole system. EHCH is used to enable the storage charge and release circuitry. If ENCH is already high before VB finishes the DVDT process, the storage charge circuitry works automatically when VIN is higher than the UVLO (2.5V, typically). The storage charge circuitry operates in two modes: pre-charge mode (where the STRG voltage is charged to the VB voltage using a current source) and boost mode (where the STRG voltage is charged to set the voltage). The pre-charge mode charges the STRG voltage up to the VB voltage using an almost constant current source (around 130mA). When STRG voltage is close to VB and VB voltage is higher than a certain threshold (where the corresponding FBB is higher than 0.813V), boost mode is initiated. Boost mode charges the STRG voltage to the target voltage. Figure 2 shows the charging build-up process when ENCH is high before VB starts up. It is recommended strongly to enable ENCH after VB has settled (see Figure 3). Because release mode is triggered when FBB voltage is lower than 0.79V (although there is a 23mV hysteresis between boost mode and release mode, in some high-current charges boost mode can be programmed by ICH), VB voltage may be pulled back low and accidently enter release mode. In order to avoid this, enable ENCH after VB settles. Figure 3 shows the charging build-up process when ENCH is enabled after VB settles. V IN EN&ENCH VB DVDT Charge-Up FBB=0.813V VB STRG Boost Mode VSTRG STRG Pre-Charge Mode Power-On Delay Time Figure 2. Charging Process VIN EN ENCH VB VB DVDT Charge-Up STRG Boost Mode V STRG STRG Pre-Charge Mode Power-On Delay Time Figure 3. Charging Process when EN and ENCH Are Separated Storage Voltage After the start-up period, the internal boost converter regulates automatically the storage voltage to a set value. The MP5505A uses burst mode to minimize the converter’s power loss. When the storage voltage drops below the set voltage, burst mode initiates and charges MP5505A Rev. 1.11 www.MonolithicPower.com 5/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 10 MP5505A – ENERGY STORAGE AND MANAGEMENT UNIT the storage capacitor. During the burst period, the current limit and the low-side MOSFET (LSFET) control the switch. When the LS-FET turns on, the inductor current increases until it reaches its current limit. The boost-current limit can be programmed by an ICH resistor. By floating ICH, the boost-current limit is around 500mA. After hitting the current limit, the LSFET turns off for the set minimum off-time. At the end of this minimum off-time, if the feedback voltage remains below the 0.79V internal reference, the LS-FET turns on again; otherwise the MP5505A waits until the voltage drops below the threshold before turning on the LS-FET. Release The MP5505A monitors continuously the input and bus voltages. Once the bus voltage drops below the selected release voltage (such as when losing input power), the internal boost converter stops charging and works in buckrelease mode. In buck mode, the part transfers energy from the high-voltage storage capacitor to the low-voltage bus capacitor. Determine the release voltage by selecting resistor values for the bus resistor divider. VSTRG The input-current limiter controls carefully the input-inrush current of the internal hot-swap MOSFET to prevent an inrush current from the input to the bus. A capacitor connected to dv/dt sets the soft-start time. Despite the soft-start process, ILIM can limit the steady-state current. Connect a resistor between ILIM and GND to set the current limit. Reverse-Current Protection The hot-swapping circuit uses reverse-current protection to prevent the storage energy from transferring back to the input when energy is released from the storage capacitors to bus. The hot-swap MOSFET turns on when the input voltage exceeds the VIN UVLO threshold during start-up (or when input voltage is about 0.2V higher than VB voltage). The hot-swap MOSFET turns off when input voltage falls below the bus voltage during release (or input falls below the PGIN threshold). Start-Up Sequencing Connect a capacitor across DVDT to program the soft-start time; during soft-start, the energy storage capacitors will charge. Very short dv/dt times can trigger the current-limit threshold. Select the DVDT capacitor based on the storage capacity. Storage Power-Good Indicator (PGS) VB PGIN Input-Current Limit Release VB Regulation Voltage When the voltage on FBS (storage feedback) drops below 0.9×VFBS, the MP5505A pulls PGS low internally. When the FBS voltage is above 0.95×VFBS, PGS goes high. Bus Power-Good Indicator (PGIN) Figure 4. Release Times The released buck applies the fixed-frequency constant-on-time (COT) control and enables the fast transition between the charge and release modes. The buck converter works at 100% duty cycle until the storage-capacitor voltage approaches the bus voltage. Then the storage and bus voltages drop until they reach the DCDC converter’s UVLO (see Figure 4). When the voltage on FBB (bus feedback) falls below 1.0×VFBB, the MP5505A pulls PGIN low to indicate the releasing status. When MP5505A works in boost mode, PGIN is pulled high to indicate the charging status. MP5505A Rev. 1.11 www.MonolithicPower.com 5/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 11 MP5505A – ENERGY STORAGE AND MANAGEMENT UNIT APPLICATION INFORMATION Selecting Input Capacitor and TVS Capacitors at VIN are recommended to absorb possible voltage spikes during input-power turn on, input-switch hard off (during power off), or other special conditions. The application determines the capacitor. For example, if the input-power trace is too long (with higher parasitic inductance) during the input-switch hard-off period, more energy pumps into the input. This means more input capacitors are needed to ensure the input voltage spike stays in a safe range. Use a 0.1uF (or larger) capacitor based on the spike condition. Keep inrush-current requirements in mind when selecting an input capacitor. Typically, more input capacitors result in a higher input-inrush current during hot-plugging. A smaller input capacitor is needed for a smaller inrush current. MP5505A works normally with a very small input capacitor. However, this leads to a possible high-voltage spike. An efficient solution is to add a TVS diode at the input to absorb the possible input-voltage spike. At the same time, keep the inrush current small during hot-plugging. A typical TVS diode, like SMA6J5.0A, is recommended. Setting the Storage Voltage Set the storage voltage by choosing the external feedback resistors R11 and R12 shown in Figure 5. R11  14k  (VSTORAGE  VFBS ) VFBS For a 12V storage voltage, R11 is 200kΩ. Table 1 lists the recommended resistors for different storage voltages. Table 1. Resistor Pairs for VSTORAGE R11 (kΩ) R12 (kΩ) VSTORAGE(V) 8 127 14 12 200 14 20 340 14 Select Release Voltage and VBus Capacitors Select the release voltage by choosing the external feedback resistors R1 and R2 (see Figure 6). Similarly, the release voltage is: VR ELEASE  (1  R1 )  VFBB R2 VFBB is 0.79V, typically. However, R1 and R2 not only determine the release voltage, but also affect stability. Since the release-buck mode works in COT mode, avoid small resistor values to ensure a sufficient voltage ramp. Generally, choose R1//R2≥20kΩ for stable performance with CB=22μF. Table 2 lists the recommended resistor values for different release voltages. VB STRG R1 R11 FBS FBB CB Cstorage R2 R12 Figure 6. Release Feedback Circuit Figure 5. Storage Feedback Circuit The storage voltage is determined by: VSTORAGE  (1  R11 )  VFBS R12 Where VFBS is 0.79V, typically. R11 and R12 are not critical for normal operation. Select R11 and R12 higher than 10kΩ to account for the bleed current. For example, if R12 is 14kΩ, R11 is then: Table 2. Resistor Pairs for VRELEASE VRELEASE (V) R1 (kΩ) R2 (kΩ) 4.2 105 24.3 2.9 107 40.2 Selecting the Storage Capacitor The storage capacitor stores energy during normal operation and releases this energy to VB MP5505A Rev. 1.11 www.MonolithicPower.com 5/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 12 MP5505A – ENERGY STORAGE AND MANAGEMENT UNIT when VIN loses input power. Use a generalpurpose electrolytic capacitor or low-profile POS capacitor for most applications. One 4.7uF ceramic capacitor is recommended if the electrolytic capacitor ESR is high. Select a storage capacitor with a voltage rating that exceeds the targeted storage voltage. Consider the capacitance reduction with the DC voltage offset when choosing the capacitors. Different capacitors have a different capacitance de-rating performance. Choose a capacitor with enough voltage rating to guarantee enough capacitance. The required capacitance depends on the length of the “dying gasp” for a typical application. Assume the release current is IRELEASE when VB voltage is regulated at VRELEASE for the DC-DC converter, the storage is VSTORAGE, and the required dying gasp time is τDASP. The required storage capacitance is then: CS  2  VRELEASE  IRELEASE  DASP 2 2 VSTORAGE  VRELEASE the recommended resistors for different current limit values. Table 3. ILIM vs. RLIM RLIM (kΩ) ILIM(A) 4.6 1.07 4.1 1.2 3.7 1.4 1.6 3.2 Input Hot-swap Voltage Drop MP5505A integrates one back-to-back MOSFET between VIN and VB for current limit and reverse current blocking. The voltage drop on this FET may affect application when VIN voltage is low. One load switch such as MP5090 is suggested to place in parallel with MP5005A input hot-swap MOSFET, as Figure 7 block diagram. In this application, OUT1 and OUT2 of MP5090 must be connected together without capacitor to GND. PGB of MP5505A will enable MP5090 and provide much lower resistance between VIN and VB power, while providing reverse current block at the same time. Consider the power loss during release; the buck converter can run up to 90% efficiency in most applications. Select storage capacitance at 1.1xCs to ensure enough releasing time. If IRELEASE=1A, τDASP=20ms, VSTORAGE=12V, and VRELEASE=4.2V, then the required storage capacitance is 1500μF. For typical applications using a 5V input supply, set the storage voltage above 10V to utilize fully the high-voltage energy and minimize the storage capacitance requirements. Generally, use the 16V POS capacitor or 25V electrolytic capacitors. Selecting the External Diode An external diode parallel with the high-side power MOSFET (HS-FET) is optional for normal charge mode operation. This diode improves the boost efficiency if the boost peak current is high. The voltage rating should be higher than the storage voltage, and the current rating should be higher than the current programmed by ICH. Setting the Input Hot-Swap Current Limit Connect a resistor from ILIM to GND to set the current-limit value. For example, a 1.2kΩ resistor sets the current limit to about 4.1A. Table 3 lists Figure 7．MP5505A parallel with MP5090 Selecting the Inductor The inductor is necessary to supply constant current to the load. Since boost mode and buck mode share the same inductor, and generally the buck mode current is higher, an inductor that at least supports the buck mode releasing current is recommended. Select the inductor based on the buck-release mode. If the storage voltage is VS, then the release voltage is VR and the buck running is fixed at a 500kHz frequency. The inductance value can be calculated by: L VR V  (1  R ) IL  FSW VS MP5505A Rev. 1.11 www.MonolithicPower.com 5/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 13 MP5505A – ENERGY STORAGE AND MANAGEMENT UNIT Where ∆IL is the peak-to-peak inductor-ripple current (which can be set in the range of 30% to 40% of the full releasing current). The inductor should not saturate under the maximum inductor peak current. Setting the Power-On Reset Delay Time Connect a capacitor to TPOR to set the poweron-reset delay time. Leave TPOR floating for the default delay time (around 0.4ms). Table 4 lists the recommended capacitors for different delay times. In order to eliminate the power-on-reset delay, connect TPOR directly to VIN. Table 4. Reset Delay vs. Capacitor Value CTPOR (nF) τD (mS) 100 100 500 500 Setting the Bus Voltage Rise Time Connect a capacitor to the DVDT to set the bus voltage start-up slew rate and soft-start time. Leave DVDT floating for the default soft-start time (around 0.9ms from 0V to 5V). Table 5 lists the recommended capacitors for different softstart times at a 5V input condition. Table 5. Soft-Start vs. Capacitor Value Cdv/dt (nF) τR (mS) 10 10 100 100 PCB Layout 1) Use short, wide, and direct traces in the high-current paths (VIN, VB, VBO, SW, STRG, and GND). 2) Place the decoupling capacitor across VB and GND as close as possible. 3) Place the decoupling capacitor across STRG and GND as close as possible. 4) Keep the switching node SW short and away from the feedback network. 5) Place the external feedback resistors next to the FB pins. 6) Keep the BST voltage path (BST, C6, R10, and SW) as short as possible. A 4-layered layout is recommended to achieve better thermal performance and simplify layout. Schematic for Layout MP5505A Rev. 1.11 www.MonolithicPower.com 5/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 14 MP5505A – ENERGY STORAGE AND MANAGEMENT UNIT Please use the following figures as a sample layout (with four layers). Inner Layer 2: Top Layer: Bottom Layer: Inner Layer 1: Figure 8. Layout Recommendation MP5505A Rev. 1.11 www.MonolithicPower.com 5/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 15 MP5505A – ENERGY STORAGE AND MANAGEMENT UNIT Design Example Table 6 below is a design example following the application guidelines for the specifications: Table 6. Design Example Parameter Symbol Input Voltage VIN Charge Voltage VSTRG Regulated-Bus VRLS Voltage at Pfail Boost Mode Max ICHARGE Charge Current Buck Mode Max Output Current at IRELEASE Pfail Value 5 12 Units V V 4.2 V 0.5 A 3 A The detailed application schematic is shown in Figure 9. The typical performance and circuit waveforms have been shown in the “Typical Performance Characteristics” section on page 6. For more device applications, please refer to the related evaluation board datasheets. Figure 9. Detailed Application Schematic MP5505A Rev. 1.11 www.MonolithicPower.com 5/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 16 MP5505A – ENERGY STORAGE AND MANAGEMENT UNIT PACKAGE INFORMATION QFN-20 (3mmx4mm) MP5505A Rev. 1.11 www.MonolithicPower.com 5/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 17 MP5505A – ENERGY STORAGE AND MANAGEMENT UNIT Revision History Revision # Revision Date 1.11 05/15/2020 Description Pages Updated The units of ‘PGIN high threshold’ and ‘PGIN low threshold’ in EC table on page 5 are changed from VFBS to VFBB . NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP5505A Rev. 1.11 www.MonolithicPower.com 5/19/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. 18