MP2953B
Digital Multi-Phase Controller
with PMBus Interface for VR12.5
DESCRIPTION
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The Future of Analog IC Technology
FEATURES
The MP2953B is a digital multi-phase controller
that provides power for the core of the INTEL
VR12.5 platform. It works with MPS’ IntelliPhase products to complete the multi-phase VR
solution with minimal external components. It
can be configured for 1 ~ 6 phase operation.
The MP2953B provides on-chip EEPROM to
store and restore device configurations. Device
configurations and fault parameters are easy to
program or monitor using the PMBus interface.
The MP2953B monitors and reports the output
current through CS output from Intelli-Phase
products.
N
6-Phase Digital PWM Controller
Intel’s VR12.5 Compliant
PMBus Compliant
Serial VID Interface for Programming and
Monitoring
Pin Programmable SVID registers
Built-In EEPROM to Store Custom
Configurations
Automatic Loop Compensation
Less
External
Components
than
Conventional Analog Controllers
Phase-Shedding at Light Load to Provide
High Efficiency
Phase-to-Phase Active Current Balancing
Input and Output Voltage, Current, and
Power Monitoring
Regulator Temperature Monitoring
Open-Drain FAULT# Signal for Fault
Notification
RVP/OVP/UVP/OCP/OTP/UVLO Protection
with Options of No Action, Latch, Retry, or
Hiccup
Adjustable Load-Line Regulation
RoHS Compliant 5mmx5mm QFN-40
APPLICATIONS
Server Core Voltage
Graphic Card Core Regulators
Telecom and Networking Systems
Base Stations
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are
trademarks of Monolithic Power Systems, Inc. or its subsidiaries.
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The MP2953B is based on a unique digital
multi-phase, non-linear control to provide fast
transient response to load transient with
minimal output capacitors. With only one power
loop control method for both steady state and
load transient, the power loop compensation is
easily configured.
MP2953B Rev. 1.02
www.MonolithicPower.com
11/11/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
1
MP2953B – DIGITAL PWM CONTROLLER WITH PMBUS FOR VR12.5
TYPICAL APPLICATION
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VIN=12V
+5V
PMBus
KIT
VDD
VIN
BST
EN
IntelliTEMP Phase
PWM
CS
VTT = 1.05V
VDD33
ALT#
VRRDY
VRRDY
PROCHOT#
AGND
VOSEN
EN
VRFLT#
IREF
IMON
VDD33
PGND
VORTN
VRHOT#
EN
VINSEN
DGND
VDD50
VDD33
VDDHC18
SCL_P
SDIO
ALERT#
SDA_P
SCLK
SDIO
ALT_P#
SCLK
FB
MP2953B
6- Phase VR12.5
Digital Controller
VDIFF
CS1
CS2
CS3
CS4
VFS
PGND
VOUT
LOAD
AGND
CPU
SW
SYNC
VDD
VIN
BST
EN
IntelliTEMP Phase
PWM
CS
SW
SYNC
PGND
AGND
CS5
CS6
ADDR_S
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
TEMP
VBOOT
CCM
ADDR_P
CS_SUM
VDD
VIN
BST
EN
IntelliTEMP Phase
PWM
CS
SW
SYNC
O
AGND
VDD
VIN
BST
EN
IntelliTEMP Phase
PWM
CS
EC
SW
SYNC
AGND
PGND
VDD
VIN
BST
EN
IntelliTEMP Phase
PWM
CS
N
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SW
SYNC
AGND
PGND
VDD
VIN
BST
EN
IntelliTEMP Phase
PWM
R
N
PGND
CS
SW
SYNC
AGND
PGND
Figure a: 6 Phase application
MP2953B Rev. 1.02
www.MonolithicPower.com
11/11/2019
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© 2019 MPS. All Rights Reserved.
2
AGND
VINSEN
DGND
VDD50
PWM1
PWM3
PWM2
VDD33
VDDHC18
PWM4
SCL_P
SDA_P
N
Figure b: 4 Phase application
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PWM5
PWM6
TEMP
CCM
ALT_P#
LOAD
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MP2953B – DIGITAL PWM CONTROLLER WITH PMBUS FOR VR12.5
MP2953B Rev. 1.02
www.MonolithicPower.com
11/11/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
3
MP2953B – DIGITAL PWM CONTROLLER WITH PMBUS FOR VR12.5
ORDERING INFORMATION
(*)
PACKAGE
QFN-40 (5mmx5mm)
Top Marking
See Below
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Part Number
MP2953BGU-xxxx(**)
* For Tape & Reel, add suffix (e.g. MP2953BGU-xxxx(**)-Z).
**: “xxxx” is the configuration code identifier for the register settings stored in the EEPROM. For the default case,
the number will be “0000.” Each “x” could have a hexadecimal value between 0 & F. Please work with the MPS
FAE to create this unique number even if ordering the “0000” code.
TOP MARKING
MPS: MPS Prefix
YY: Year Code
WW: Week Code
MP2953B: Part Number
LLLLLLL: Lot Number
CS6
EN
VDD33
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
CCM
40
39
38
37
36
35
34
33
32
31
1
30
SCL_P
CS4
2
29
SDA_P
CS3
3
28
ALT_P#
CS2
4
27
DGND
CS1
5
26
VRRDY
N
CS5
AGND
SDIO
CS_SUM
10
21
SCLK
VBOOT
11
12
13
14
15
16
17
18
19
20
VDD50
ALT#
22
VDD18
23
9
IREF
8
VORTN
ADDR_S
VOSEN
VINSEN
VRFLT#
ADDR_P
VRHOT#
24
VFS
25
7
IMON
6
VFB
TEMP
VDIFF
R
N
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EC
PACKAGE REFERENCE
MP2953B Rev. 1.02
www.MonolithicPower.com
11/11/2019
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© 2019 MPS. All Rights Reserved.
4
MP2953B – DIGITAL PWM CONTROLLER WITH PMBUS FOR VR12.5
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance (4)
VDD50.......................................–0.3V to +6.5 V
VDD18.......................................–0.3V to +2.0 V
CS1 to CS6, PWM1 to PWM6, FB, VDIFF,
VOSEN, VORTN, SCL_P, SDA_P, ALT_P#,
CCM, EN, VDD33......................–0.3V to +3.6 V
All Other Pins.............................–0.3V to +1.8 V
Continuous Power Dissipation (TA = +25°C) (2)
………………………………………..…… ..3.4 W
Junction Temperature...............................150oC
Lead Temperature ....................................260oC
Storage Temperature.............. –65oC to +150oC
QFN-40 (5mmx5mm) .............. 36 ........ 5 .... C/W
θJC
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θJA
Recommended Operating Conditions (3)
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VDD50......................................................... +5V
Operating Junction Temp. (TJ). -10°C to +125°C
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 6-layer PCB.
MP2953B Rev. 1.02
www.MonolithicPower.com
11/11/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
5
MP2953B – DIGITAL PWM CONTROLLER WITH PMBUS FOR VR12.5
ELECTRICAL CHARACTERISTICS
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VDD50 = 5 V, EN = 1V, VID = 0.50 V to 2.6 V, Current going into pin is positive, TJ =-10°C to 125°C,
unless otherwise noted.
Parameter
Symbol
REMOTE SENSE AMPLIFIER
Bandwidth(5)
VORTN Current
VOSEN Current
OSCILLATOR
Min
Typ
Max
Units
GBW(RSA)
20
IRTN
-70
-400
μA
IVOSEN
70
400
μA
fOSC
Frequency
Condition
IREF=1.23V; RIREF=61.9kΩ
MHz
1.56
MHz
SYSTEM INTERFACE CONTROL INPUTS
EN
Input Low Voltage
0.4
VIL(EN)
Input High Voltage
VIH(EN)
Enable High Leakage
Enable Delay
IIH(EN)
TA
0.8
V
V
EN=2V
3.6
µA
EN High to SVID Ready
2
5
ms
IVRHOT# = 20mA, TA = 25°C
8
12
Ω
3
µA
THERMAL THROTTLING CONTROL
VRHOT# Low Output
Impedance
VRHOT# High Leakage
Current
EC
IMON OUTPUT
VRHOT = 1.8V
Current Gain Accuracy
IMON/ICS_SUM
-3
Measured from ICS_SUM to
IMON, ICS_SUM =1.2mA
1:32
A/A
10
ns
COMPARATOR (VFB & VREF)
R
Propagation Delay(5)
tPD
Common-Mode Range
0
2.6
V
N
T
COMPARATOR (VFB & VREF-20mV)
tPD
10
Common-Mode Range
0
ns
2.6
V
COMPARATOR (Protection)
Under-Voltage
Threshold
VDIFF (UV)
R
N
O
Propagation Delay(5)
Over-Voltage Threshold
VDIFF (OV)
Relative to Reference DAC
Voltage
−300
mV
Relative to Reference DAC
Voltage
300
mV
Relative to Protection DAC
Voltage
400
mV
MP2953B Rev. 1.02
www.MonolithicPower.com
11/11/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
6
MP2953B – DIGITAL PWM CONTROLLER WITH PMBUS FOR VR12.5
ELECTRICAL CHARACTERISTICS (continued)
Parameter
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VDD50 = 5 V, EN = 1V, VID = 0.50 V to 2.6 V, Current going into pin is positive, TJ =-10°C to 125°C,
unless otherwise noted.
Symbol
Reverse Voltage
Detection Threshold(5)
CCM OUTPUT
Output Low Voltage
Output High Voltage
PWM OUTPUTS
Output Low Voltage
Output High Voltage
Rise and Fall Time(5)
Max
Units
mV
Relative to RTN, VDIFF is
Rising
30
mV
VOL
ICCM(SINK) = 400 µA
10
VOH
ICCM(SOURCE) = -400 µA
VOSEN (RV)
VOL (PWM)
IPWM(SINK) = 400 µA
VOH (PWM)
IPWM(SOURCE) = -400 µA
3
PWM = 1.5V; EN = 0V
VDD50
EC
IVDD50
mV
V
200
mV
VDD330.02
V
10
ns
-1
4.5
EN=High. Both the SVID
Bus and the Internal ID Bus
are Idle. No-Load Condition.
6-Phase Configuration.
VDD330.02
10
3.15
500
5
1
µA
5.5
V
16
mA
UVLO Threshold Voltage
VDDUVLO
VDD50 is Rising
4.13
Hysteresis(5)
VDDUVLO
VDD50 is Falling
180
mV
IVDD18 = 0mA
1.8
V
VOL = VDD18 - 40mV
30
mA
IVDD33 = 0mA
3.3
V
VOL = VDD33 - 40mV
30
mA
UVLO
1.8V REGULATOR
R
1.8V Regulator Output
Voltage
VDD18
IVDD18
N
T
1.8V Regulator Load
Capability
3.3V REGULATOR
O
3.3V Regulator Output
Voltage
3.3V Regulator Load
Capability
VDD33
IVDD33
4.5
V
R
N
Typ
0
C = 10pF
Supply Voltage Range
Supply Current
Min
Relative to RTN, VDIFF is
Falling
PWM Tri-State Leakage
SUPPLY
Condition
MP2953B Rev. 1.02
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11/11/2019
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© 2019 MPS. All Rights Reserved.
7
MP2953B – DIGITAL PWM CONTROLLER WITH PMBUS FOR VR12.5
ELECTRICAL CHARACTERISTICS (continued)
Parameter
SVID Interface(5)
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VDD50 = 5 V, EN = 1V, VID = 0.50 V to 2.6 V, Current going into pin is positive, TJ =-10°C to 125°C,
unless otherwise noted.
Symbol
Condition
VIL
VIH
Vhyst
Logic Low
Logic High
Hysteresis
CPU Interface Voltage
(SDIO, SCLK)
Range
Max
Units
0.45
V
V
mV
TBD
Ω
10
μA
CPAD
4
pF
CPIN
5
pF
4
5
Ω
Transient Voltage including
Ringing
-0.3
2.1
V
2nH, 4pF Load
0.5
2
V/ns
8.3
7
14
ns
ns
ns
2.88
V
10
mV
100
mV/μs
350
mV
8
bit
0.97~3.54
V
10
mV
RPU
IL
0V to VTT
RON
VMAX
Resolution per LSB
50
55
-10
4
Output Voltage Slew Rate(5)
R
Typ
0.65
50
EC
Termination Resistance
(SDIO, SCLK, ALT#)(5)
Leakage Current
(SDIO, SCLK, ALT#)
Pad Capacitance
(SDIO, SCLK, ALT#)
Pin Capacitance
(SDIO, SCLK, ALT#)(5)
Buffer On Resistance
(SDIO, SCLK, ALT#)(5)
Maximum voltage
(SDIO, SCLK, ALT#)
Slew Rate
(SDIO, SCLK, ALT#)(5)
VR Clock to Data Delay(5)
Setup Time
Hold Time
DAC (Reference Voltage)
Min
N
O
Resolution
DAC (Protection)
Range
Resolution
Adjustable via the PMBus
R
T
Range
N
DAC (Vout Calibration)
MP2953B Rev. 1.02
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11/11/2019
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© 2019 MPS. All Rights Reserved.
8
MP2953B – DIGITAL PWM CONTROLLER WITH PMBUS FOR VR12.5
ELECTRICAL CHARACTERISTICS (continued)
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VDD50 = 5 V, EN = 1V, VID = 0.50 V to 2.6 V, Current going into pin is positive, TJ =-10°C to 125°C,
unless otherwise noted.
N
Min
Typ
Max
10.2
V
9
V
150
oC
30
oC
2.4
-10
-0.3
Units
3.3
10
0.8
10
400
V
V
μA
mV
3.6
V
10
pF
400
kHz
4.7
μs
4.0
μs
4.7
μs
4.0
300
250
25
4.7
4.0
μs
ns
ns
ms
μs
μs
μs
μs
35
50
300
1000
Notes:
5)
Guaranteed by design or characterization data, not tested in production.
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Parameter
Symbol Condition
Power Management Features
VIN UVLO Turn-On
Adjustable via the PMBus
Threshold
VIN UVLO Turn-Off
Adjustable via the PMBus
Threshold
Thermal Protection
DBh = 961Eh
Threshold
Thermal Protection
DBh = 961Eh
Hysteresis
PMBus DC Characteristics (ALT_P, SDA_P, SCL_P)
Input High Voltage
VIH
SCL_P, SDA_P
Input Low Voltage
VIL
SCL_P, SDA_P
Input Leakage Current
SCL_P, SDA_P, ALT_P
Output Low Voltage
VOL
ALT_P Sinks 2mA
Transient Voltage including
Maximum Voltage
VMAX
Ringing
Pin Capacitance(5)
CPIN
PMBus Timing characteristics(5)
Operating Frequency Range
Period between Stop and Start
Bus Free Time
Condition
Holding Time
Repeated Start Condition
Setup Time
Stop Condition Setup Time
Data Hold Time
Data Setup Time
Clock Low Time Out
Clock Low Period
Clock High Period
Clock/Data Fall Time
Clock/Data Rise Time
MP2953B Rev. 1.02
www.MonolithicPower.com
11/11/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
9
MP2953B – DIGITAL PWM CONTROLLER WITH PMBUS FOR VR12.5
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TYPICAL PERFORMANCE CHARACTERISTICS
MP2953B Rev. 1.02
www.MonolithicPower.com
11/11/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
10
MP2953B – DIGITAL PWM CONTROLLER WITH PMBUS FOR VR12.5
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VOUT
700mV/div.
VTEMP
300mV/div.
VCS
1V/div.
VPWM
2V/div.
N
R
N
O
T
R
EC
VOUT
500mV/div.
VCS1
600mV/div.
VPWM1
3V/div.
VPWM2
3V/div.
MP2953B Rev. 1.02
www.MonolithicPower.com
11/11/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
11
MP2953B – DIGITAL PWM CONTROLLER WITH PMBUS FOR VR12.5
PIN FUNCTIONS
1
2
3
4
5
6
CS5
CS4
CS3
CS2
CS1
VDIFF
7
FB
8
VOSEN
9
VORTN
10
CS_SUM
11
VBOOT
12
IMON
13
TEMP
15
I
I
I/O
I/O
I
I/O
VINSEN
ADDR_P
ADDR_S
IREF
I
20
VDD50
21
SCLK
22
SDIO
ALT#
I/O
I/O
I
N
O
T
VDD18
N
Phase 5 Current Sense Input. Connect CS of the unused phase to CS_SUM pin.
Phase 4 Current Sense Input. Connect CS of the unused phase to CS_SUM pin.
Phase 3 Current Sense Input. Connect CS of the unused phase to CS_SUM pin.
Phase 2 Current Sense Input. Connect CS of the unused phase to CS_SUM pin.
Phase 1 Current Sense Input.
Differential Remote Sense Amplifier Output.
Feedback. FB sources a current proportional to the sensed output current
(Idroop). This current flows through the resistor between FB and VDIFF to create a
voltage drop proportional to the load current. Ensure the resistor between VDIFF
and FB has a value that will set a proper load line.
Positive Remote Voltage Sense Input. VOSEN is connected directly to the VR
output voltage at the load and should be routed differentially with VORTN.
Remote Voltage Sensing Return Input. VORTN is connected directly to ground
at the load and should be routed differentially with VOSEN.
Total Phase Current, which Monitors AVP. Connect the active phase CS signal
to CS_SUM through current-sense resistors.
Boot Voltage Setting.
Analog Total Load Current Signal. IMON sources a current proportional to the
sensed total load current from CS_SUM. Connect an external resistor from IMON
to GND to program the gain.
Analog Signal from the VR to the VID Controller to Indicate the Power Stage
Temperature. The MP2953B only supports temperature sensing from IntelliPhase. Connect all of Intelli-Phase’s VTEMP pins together to produce the
maximum junction temperature and then connect to TEMP.
Switching Frequency Setting.
Input Voltage Sensing. Connect VINSEN to the system input voltage through a
resistor divider.
PMBus Address Setting.
SVID Address Setting.
Internal Bias Current. Connect an 61.9kΩ resistor from IREF to GND.
1.8V LDO Output for Current Sense. Connect a 1µF bypass capacitor to digital
ground.
5V Analog Power Supply. Connect a 10µF bypass capacitor to digital ground.
Source Synchronous Clock from the CPU. Frequency range from 10MHz to
26MHz.
Data Signal between the CPU and VID Controller.
Alert. ALT# is an open-drain output. It is the alert signal from the VID controller to
the CPU.
I
VFS
19
23
I
I
I
I
I
O
I/O
R
16
17
18
Description
O
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I
I/O
R
14
I/O
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Name
EC
Pin #
O
MP2953B Rev. 1.02
www.MonolithicPower.com
11/11/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
12
MP2953B – DIGITAL PWM CONTROLLER WITH PMBUS FOR VR12.5
PIN FUNCTIONS
Name
24
VRFLT#
25
VRHOT#
26
VRRDY
27
28
DGND
ALT_P#
29
30
SDA_P
SCL_P
31
CCM
32
33
34
35
36
37
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
38
VDD33
40
O
Open-Drain Output that Asserts Low when a Warning has Occurred.
I/O
I
Data Signal between the PMBus Controller and the VID Controller.
Source Synchronous Clock from the PMBus Controller.
Forced CCM Operations Enable. CCM stays high in power state 0 and 1. It pulls
low actively during PS2/3 to enable DCM operation.
O
O
O
O
O
O
O
O
O
Tri-State Logic-Level PWM Outputs. Each output is connected to the input of
Intelli-Phase’s PWM pin.
The logic levels are 0V for low logic and 3.3V for high logic.
The output is set to tri-state (High-Z) to shut down both the high-side MOSFET
and the low-side MOSFET of Intelli-Phase.
3.3V LDO Output for the Internal Digital Power Supply. Connect a 1µF bypass
capacitor to digital ground.
Enable Control for the Controller.
Phase 6 Current Sense Inputs. Connect CS of the unused phase to CS_SUM
pin.
EN
I
CS6
AGND
I
I/O
Analog Ground.
R
N
T
O
N
I/O
VR Fault. VRFLT# is an open-drain output. When Vin or Vout OVP occurs,
VRFLT# is asserted to shut down the input power supply.
Voltage Regulator Thermal Throttling Logic Output. VRHOT# is an open-drain
output. VRHOT# pulls low actively if the monitored temperature exceeds the
programmed VRHOT# temperature threshold.
VR Ready Output. VRRDY is an open-drain output that signals when the output
voltage is outside of the proper operating range. A VTT rail is expected for pull
up; however, some systems may pull up to a maximum voltage of 3.3V with an
external pull-up circuit.
Digital Ground.
O
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PAD
Description
EC
39
I/O
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Pin #
MP2953B Rev. 1.02
www.MonolithicPower.com
11/11/2019
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© 2019 MPS. All Rights Reserved.
13
MP2953B – DIGITAL PWM CONTROLLER WITH PMBUS FOR VR12.5
OPERATION
PMBus interface, SVID interface, and EEPROM
for custom configuration.
Fault protection features include under-voltage
lockout (Vin-UVLO), over-current protection
(OCP), over-voltage protection (OVP), undervoltage protection (UVP), over-temperature
protection
(OTP),
and
reverse-voltage
protection (RVP).
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The MP2953B is a digital multi-phase VR12.5
compliant controller for Intel microprocessors. It
operates in 1-, 2-, 3-, 4-, 5-, or 6-phase. It
contains blocks of precision DAC and ADC,
differential remote voltage sense amplifier, fast
comparators, current sense amplifiers, internal
loop
compensation,
load-line
setting,
VR_Ready monitor, temperature monitor,
VDD50
VDD33
AGND
VDD18
DGND
EN
Power Vcc
& Oscillator
SCL_P
PMBus Interface
& Register
SDA_P
ALT_P#
SDIO
Idroop
CS_SUM
SVID Interface
& Register
ALT#
VRRDY
IREF
1:8
MEMORY
(EEPROM)
SCLK
VRHOT#
1.23V
1:32
IMON
VFB
CM
VID-20mV
ADDR_S
vr_settle
ADDR_P
VRFLT#
VBOOT
DAC
CS1
CS2
CS3
VFS
CM
OC1
CM
OC2
CM
OC3
CM
OC4
CM
OC5
CM
OC6
EC
CS4
OCP_LIM
CS5
CS6
DAC
R
CM
VDIFF
TEMP
Sensing
& Monitor
CS3
Protection &
FAULT Monitor
CS4
CS5
OVP_LIM
CS6
OV1
VID+300mV
CM
Current Balancing
& Vout DC Calibration
OV2
N
T
O
CM
UV
DAC
Idroop
Vdc_trim
VFB
RV
FB
ΣADC
PWM Generator
& Phase Interleaving
& Power State
VDIFF
VID
VOSEN
R
N
CM
30mV
CS1
MUX
CS2
VID-300mV
VOSEN
VINSEN
ADC
x1
DAC
Reference Generator &
Internal Loop Compensation
DAC
VORTN
Vac_trim
CCM
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
FIGURE 1. System Functional Block
MP2953B Rev. 1.02
www.MonolithicPower.com
11/11/2019
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© 2019 MPS. All Rights Reserved.
14
MP2953B – DIGITAL PWM CONTROLLER WITH PMBUS FOR VR12.5
System Configuration
The MP2953B provides EEPROM for storing
application configuration parameters. The default
values are pre-programmed at the factory. The
data can be programmed again using
STORE_USER_ALL command via the PMBus.
The MP2953B provides a differential output
voltage sense, an input voltage sense, and an
output enable function. Working with the IntelliPhase (MPS Driver MOS), the MP2953B senses
the per-phase current and the maximum
temperature among the power MOSFETs with
minimal external components. The PWM of the
MP2953B outputs 3.3V compatible tri-state
signals before outputting power to the load.
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EEPROM Operation
EEPROM is read automatically during the poweron
sequence
or
by
receiving
the
RESTORE_USER_ALL command from the
PMBus. The state machine of the MP2953B is
shown in Fig. 2.
EEPROM operation is accomplished easily with
MPS GUI software.
EEPROM is subject to more than 100,000
erase/write cycles.
STDY
POR
COPY
EEPROM
EC
Data Invalid
Command on
EEPROM
FAULTS
Waiting
Fault Clear
SYSTEM
INITIAL
Command
off
N
R
T
O
N
Command
off
SHUT
DOWN
POWER
ACTIVE
Protect = 1
SOFT
START
Protect = 1
R
Protect = 1
Command off
The MP2953B can be configured as a 3~6 phase
operation application via the PMBus (see Table
1).
TABLE 1. Phase Configuration and Active PWM
Pins
MFR_VR_CONFIG
Phase
Active PWM
[14:12]
Number
Pins
3’b100
2
1, 3
3’b011
3
1, 2, 3
3’b100
4
1, 2, 3, 4
3’b101
5
1, 2, 3, 4, 5
3’b110
6
1, 2, 3, 4, 5, 6
An unused PWM enters tri-state, and the active
phase becomes interleaving automatically.
Power-On Configuration
Data is OK
WAIT 1
The boot voltage, per-phase switching frequency,
SVID address, and PMBus slave address can be
set using pin configurations or using the registers
via the PMBus.
Protect = 0
The MP2953B is supplied by +5V voltage, its
internal LDOs produce +3.3V voltage for the
analog circuit and +1.8V voltage for the digital
circuit. The system is re-set by the internal
power-on re-set signal (POR). After the system
exits POR, the data in the EEPROM loads to the
registers to configure the VR operation. If the
setting is loaded from pins, then resistors with
1% tolerance must be connected from VBOOT,
VFS, ADDR_S, and ADDR_P to ground in order
to set the parameters of the controller. The
initialization process takes 700μs.
WAIT 2
FIGURE 2. System State Machine
MP2953B Rev. 1.02
www.MonolithicPower.com
11/11/2019
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© 2019 MPS. All Rights Reserved.
15
MP2953B – DIGITAL PWM CONTROLLER WITH PMBUS FOR VR12.5
EEPROM Fault and Wait State
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If the data in the EEPROM is invalid, the system
enters the EEPROM FAULT state and waits for
the error to clear. The data in the EEPROM is
ignored if the system detects an EEPROM fault.
The following 3 actions clear the EEPROM fault
in order to re-set with the default value in the
register:
1. Clear the EERPOM FAUTL via the PMBus;
2. Store the register data into the EEPROM via
the PMBus and re-start again;
3. Receive the SetVID command and run the
VR with default values in the registers.
Once the registers are loaded from the EEPROM,
the MP2953B enters a soft-start state. If any of
the conditions below occur, the system will
remain in the waiting state until the conditions are
removed:
1. Protection is triggered (i.e. the sense input
voltage is under the VIN_ON threshold), or
the sensed temperature is above the
OTP_LIMI, OVP1. The system enters the
WAIT2 state until the protection signal is reset.
EC
2. The internal enable command is off, the
system enters the WAIT1 state until the
enable command is on; the EEPROM will be
read again.
R
Soft-Start (SS)
N
Fig. 3 shows the soft-start process with a prebias function. The CCM signal is low to turn off all
phases until the reference voltage rises above
the output voltage.
If boot voltage is nonzero, the output voltage
ramps up to the boot voltage and asserts
ALERT#. ALERT# de-asserts after the STATUS1
register is read. When receiving a new SetVID
command, the controller ramps to the target
voltage with the rate of SVID_Fast or SVID_Slow.
If the boot voltage or the ICC max is set initially
to 0, the PWM is kept in tri-state until a valid
SVID voltage is received, and the ICC max is set
above 0. The controller then ramps the voltage to
the target value and asserts ALERT#.
After the controller completes the soft-start
process, it is ready to output power to the load
and assert VR_READY.
Power Active
The MP2953B applies a digital, non-linear control
to provide fast transient response and easy loop
compensation. The duty cycle of each phase’s
PWM updates in real-time, according to the input
voltage and reference voltage. Figure 4(a) shows
the steady-state performance with load current at
160A.
R
N
O
T
Before entering the power-active state, the
MP2953B executes the soft-start process to
charge the
output capacitor with
the
SetVID_Slow slew rate (until the reference
reaches the boot voltage).
FIGURE 3. Soft-Start with Pre-Bias
Once the pre-bias is over, the controller sets
PWM1 high (with a narrow minimum on pulse).
The controller increases the on-time according to
the VID and sensed input voltage. In next cycle,
the controller triggers phase 2 to turn on and exit
tri-state. All other phases will exit tri-state in this
manner.
MP2953B Rev. 1.02
www.MonolithicPower.com
11/11/2019
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2019 MPS. All Rights Reserved.
16
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MP2953B – DIGITAL PWM CONTROLLER WITH PMBUS FOR VR12.5
FIGURE 4(a). Steady State with Load @160A
FIGURE 4(c). Load Step Down @ 1kHz
Load transient performance is illustrated in
Figures 4(b)—(d). The MP2953B adaptively
changes the switching frequency of each
individual phase during load transient to achieve
fast closed-loop speed. Only one set of loop
compensation is needed, so it is very easy to set
the loop parameter.
FIGURE 4(d). Load Step @1MHz
N
Power State Change
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EC
Fig. 4(b) shows no ring-back when the load steps
up from 36A to 180A. Fig. 4(c) shows that the
overshoot of the output voltage is small during
load release. Fig. 4(d) shows the high-load
transient rate; the output voltage is stable. The
MP2953B meets Intel VR12.5 standards with a
minimum number of output capacitors.
FIGURE 4(b). Load Step Up @ 1kHz
The SVID bus changes the VR into different
power states to achieve high efficiency during
light-load conditions. These states are entered by
programming the power-state register using
SVID’s SetPS command. The VR optimizes its
power loss to flatten the efficiency curve over the
operating current range with the power-state
commands issued by the CPU.
In PS0 mode, all phases run in CCM. In PS1
mode (
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