MP20042DG-ZS-LF-P

MP20042 Dual, Low Noise, High PSRR 200mA Linear Regulator The Future of Analog IC Technology DESCRIPTION FEATURES The MP20042 is a dual-channel, micropower, low noise, low dropout and high PSRR linear regulator. The output voltage of MP20042 ranges from 1.2V to 5.0V and 1% accuracy by operating from a +2.5V to +6.0V input. The MP20042 can supply up to 200mA of load current at each channel. • • • • • • • The MP20042 uses an internal PMOS as the pass element, which consumes 114μA supply current (both LDOs on) at no load condition. The EN1 and EN2 pins control each output respectively. When both channels shutdown simultaneously, the chip will be turned off and consume nearly zero operation current which is suitable for battery-power devices. The MP20042 features current limiting and over temperature protection. Two LDOs in a 2mmx2mm QFN8 Package Up to 200mA Output Current (Per Channel) Dual Enable Pins Control Each Output 72dB PSRR at 1kHz 11μVRMS Low Noise Output 110mV Dropout at 100mA Load Very Fast Transient Responses with Small Output Capacitor Current Limiting and Thermal Protection • APPLICATIONS • • • • • Cellular Phones Battery-powered Equipment Laptop, Notebook, and Palmtop Computers Hand-held Equipment Wireless LAN “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. It is available in a 2mm x 2mm QFN8 package. TYPICAL APPLICATION EN1 EN1 EN2 OUT2 OUT2 COUT2 EN2 OUT1 OUT1 MP20042 COUT1 IN IN GND MP20042 Rev. 0.9 9/28/2009 CIN www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 1 MP20042-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR ORDERING INFORMATION* Part Number VOUT1 VOUT2 MP20042DG-JG-LF-Z MP20042DG-ZS-LF-Z MP20042DG-PN-LF-Z MP20042DG-DD-LF-Z MP20042DG-SJ-LF-Z MP20042DG-MG-LF-Z 2.5V 5.0V 3.0V 1.85V 3.3V 2.8V 1.8V 3.3V 2.85V 1.85V 2.5V 1.8V Package QFN8 (2mmx2mm) Temperature Top Marking -40°C to +85°C 7E 7L 8L 9L 2M 3M * Other output voltage versions between 1.2V and 5.0V are available in 100mV increments. Contact factory for availability. ORDERING GUIDE** MP20042DG- OUTPUT GUIDE*** -LF-Z VOUT2 VOUT1 Package Type G: QFN (2mm x 2mm x 1mm) ** For RoHS Compliant Packaging, add suffix - LF (e.g. MP20042DG-LF); For Tape and Reel, add suffix -Z (e.g. MP20042DG-LF-Z) Code C B F W G D Y H E J K VOLTAGE VOUT 1.2 1.3 1.5 1.6 1.8 1.85 1.9 2.0 2.1 2.5 2.6 Code T L M N V P Q X R S Z SELECTOR VOUT 2.65 2.7 2.8 2.85 2.9 3.0 3.1 3.15 3.2 3.3 5.0 *** Code in Bold are standard versions. For other output voltages between 1.2V and 5.0V contact factory for availability. Minimum order quantity on non-standard versions is 25,000 units. PACKAGE REFERENCE TOP VIEW MP20042 Rev. 0.9 9/28/2009 VOUT1 1 8 VOUT2 VIN 2 7 NC EN1 3 6 NC GND 4 5 EN2 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 2 MP20042-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR ABSOLUTE MXIMUM RATINGS (1) Supply Input Voltage ................................. 6.5V Continuous Power Dissipation (TA = +25°C)(2) ……………………………………………….1.25W Operation Temperature Range ... -40°C to 85°C Storage Temperature Range ..... -65°C to 150°C Lead Temperature (Soldering, 10sec) .....260°C Recommended Operating Conditions (3) Supply Input Voltage.......................2.5V to 6.0V Enable Input Voltage .........................0V to 6.0V Junction Temperature Range . –40°C to +125°C MP20042 Rev. 0.9 9/28/2009 Thermal Resistance (4) θJA θJC 2x2 QFN8 ............................... 80 ...... 16. .. °C/W Notes: 1) Exceeding these ratings may cause permanent damage to the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/ θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside its operating conditions. 4) Measured on JESD51-7 4-layer board. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 3 MP20042-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR ELECTRICAL CHARACTERISTICS VIN=3.6V, VOUT1=2.5V, VOUT2=1.8V, CIN=COUT1=COUT2=2.2uF, EN1=EN2=VIN, Typical Value at TA=25°C for each LDO unless otherwise noted. Parameter Symbol Output Voltage Accuracy (Load regulation)(5) Maximum Output Current Current Limit ΔVOUT IMAX ILIM Condition ILOAD = 1mA to 200mA Continuous RLoad=1Ω Quiescent Current IG Dropout Voltage (6) VDROP Line Regulation(7) ∆VLINE EN Input High Threshold EN Input Low Threshold EN Input Bias Current Shutdown Supply Current Thermal Shutdown Temperature Thermal Shutdown Hysteresis VIH VIL ISD IGSD TSD ΔTSD Min -1 Units +1 % mA mA No Load 114 uA IOUT = 100mA 110 mV IOUT = 200mA 250 mV VIN =(VOUT+0.4V or 2.5V) to 6V, IOUT=1mA 200 -0.05 +0.05 1.6 10Hz to 100kHz, COUT=4.7μF, ILOAD=1mA 100Hz, COUT = 2.2μF, ILOAD = 100mA 1kHz , COUT = 2.2μF, ILOAD = 100mA 100kHz , COUT = 2.2μF, ILOAD = 100mA Output Voltage AC PSRR Max 450 VIN = 2.5V to 6.0V VIN = 2.5V to 6.0V EN = VIN=6.5V EN1 = EN2 = GND Output Voltage Noise Typ 0.03 140 10 0.45 300 1 %/V V V nA uA °C °C 11 μVRMS 72 dB 72 dB 47 dB Notes: 5) Load Regulation= − VOUT ⎡I VOUT ⎡I ⎤ ⎣ OUT (MAX ) ⎦ ⎤ ⎣ OUT (MIN) ⎦ VOUT (NOM) × (%) 6) Dropout Voltage is defined as the input to output differential when the output voltage drops 100mV below its nominal value. 7) Line Regulation= VOUT ⎡ V ⎣ ⎤ IN(MAX ) ⎦ − VOUT ⎡ V ⎣ ⎤ IN(MIN) ⎦ ⎡V − VIN(MIN) ⎤ × VOUT(NOM) ⎣ IN(MAX ) ⎦ × (% / V) PIN FUNCTIONS Pin # 1 2 3 4 5 6, 7 8 MP20042 Rev. 0.9 9/28/2009 Name VOUT1 VIN EN1 GND EN2 NC VOUT2 Description Channel 1 Output Voltage Supply Input Pin Channel 1 Enable (Active High). Do Not Float This Pin. Common Ground Channel 2 Enable (Active High). Do Not Float This Pin. Channel 2 Output Voltage www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 4 MP20042-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR TYPICAL PERFORMANCE CHARACTERISTICS VIN=3.6V, VOUT1=2.5V, VOUT2=1.8V, CIN=COUT1=COUT2=2.2uF, EN1=EN2=VIN, Typical Value at TA = 25°C for Both Channel Enabled. Quiescent Current vs. Supply Voltage 180 300 DROPOUT VOLTAGE (mV) 200 150 150 120 90 100 60 50 30 0 2.5 3 3.5 4 4.5 5 5.5 Dropout Voltage vs. Temperature Quiescent Current vs. Temperature 0 -20 6 0 20 40 60 85 280 260 240 220 200 -40 -20 ILOAD=200mA 0 20 40 60 85 0.25 0.20 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15 -0.20 -0.25 -40 -20 0 20 40 60 85 Power Supply Rejection Ratio vs. Frequency 80 70 60 50 40 30 20 10 0 Channel-to-Channel Isolation vs. Frequency CHANNEL ISOLATION (dB) Out Voltage Accuracy vs. Temperature POWER SUPPLY REJECTION RATIO (dB) OUT VOLTAGE ACCURACY (%) INPUT VOLTAGE (V) 120 100 80 60 40 20 0 10 100 1000 10000 100000 1000000 100 FREQUENCY(Hz) 10000 100000 1000000 FREQUENCY(Hz) Load Transient Response Line Transient Response 1000 EN Pin Shut Down Response VIN=3.6V, VOUT=1.8V, VEN=0 to 5V VOUT=3.5V to 4.5V, CIN=0uF, COUT=2.2uF VIN=3.6V, VOUT=1.8V ILOAD=0 to 80mA, with Resistor Load ILOAD=50mA, with Resistor Load No Load VOUT 10mV/div VOUT 10mV/div VOUT 1V/div ILOAD 50mA/div VIN 1V/div 1ms/div MP20042 Rev. 0.9 9/28/2009 VEN 5V/div 1ms/div www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 5 MP20042-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR BLOCK DIAGRAM Figure1—Functional Block Diagram OPERATION The MP20042 integrates two low noise, low dropout, low quiescent current and high PSRR linear regulators. It is intended for use in devices that require very low voltage, low quiescent current power such as wireless LAN, batterypowered equipment and hand-held equipment. The MP20042 uses internal PMOSs as the pass elements and features internal thermal shutdown and an internal current limit circuit. Dropout Voltage Dropout voltage is the minimum input to output differential voltage required for the regulator to maintain an output voltage within 100mV of its nominal value. Because the PMOS pass element behaves as a low-value resistor, the dropout voltage of MP20042 is very low. Shutdown The MP20042 can be switched ON or OFF by a logic input at the EN pin. A high voltage at this pin will turn the device on. When the EN pin is low, the regulator output is off. The EN pin should be tied to VIN to keep the regulator output always on if the application does not require the shutdown feature. Do not float the EN pin. MP20042 Rev. 0.9 9/28/2009 Current Limit The MP20042 includes two independent current limit structures which monitor and control each PMOS’s gate voltage limiting the guaranteed maximum output current to 200mA. Thermal Protection Thermal protection turns off the PMOS when the junction temperature exceeds +140ºC, allowing the IC to cool. When the IC’s junction temperature drops by 10ºC, the PMOS will be turned on again. Thermal protection limits total power dissipation in the MP20042. For reliable operation, junction temperature should be limited to 125 ºC maximum. Load-Transient Considerations The output response of load-transient consists of a DC shift and transient response. Because of the excellent load regulation of MP20042, the DC shift is very small. The output voltage transient depends on the output capacitor’s value and the ESR. Increasing the capacitance and decreasing the ESR will improve the transient response. Typical output voltage transient spike of MP20042 for a step change in the load current from 0mA to 80mA is tens mV. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 6 MP20042-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR APPLICATION INFORMATION 100 Power Dissipation The power dissipation for any package depends on the thermal resistance of the case and circuit board, the temperature difference between the junction and ambient air, and the rate of airflow. The power dissipation across the device can be represented by the equation: Unstable 10 1 Stable P = (VIN - VOUT) ×IOUT The allowable power dissipation can calculated using the following equation: P(MAX) = (TJunction - TAmbient) / θJA be Where (TJunction - TAmbient) is the temperature difference between the junction and the surrounding environment, θJA is the thermal resistance from the junction to the ambient environment. Connect the GND pin of MP20042 to ground using a large pad or ground plane helps to channel heat away. Input Capacitor Selection Using a capacitor whose value is >0.47µF on the MP20042 input and the amount of capacitance can be increased without limit. Larger values will help improve line transient response with the drawback of increased size. Ceramic capacitors are preferred, but tantalum capacitors may also suffice. Output Capacitor Selection The MP20042 is designed specifically to work with very low ESR ceramic output capacitor in space-saving and performance consideration. A ceramic capacitor in the range of 0.47µF and 10µF, and with ESR lower than 1.2Ω is suitable for the MP20042 application circuit. Output capacitor of larger values will help to improve load transient response and reduce noise with the drawback of increased size. 0.1 0 40 80 120 160 200 LOAD CURRENT (mA) Figure 2—Relationship between ESR and LDO Stability Reverse Current Path The PMOS used in the MP20042 has an inherent diode connected between input and output (see Figure3). If VOUT - VIN is more than a diode-drop, this diode gets forward biased and starts to conduct. To avoid misoperation, an external Schottky connected in parallel with the internal parasitic diode prevents it from being turned on by limiting the voltage drop across it to about 0.3V (see Figure 4). Figure 3—Inherent Diode Connected between Each Regulator Input and Output Figure 4—External Schottky Diode Connected in Parallel with the Internal Parasitic Diode MP20042 Rev. 0.9 9/28/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 7 MP20042-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR PCB layout guide PCB layout is very important to achieve good regulation, ripple rejection, transient response and thermal performance. It is highly recommended to duplicate EVB layout for optimum performance. If change is necessary, please follow these guidelines and take figure ? for reference. 1) Input and output bypass ceramic capacitors are suggested to be put close to the IN Pin and OUT Pin respectively. 2) Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close to the chip as possible. 3) Connect IN, OUT and especially GND respectively to a large copper area to cool the chip to improve thermal performance and long-term reliability. EN1 EN2 EN1 EN2 R2 R1 OUT2 OUT2 COUT2 OUT1 OUT1 MP20042 COUT1 IN IN GND CIN Top Layer Figure 5—PCB Layout MP20042 Rev. 0.9 9/28/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 8 MP20042-DUAL, LOW NOISE, HIGH PSRR, 200mA LINEAR REGULATOR PACKAGE INFORMATION 2mm x 2mm QFN8 PIN 1 ID MARKING 1.90 2.10 0.25 0.45 0.18 0.30 1.90 2.10 PIN 1 ID INDEX AREA PIN 1 ID SEE DETAIL A 0.45 0.65 8 1 1.05 1.25 0.50 BSC 5 TOP VIEW 4 BOTTOM VIEW 0.80 1.00 PIN 1 ID OPTION A R0.20 TYP. PIN 1 ID OPTION B R0.20 TYP. 0.20 REF 0.00 0.05 SIDE VIEW DETAIL A NOTE: 1.90 0.70 0.60 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX. 4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VCCD-3. 5) DRAWING IS NOT TO SCALE. 0.25 1.20 0.50 RECOMMENDED LAND PATTERN NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP20042 Rev. 0.9 9/28/2009 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2009 MPS. All Rights Reserved. 9