MP20073
2A, 1.3V–6.0V
DDR Memory Termination Regulator
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP20073 integrates the DDR memory
termination regulator with the output voltage
(VTT) and a buffered VTTREF outputs is a half
of VREF.
VDDQ Voltage Range: 1.3V to 6.0 V
Up to 2A Integrated Sink/Source Linear
Regulator with Accurate VREF/2 Divider
Reference for DDR Termination
Requires Only 20µF Ceramic Output
Capacitance
Drive Voltage : 3.3V
1.3V Input (VDDQ) Helps Reduce Total
Power Dissipation
Integrated Divider Tracks VREF for VTT
and VTTREF
Kelvin Sensing (VTTSEN)
±30mV Accuracy for VTT and VTTREF
Built-In Soft-Start, UVLO and OCL
Thermal Shutdown
The VTT-LDO is a 2A sink/source tracking
termination regulator. It is specifically designed
for low-cost/low-external component count
systems, where space is a premium.
The MP20073 maintains a fast transient
response only requiring 20µF (2x10µF) of
ceramic output capacitance. The MP20073
supports Kelvin sensing functions.
The MP20073 is available in the 8-pin MSOP
with Exposed PAD package and is specified
from -40oC to 85oC.
APPLICATIONS
Notebook DDR2/3 Memory Supply and
Termination Voltage in ACPI Compliant
Active Termination Busses
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
VDDQ
1
R3
20
6
DDQ
VTTREF
REF
8
VTTREF
MP20073
5
3.3V
VDRV
VTTSEN
4
R2
100k
EN
7
VTT
VTTEN
GND
3
MP20073 Rev. 1.0
10/16/2012
2
VTT
C9
NC
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© 2012 MPS. All Rights Reserved.
1
MP20073 – 2A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR
ORDERING INFORMATION
Part Number*
MP20073DH
Package
MSOP8E
Top Marking
20073
Free Air Temperature (TA)
-40C to +85C
* For Tape & Reel, add suffix –Z (e.g. MP20073DH–Z);
For RoHS Compliant Packaging, add suffix –LF (e.g. MP20073DH–LF–Z)
PACKAGE REFERENCE
TOP VIEW
DDQ
1
8
VTTREF
VTT
2
7
EN
GND
3
6
REF
VTTSEN
4
5
VDRV
EXPOSED PAD
ON BACKSIDE
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VDDQ...................... -0.3V to 6.0V
Drive Voltage VDRV..................... -0.3V to 6.0V
All Other Pins................................ -0.3V to 6.0V
(2)
Continuous Power Dissipation (TA = +25°C)
........................................................... 1.56W
Junction Temperature...............................150oC
Lead Temperature ....................................260oC
Storage Temperature .............. -50oC to +150oC
Recommended Operating Conditions
(3)
Drive Voltage VDRV.......................... 3.3V to 5V
Operating Junct. Temp (TJ) ......-40oC to +125oC
MP20073 Rev. 1.0
10/16/2012
Thermal Resistance
(4)
θJA
θJC
MSOP8E.................................. 80...... 12... oC/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/ θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
3) The device is not guaranteed to function outside of its operating
conditions.
4) Measured on JESD51-7 4-layer board.
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© 2012 MPS. All Rights Reserved.
2
MP20073 – 2A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR
ELECTRICAL CHARACTERISTICS
VDRV = 3.3V, TA = +25oC, unless otherwise noted.
Parameters
Symbol
VDRV Operating Voltage
VDRV
VDRV Shut down current
IDRV_SD
Test Condition
Min
Typ
Max
Unit
-
3
3.3
5
V
VDRV =3.3 V, VDDQ=0V
-
0.2
1.0
-
1.3
150
25
3
-
A
mA
o
C
o
C
-
0.9
1.3
V
-30
-30
-
30
30
mV
-30
-30
-
30
30
mV
VDRV Operation Current
IDRV
VEN_H, VTT=0.75V
Thermal Trip Point
TSD
Hysteresis
TSDHYS
VDDQ
UVLO
Upper
VDDQUV+ Rising Edge; hysteresis = 55mV
Threshold
1/2VREF – VTT, VREF = 1.8V,
IVTT = 0 to 2A (Sink Current)
IVTT = 0 to 2A (Source Current)
VTT with Respect to 1/2VREF
dVTT0
1/2VREF – VTT, VREF = 1.5V,
IVTT = 0 to 2.5A (Sink Current)
IVTT = 0 to 2.5A (Source Current)
Source Current Limit
ILIMVTsrc
-
-
3.0
-
A
Sink Current Limit
ILIMVTsnk -
-
3.0
-
A
ILIMVTSS
-
-
1.0
-
A
VREF=1.8, VDRV=3.3V
-
9
-
VREF=1.5V, VDRV=3.3V
-
7
10
-
-
mA
-18
-
18
mV
-15
-
15
mV
Soft−Start
Limit
Source
Current
Maximum Soft−Start Time
VTTREF Source Current
VTTREF Accuracy Referred
to 1/2VREF
tssvttmax
IVTTR
dVTTR
VREF = 1.8 V or 1.5 V
1/2VREF – VTTR,
VREF = 1.8 V,
IVTTR = 0 mA to 10 mA
1/2VREF – VTTR,
VREF = 1.5 V,
IVTTR = 0 mA to 10 mA
us
VEN Pin Threshold High
VEN_H
-
1.4
-
-
V
VEN Pin Threshold Low
VEN_L
-
-
-
0.5
V
VEN = 3.3 V
-
-
1.0
A
VEN Pin Input Current
MP20073 Rev. 1.0
10/16/2012
IIN_VEN
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3
MP20073 – 2A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR
PIN FUNCTIONS
Pin #
Name
1
DDQ
2
4
5
VTT
GND,
Exposed Pad
VTTSEN
VDRV
6
REF
7
EN
8
VTTREF
3
MP20073 Rev. 1.0
10/16/2012
Description
Power input for VTT regulator. Connect to GND through 10uF ceramic capacitor.
It is normally connected to the VDDQ of DDR memory rail.
Power output for the VTT LDO.
The exposed pad and GND pin must be connected to the same ground plane.
Kelvin sensed feedback signal.
Chip bias Voltage.
LDO signal input for generating VDDQ/2 reference.
VTT regulator enable input. High to enable the chip.
Buffered output for the system. The receiving end of the DDR memory cells needs
this signal for their input comparator.
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4
MP20073 – 2A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR
TYPICAL PERFORMANCE CHARACTERISTICS
C1 =C2 = C3=10µF, C4 =C6 =0.1µF, C7 =4.7µF, VDRV =3.3V, TA=25 oC, unless otherwise noted.
DDR2 Regulation
0.94
0.78
0.93
0.77
0.92
0.76
0.91
0.75
0.74
0.72
0.87
-1.2
0
ITT (A)
1.2
0.86
2.4 3
0
INPUT CURRENT ( mA )
2.0
VTT (mV)
-20
-30
-40
-20
-30
-40
-3 -2.4
-1.2
0
ITT (A)
1.2
2.4 3
-50
VDDQ =VREF=1.8V, VTT = 0.9V
0
0.5
1
1.5
2
ITT (A)
2.5
3
Shut Down Input Current
vs. Temp
Input Supply Current
vs. Temp
DDR3 Source Regulation
-10
-10
0.89
0.88
-3 -2.4
0
0.90
0.73
0.71
DDR2 Source Regulation
VTT (mV)
0.79
VTT (V)
VTT (V)
DDR3 Regulation
0.45
VDDQ =VREF=1.8V, VTT = 0V
0.40
1.6
0.35
0.30
1.2
0.25
0.20
0.8
0.15
0.10
0.4
0.05
-50
0
0.5
1
1.5
2
2.5
3
0.0
-40
ITT (A)
-10
20
50
80 110 140
0.00
TEMPERATURE ( OC)
-40
-10
20
50
80 110 140
TEMPERATURE ( OC)
Source Over Current Protection Power Ramp Up
Power Ramp Down
VDDQ =VREF=1.8V, VTT = 0.9V
VDDQ =VREF=1.8V, VTT = 0.9V
VREF
2V/div.
VTTREF
1V/div.
VTT
0.5V/div.
ITT
2A/div.
VDDQ =VREF=1.8V, VTT = 0.9V
VREF
2V/div.
VREF
2V/div.
VDDQ
2V/div.
VDDQ
2V/div.
VTT
0.5V/div.
VTT
0.5V/div.
ITT
1A/div.
ITT
1A/div.
4ms/div.
MP20073 Rev. 1.0
10/16/2012
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10ms/div.
5
MP20073 – 2A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
C1 =C2 = C3=10µF, C4 =C6 =0.1µF, C7 =4.7µF, VDRV =3.3V, TA=25 oC, unless otherwise noted.
VREF
2V/div.
VTTREF
1V/div.
VTT
0.5V/div.
ITT
2A/div.
Enable On
Enable Off
VDDQ =VREF=1.8V, VTT = 0.9V
VDDQ =VREF=1.8V, VTT = 0.9V
VREF
2V/div.
VTTEN
2V/div.
VREF
2V/div.
VTTEN
2V/div.
VTT
1V/div.
VTT
1V/div.
ITT
1A/div.
ITT
1A/div.
µ
Short Circuit
Short Circuit Recovery
Source Load Transient
VDDQ =VREF=1.8V, VTT = 0.9V
VDDQ =VREF=1.8V, VTT = 0.9V
VDDQ =VREF=1.8V, VTT = 0.9V
VTT
20mV/div.
VTT
0.5V/div.
VTT
0.5V/div.
ITT
2A/div.
ITT
2A/div.
ITT
1A/div.
µ
Sink Load Transient
VDDQ =VREF=1.5V, VTT = 0.75V
VSINK= 1.5V
VTT
20mV/div.
ITT
1A/div.
µ
MP20073 Rev. 1.0
10/16/2012
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© 2012 MPS. All Rights Reserved.
6
MP20073 – 2A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR
DETAILED OPERATING DESCRIPTION
VREF
VDDQ
DDQ
REF
Soft-Start
3.3V
VDRV
DDQ
DDQ
UVLO
VTT
Regulation
& Deadband
Control
Current
Limiter
VTT
VTT
Current
Limiter
GND
VTTSEN
VTTSEN
VTTREF
VEN
VTTREF
EN
Figure 1—Functional Block Diagram
Control Logic
The internal control logic is powered by VDRV.
The IC is enabled whenever VDDQ UVLO is
pulled low. VTTREF output begins to track
VREF/2. When the VTTEN pin is high, the VTT
regulator is activated.
VTTREF Output
The VTTREF output tracks VREF/2 with 2%
accuracy. It has source current capability of up to
15mA. VTTREF should be bypassed to analog
ground of the device by 1.0F ceramic capacitor
for stable operation.
The VTTREF is turned on as long as VDDQ is
higher the UVLO threshold. VTTREF features a
soft-start and tracks VREF/2.
Output Voltages Sensing
The VTT output voltage is sensed across the
VTTSEN and GND pins. The VTTSEN should be
connected to the VTT regulation point, which is
MP20073 Rev. 1.0
10/16/2012
usually the VTT local bypass capacitor, via a
direct sense trace. The GND should be
connected via a direct sense trace to the ground
of the VTT local bypass capacitor for load.
VDDQ UVLO Protection
For VDDQ undervoltage lockout (UVLO)
protection, the MP20073 monitors VDDQ voltage.
When the VDDQ voltage is lower than UVLO
threshold voltage, the VTT regulator is shut off.
Current Protection of VTT Active Terminator
To provide protection for the internal FETs, over
current limit(OCL) of 3A is implemented.
The LDO has a constant overcurrent limit (OCL)
at 3A. This trip point is reduced to 1.0 A if the
output voltage drops below 1/3 of the target
voltage.
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MP20073 – 2A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR
Thermal Consideration of VTT Active
Terminator
The VTT terminator is designed to handle large
transient output currents. If large currents are
required for very long duration, then care should
be taken to ensure the maximum junction
temperature is not exceeded. The 8-pin MSOP
with ExposedPAD has a thermal resistance of
50oC/W (dependent on air flow, and PCB design).
In order to take full advantage of the thermal
capability of this package, the exposed pad
should be soldered directly onto the PCB ground
layer to allow good thermal contact. It is
recommended that the PCB should have 10 to 15
vias with 0.3mm drill size underneath the
exposed thermal pad connecting all the ground
layers
MP20073 Rev. 1.0
10/16/2012
Supply Voltage Undervoltage Monitor
The IC continuously monitors VDDQ. If VDDQ is
set higher than its preset threshold and VTTEN is
high too, the IC will start up.
Thermal Shutdown
When the chip junction temperature exceeds
150oC, the entire IC is shutdown. The IC
resumes normal operation only after the junction
temperature dropping below 125oC.
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8
MP20073 – 2A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR
APPLICATION INFORMATION
Input Capacitor
Depending on the trace impedance from the
power supply to the part, transient increase of
source current is supplied mostly by the charge
from the VDDQ input capacitor. Use a 10μF (or
more) ceramic capacitor to supply this transient
charge. Provide more input capacitance as more
output capacitance is used at VTT. In general,
use 1/2 COUT for input.
Output Capacitor
For stable operation, total capacitance of the VTT
output terminal can be equal or greater than
20μF. Attach two 10μF ceramic capacitors in
parallel to minimize the effect of ESR and ESL. If
the ESR is greater than 10m, insert an R-C
filter between the output and the VTTSEN input
to achieve loop stability. The R-C filter time
constant should be almost the same or slightly
lower than the time constant of the output
capacitor and its ESR.
VDRV Capacitor
Add a ceramic capacitor with a value between
1.0μF and 4.7μF placed close to the VDRV pin,
to stabilize 3.3V from any parasitic impedance
from the supply.
Thermal design
As the MP20073 is a linear regulator, the VTT
current flow in both source and sink directions
generate power dissipation from the device.
In the source phase, the potential difference
between VDDQ and VTT times VTT current
becomes
the
power
dissipation,
Psource=(VDDQ-VTT) x Isource
In this case, if VDDQ is connected to an
alternative power supply lower than VDDQ
voltage, power loss can be decreased.
For the sink phase, VTT voltage is applied across
the internal LDO regulator, and the power
dissipation Psink is:
The device does not sink and source the current
at the same time and source/sink current varies
rapidly with time. The actual power dissipation to
be considered for thermal design is an average
of the above values over time.
Another power consumption is the current used
for internal control circuitry from VDDQ supply.
This power needs to be effectively dissipated
from the package.
PCB Layout Guidelines
Good PCB layout design is critical to ensure high
performance and stable operation of the DDR
power controller. The following items must be
considered when preparing PCB layout:
1. All high−current traces must be kept as short
and wide as possible to reduce power loss.
High−current traces are the trace from the input
voltage terminal to VDDQ pin, the trace from the
VTT output terminal to the load, the trace from
the input ground terminal to the VTT output
ground terminal, and the trace from VTT output
ground terminal to the GND pin.
Power handling and heaksinking of high−current
traces can be improved by also routing the same
high−current traces in the other layers by the
same path and joining them together with
multiple vias.
2. To ensure the proper function of the device,
separated ground connections should be used
for different parts of the application circuit
according to their functions.
The VTT output capacitor ground should be
connected to the GND pin first with a short trace,
it is then connected to the ground plane of GND.
The input capacitor ground, the VTT output
capacitor ground, the VDDQ decoupling
capacitor ground should be connected to the
GND plane.
Psink=VTT x Isink
MP20073 Rev. 1.0
10/16/2012
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9
MP20073 – 2A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR
3. The thermal pad of the 8-pin MSOP package
should to be connected to GND for better thermal
performance. It is recommended to use a PCB
with 1 oz or 2oz copper foil.
4. A separate sense trace should be used to
connect the VTT point of regulation, which is
usually the local bypass capacitor for load, to the
VTTSEN pin.
connect the VREF point of regulation to the
VTTREF pin to ensure the accuracy of the
reference voltage to VTT.
6. VDDQ should be connected to VREF Input
with wide and short trace if VDDQ is used as the
sourcing supply for VTT. An input capacitor of at
least 10F should be added close to the VDDQ
pin and bypassed to GND if external voltage
supply is used as the VTT sourcing supply.
5. Separate sense trace should be used to
MP20073 Rev. 1.0
10/16/2012
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10
MP20073 – 2A, 1.3V-6.0V INPUT, DDR MEMORY TERMINATION REGUALTOR
PACKAGE INFORMATION
MSOP8E (EXPOSED PAD)
0.087(2.20)
0.099(2.50)
0.114(2.90)
0.122(3.10)
5
8
0.114(2.90)
0.122(3.10)
PIN 1 ID
(NOTE 5)
0.187(4.75)
0.199(5.05)
0.062(1.58)
0.074(1.88)
Exposed Pad
0.010(0.25)
0.014(0.35)
4
1
0.0256(0.65)BSC
BOTTOM VIEW
TOP VIEW
GAUGE PLANE
0.010(0.25)
0.030(0.75)
0.037(0.95)
0.043(1.10)MAX
SEATING PLANE
0.002(0.05)
0.006(0.15)
FRONT VIEW
NOTE:
0.181(4.60)
0.040(1.00)
0.016(0.40)
0.016(0.40)
0.026(0.65)
SIDE VIEW
0.100(2.54)
0.075(1.90)
0o-6o
0.004(0.10)
0.008(0.20)
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS
IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURR.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) PIN 1 IDENTIFICATION HAS HALF OR FULL CIRCLE OPTION.
6) DRAWING MEETS JEDEC MO-187, VARIATION AA-T.
7) DRAWING IS NOT TO SCALE.
0.0256(0.65)BSC
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP20073 Rev. 1.0
10/16/2012
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