MP2106
1.5A, 15V, 800kHz
Synchronous Buck Converter
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP2106 is a 1.5A, 800kHz synchronous
buck converter designed for low voltage
applications requiring high efficiency. It is
capable of providing output voltages as low as
0.9V, and integrates top and bottom switches to
minimize power loss and component count. The
800kHz switching frequency reduces the size of
filtering components, further reducing the
solution size.
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•
•
•
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•
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The MP2106 includes cycle-by-cycle current
limiting and under voltage lockout. The internal
power switches, combined with the tiny 10-pin
MSOP and QFN packages, provide a solution
requiring a minimum of surface area.
EVALUATION BOARD REFERENCE
Board Number
Dimensions
EV2106DQ/DK-00A
2.5”X x 2.0”Y x 0.5”Z
1.5A Output Current
Synchronous Rectification
Internal 210mΩ and 255mΩ Power Switches
Input Range of 2.6V to 15V
>90% Efficiency
Zero Current Shutdown Mode
Under Voltage Lockout Protection
Soft-Start Operation
Thermal Shutdown
Internal Current Limit (Source & Sink)
Tiny 10-Pin MSOP or QFN Package
APPLICATIONS
•
•
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•
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DC/DC Regulation from Wall Adapters
Portable Entertainment Systems
Set Top Boxes
Digital Video Cameras, DECT
Networking Equipment
Wireless Modems
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TYPICAL APPLICATION
Efficiency vs.
Load Current
C7
R4
7
5
OFF ON
1
3
C5
10nF
C3
3.3nF
R3
100
10nF
C1
BST
LX
MP2106
SS
COMP
VREF
4
FB
SGND PGND
C6
10nF
10
9
VIN=3.3V
80
6
VIN
RUN
90
L1
OUTPUT
1.8V / 1.5A
8
2
R2
C2
EFFICIENCY (%)
INPUT
2.6V to 15V
70
60
VIN=5V
50
40
30
20
R1
10
0
0.01
MP2106_TAC_S01
0.1
1
LOAD CURRENT (A)
10
MP2106_TAC_EC02
MP2106 Rev. 1.81
3/7/2011
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1
MP2106 – 1.5A, 15V, 800kHz SYNCHRONOUS BUCK CONVERTER
ORDERING INFORMATION
Part Number
Package
Top Marking
Free Air Temperature (TA)
MP2106DK*
MSOP10
2106D
-40°C to +85°C
MP2106DQ**
QFN10 (3x3mm)
C4
-40°C to +85°C
* For Tape & Reel, add suffix –Z (e.g. MP2106DK–Z).
For Lead Free, add suffix –LF (e.g. MP2106DK–LF–Z)
** For Tape & Reel, add suffix –Z (e.g. MP2106DQ–Z).
For Lead Free, add suffix –LF (e.g. MP2106DQ–LF–Z)
PACKAGE REFERENCE
TOP VIEW
TOP VIEW
SS
1
10
SGND
FB
2
9
PGND
LX
COMP
3
8
LX
VIN
VREF
4
7
VIN
RUN
5
6
BST
SS
1
10
SGND
FB
2
9
PGND
COMP
3
8
VREF
4
7
RUN
5
6
BST
MP2106_PD01-MSOP10
EXPOSED PAD
ON BACKSIDE
MP2106_PD02-QFN10
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance
Input Supply Voltage VIN .............................. 16V
LX Voltage VLX ...................... -0.3V to VIN + 0.3V
BST to LX Voltage .......................... -0.3V to +6V
Voltage on All Other Pins ................ -0.3V to +6V
(2)
Continuous Power Dissipation (TA = +25°C)
MSOP10 .................................................. 0.83W
QFN10 ....................................................... 2.5W
Junction Temperature ...............................150°C
Lead Temperature ....................................260°C
Storage Temperature ............... -55°C to +150°C
MSOP10 ................................ 150 ..... 65... °C/W
QFN10 (3x3mm) ..................... 50 ...... 12... °C/W
Recommended Operating Conditions
(3)
Input Supply Voltage VIN .................. 2.6V to 15V
Output Voltage VOUT ................0.9V to VIN x 80%
Maximum Junction Temp. (TJ) ............... +125°C
MP2106 Rev. 1.81
3/7/2011
(4)
θJA
θJC
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
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2
MP2106 – 1.5A, 15V, 800kHz SYNCHRONOUS BUCK CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 5.0V, TA = +25°C, unless otherwise noted.
Parameter
Input Voltage Range
Input Under Voltage Lockout
Input Under Voltage Lockout
Hysteresis
Shutdown Supply Current
Operating Supply Current
VREF Voltage
RUN Input Low Voltage
RUN Input High Voltage
RUN Hysteresis
RUN Input Bias Current
Oscillator
Switching Frequency
Maximum Duty Cycle
Minimum On Time
Error Amplifier
Voltage Gain
Transconductance
COMP Maximum Output Current
FB Regulation Voltage
FB Input Bias Current
Soft-Start
Soft-Start Current
Soft-Start Period
Output Switch On-Resistance
Switch On Resistance
Synchronous Rectifier On Resistance
Switch Current Limit (Source)
Synchronous Rectifier Current Limit
(Sink) (5)
Thermal Shutdown
Symbol Condition
VIN
VREF
VIL
VHL
Min
2.6
VRUN ≤ 0.3V
VRUN > 2V, VFB = 1.1V
VIN = 2.6V to 15V
Typ
2.2
Units
V
V
100
mV
0.5
1.2
2.4
Max
15
1.0
1.8
0.4
1.5
100
1
fSW
DMAX
tON
200
kHz
%
ns
VFB = 0.895V
400
300
±30
895
-100
V/V
µA/V
µA
mV
nA
CSS = 0.1µF
2
15
µA
ms
255
315
210
255
2.5
mΩ
mΩ
mΩ
mΩ
A
VFB = 0.7V
700
85
AVEA
GEA
VFB
IFB
875
ISS
VIN = 5V
VIN = 3V
VIN = 5V
VIN = 3V
2.0
800
900
µA
mA
V
V
V
mV
µA
915
3.2
350
mA
160
°C
Note:
5) Guaranteed by design.
MP2106 Rev. 1.81
3/7/2011
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MP2106 – 1.5A, 15V, 800kHz SYNCHRONOUS BUCK CONVERTER
PIN FUNCTIONS
Pin #
1
2
3
4
5
6
7
8
9
10
Name Description
Soft-Start Input. Place a capacitor from SS to SGND to set the soft-start period. The MP2106
SS
sources 2µA from SS to the soft-start capacitor at startup. As the SS voltage rises, the
feedback threshold voltage increases to limit inrush current during startup.
Feedback Input. FB is the inverting input of the internal error amplifier. Connect a resistive
FB
voltage divider from the output voltage to FB to set the output voltage value.
Compensation Node. COMP is the output of the error amplifier. Connect a series RC network
COMP
to compensate the regulation control loop.
Internal 2.4V Regulator Bypass. Connect a 10nF capacitor between VREF and SGND to
VREF
bypass the internal regulator. Do not apply any load to VREF.
On/Off Control Input. Drive RUN high to turn on the MP2106; low to turn it off. For automatic
RUN
startup, connect RUN to VIN via a pullup resistor.
Power Switch Boost. BST powers the gate of the high-side N-Channel power MOSFET switch.
BST
Connect a 10nF or greater capacitor between BST and LX.
Internal Power Input. VIN supplies the power to the MP2106 through the internal LDO
VIN
regulator. Bypass VIN to PGND with a 10µF or greater capacitor. Connect VIN to the input
source voltage.
Output Switching Node. LX is the source of the high-side N-Channel switch and the drain of the
LX
low-side N-Channel switch. Connect the output LC filter between LX and the output.
Power Ground. PGND is the source of the N-Channel MOSFET synchronous rectifier. Connect
PGND
PGND to SGND as close to the MP2106 as possible.
SGND Signal Ground.
MP2106 Rev. 1.81
3/7/2011
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MP2106 – 1.5A, 15V, 800kHz SYNCHRONOUS BUCK CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
Circuit of Figure 2, VIN = 5V, VOUT = 1.8V, L1 = 5µH, C1 = 10µF, C2 = 22µF, TA = +25°C, unless
otherwise noted.
Steady State Operation
Steady State Operation
1.5A Load
No Load
VSW
5V/div.
VSW
5V/div.
VO
AC Coupled
10mV/div.
VIN
AC Coupled
200mV/div.
VOUT
AC Coupled
200mV/div.
VO
AC Coupled
10mV/div.
IL
1A/div.
VIN
AC Coupled
20mV/div.
ILOAD
1A/div.
IL
1A/div.
IL
1A/div.
MP2106-TPC01
MP2106-TPC02
MP2106-TPC03
Startup from Shutdown
Startup from Shutdown
1.5A Resistive Load
No Load
VEN
2V/div.
VEN
2V/div.
VOUT
1V/div.
VOUT
1V/div.
IL
1A/div.
IL
1A/div.
VSW
5V/div.
VSW
5V/div.
1ms/div.
1ms/div.
MP2106-TPC04
MP2106-TPC05
Short Circuit Protection
Short Circuit Recovery
VOUT
1V/div.
VOUT
1V/div.
IL
1A/div.
IL
1A/div.
MP2106-TPC06
MP2106 Rev. 1.81
3/7/2011
Load Transient
MP2106-TPC07
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MP2106 – 1.5A, 15V, 800kHz SYNCHRONOUS BUCK CONVERTER
FUNCTIONAL BLOCK DIAGRAM
VIN
VIN
OFF ON
RUN
5
VREF
4
C6
ENABLE
CKT & LDO
REGULATOR
VBP
2.4V
GATE
DRIVE
REGULATOR
Vdr
CURRENT
SENSE
AMPLIFIER
C1
7
2.6V to 15V
+
-BST
Vdr
PWM
COMPARATOR
6
+
--
C7
LX
CONTROL
LOGIC
Vdr
L1
VOUT
8
C2
800KHz
OSCILLATOR
RAMP
VBP
CURRENT
LIMIT
COMPARATOR
+
--
UVLO &
THERMAL
SHUTDOWN
R2
+
--
PGND
SS
9
C5
1
-FB
GM -ERROR
AMPLIFIER
VFB
0.895V
CURRENT
LIMIT
THRESHOLD
10
R1
3
SGND
C4
2
+
COMP
R3
C3
MP2106_BD01
Figure 1—Functional Block Diagram
MP2106 Rev. 1.81
3/7/2011
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MP2106 – 1.5A, 15V, 800kHz SYNCHRONOUS BUCK CONVERTER
sufficiently, the PWM comparator turns off the
high-side switch and turns on the low-side
switch, forcing the inductor current to decrease.
The average inductor current is controlled by
the voltage at COMP, which in turn is controlled
by the output voltage. Thus the output voltage
controls the inductor current to satisfy the load.
OPERATION
The MP2106 measures the output voltage
through an external resistive voltage divider and
compares that voltage to the internal 0.9V
reference in order to generate the error voltage
at COMP. The current-mode regulator uses the
voltage at COMP and compares it to the
inductor current to regulate the output voltage.
The use of current-mode regulation improves
transient response and improves control loop
stability.
Since the high-side N-Channel MOSFET
requires voltages above VIN to drive its gate, a
bootstrap capacitor from LX to BST is required
to drive the high-side MOSFET gate. When LX
is driven low (through the low-side MOSFET),
the BST capacitor is internally charged. The
voltage at BST is applied to the high-side
MOSFET gate to turn it on, and maintains that
voltage until the high-side MOSFET is turned
off and the low-side MOSFET is turned on, and
the cycle repeats. Connect a 10nF or greater
capacitor from BST to SW to drive the high-side
MOSFET gate.
At the beginning of each cycle, the high-side
N-Channel MOSFET is turned on, forcing the
inductor current to rise. The current at the drain
of the high-side MOSFET is internally
measured and converted to a voltage by the
current sense amplifier.
That voltage is compared to the error voltage at
COMP. When the inductor current rises
APPLICATION INFORMATION
C7
10nF
INPUT
2.6V to 15V
7
5
1
3
C5
10nF
C4
OPEN
C3
3.3nF
6
VIN
BST
LX
RUN
MP2106
SS
COMP
VREF
C6
10nF
4
FB
8
OUTPUT
1.8V / 1.5A
2
SGND PGND
10
9
MP2106_TAC_F02
Figure 2—Typical Application Circuit
MP2106 Rev. 1.81
3/7/2011
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MP2106 – 1.5A, 15V, 800kHz SYNCHRONOUS BUCK CONVERTER
APPLICATION INFORMATION
Where R2 is the high-side resistor, VOUT is the
output voltage and R1 is the low-side resistor.
Internal Low-Dropout Regulator
The internal power to the MP2106 is supplied
from the input voltage (VIN) through an internal
2.4V low-dropout linear regulator, whose output
is VREF. Bypass VREF to SGND with a 10nF
or greater capacitor for proper operation. The
internal regulator can not supply more current
than is required to operate the MP2106.
Therefore, do not apply any external load to
VREF.
Selecting the Input Capacitor
The input current to the step-down converter is
discontinuous, and so a capacitor is required to
supply the AC current to the step-down
converter while maintaining the DC input
voltage. A low ESR capacitor is required to
keep the noise at the IC to a minimum. Ceramic
capacitors are preferred, but tantalum or low
ESR electrolytic capacitors may also suffice.
Soft-Start
The MP2106 includes a soft-start timer that
slowly ramps the output voltage at startup to
prevent excessive current at the input.
When power is applied to the MP2106, and
RUN is asserted, a 2µA internal current source
charges the external capacitor at SS. As the
capacitor charges, the voltage at SS rises. The
MP2106 internally limits the feedback threshold
voltage at FB to that of the voltage at SS. This
forces the output voltage to rise at the same
rate as the voltage at SS, forcing the output
voltage to ramp linearly from 0V to the desired
regulation voltage during soft-start.
The soft-start period is determined by the
equation:
t SS = 0.45 × C5
Where C5 (in nF) is the soft-start capacitor from
SS to GND, and tSS (in ms) is the soft-start
period. Determine the capacitor required for a
given soft-start period by the equation:
C5 = 2.22 × t SS
Use values between 10nF and 22nF for C5 to
set the soft-start period (between 4ms and
10ms).
Setting the Output Voltage (see Figure 2)
Set the output voltage by selecting the resistive
voltage divider ratio. The voltage divider drops
the output voltage to the 0.895V feedback
voltage. Use 10kΩ for the low-side resistor of
the voltage divider. Determine the high-side
resistor by the equation:
The capacitor can be electrolytic, tantalum or
ceramic. Because it absorbs the input switching
current it must have an adequate ripple current
rating. Use a capacitor with RMS current rating
greater than 1/2 of the DC load current.
For stable operation, place the input capacitor
as close to the IC as possible. A smaller high
quality 0.1µF ceramic capacitor may be placed
closer to the IC with the larger capacitor placed
further away. If using this technique, it is
recommended that the larger capacitor be a
tantalum or electrolytic type. All ceramic
capacitors should be placed close to the
MP2106. For most applications, a 10µF ceramic
capacitor will work.
Selecting the Output Capacitor
The output capacitor (C2) is required to
maintain the DC output voltage. Low ESR
capacitors are preferred to keep the output
voltage ripple to a minimum. The characteristics
of the output capacitor also affect the stability of
the regulation control system. Ceramic,
tantalum, or low ESR electrolytic capacitors are
recommended.
The output voltage ripple is:
VRIPPLE =
⎛
V
VOUT
× ⎜1 − OUT
VIN
f SW × L ⎜⎝
⎞
⎞ ⎛
1
⎟
⎟⎟ × ⎜ R ESR +
⎜
⎟
8
f
C
2
×
×
SW
⎠ ⎝
⎠
Where VRIPPLE is the output voltage ripple, fSW is
the switching frequency, VIN is the input voltage,
RESR is the equivalent series resistance of the
⎛ V
⎞
R2 = ⎜⎜ OUT − 1⎟⎟ × R1
0
.
895
V
⎝
⎠
MP2106 Rev. 1.81
3/7/2011
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MP2106 – 1.5A, 15V, 800kHz SYNCHRONOUS BUCK CONVERTER
output capacitors and fSW is the switching
frequency.
Choose an output capacitor to satisfy the output
ripple requirements of the design. A 22µF
ceramic capacitor is suitable for most
applications.
Selecting the Inductor
The inductor is required to supply constant
current to the output load while being driven by
the switched input voltage. A larger value
inductor results in less ripple current that will
result in lower output ripple voltage. However,
the larger value inductor is likely to have a
larger physical size and higher series
resistance. Choose an inductor that does not
saturate under the worst-case load conditions.
A good rule for determining the inductance is to
allow the peak-to-peak ripple current to be
approximately 30% to 40% of the maximum
load current. Make sure that the peak inductor
current (the load current plus half the peak-topeak inductor ripple current) is below 2.5A to
prevent loss of regulation due to the current
limit.
Calculate the required inductance value by the
equation:
L=
VOUT × (VIN − VOUT )
VIN × f SW × ∆I
Where ∆I is the peak-to-peak inductor ripple
current. It is recommended to choose ∆I to be
30%~40% of the maximum load current.
Compensation
The system stability is controlled through the
COMP pin. COMP is the output of the internal
transconductance error amplifier. A series
capacitor-resistor combination sets a pole-zero
combination to control the characteristics of the
control system.
The DC loop gain is:
⎛ V
A VDC = ⎜⎜ FB
⎝ VOUT
voltage at COMP) and RLOAD is the load
resistance:
R LOAD =
VOUT
I OUT
Where IOUT is the output load current.
The system has 2 poles of importance, one is
due to the compensation capacitor (C3), and
the other is due to the load resistance and the
output capacitor (C2), where:
fP1 =
GEA
2π × A VEA × C3
P1 is the first pole, and GEA is the error amplifier
transconductance (300µA/V) and
fP 2 =
1
2π × R LOAD × C2
The system has one zero of importance, due to
the compensation capacitor (C3) and the
compensation resistor (R3). The zero is:
f Z1 =
1
2π × R3 × C3
If large value capacitors with relatively high
equivalent-series-resistance (ESR) are used,
the zero due to the capacitance and ESR of the
output capacitor can be compensated by a third
pole set by R3 and C4. The pole is:
fP3 =
1
2π × R3 × C4
The system crossover frequency (the frequency
where the loop gain drops to 1, or 0dB, is
important. Set the crossover frequency to below
one tenth of the switching frequency to insure
stable operation. Lower crossover frequencies
result in slower response and worse transient
load recovery. Higher crossover frequencies
degrade the phase and/or gain margins and
can result in instability.
⎞
⎟ × A VEA × G CS × R LOAD
⎟
⎠
Where VFB is the feedback voltage, AVEA is the
transconductance error amplifier voltage gain,
GCS is the current sense transconductance
(roughly the output current divided by the
MP2106 Rev. 1.81
3/7/2011
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MP2106 – 1.5A, 15V, 800kHz SYNCHRONOUS BUCK CONVERTER
Table 1—Compensation Values for Typical
Output Voltage/Capacitor Combinations
Determine the value by the equation:
C4 =
C2 × R ESR(max)
R3
VOUT
C2
R3
C3
C4
1.8V
2.5V
3.3V
22µF Ceramic
22µF Ceramic
22µF Ceramic
47µF Tantalum
(300mΩ)
47µF Tantalum
(300mΩ)
47µF Tantalum
(300mΩ)
6.8kΩ
9.1kΩ
12kΩ
3.3nF
2.2nF
1.8nF
None
None
None
Where RESR(MAX) is the maximum ESR of the
output capacitor.
13kΩ
2nF
1nF
18kΩ
1.2nF
750pF
An external bootstrap diode may enhance the
efficiency of the regulator, the applicable
conditions of external BST diode are:
24kΩ
1nF
560pF
1.8V
2.5V
3.3V
Choosing the Compensation Components
The values of the compensation components
given in Table 1 yield a stable control loop for
the given output voltage and capacitor. To
optimize the compensation components for
conditions not listed in Table 1, use the
following procedure.
Choose the compensation resistor to set the
desired crossover frequency. Determine the
value by the following equation:
R3 =
2π × C2 × VOUT × f C
G EA × G CS × VFB
Where fC is the desired crossover frequency
(preferably 33kHz).
External Boost Diode
z
VOUT=5V or 3.3V; and
z
Duty cycle is high: D=
VOUT
>65%
VIN
In these cases, an external BST diode is
recommended from the output of the voltage
regulator to BST pin, as shown in Fig.3
External BST Diode
IN4148
BST
MP2106
SW
CBST
L
+
COUT
5V or 3.3V
Figure 3—Add Optional External Bootstrap
Diode to Enhance Efficiency
The recommended external BST diode is
IN4148, and the BST cap is 0.1~1µF.
Choose the compensation capacitor to set the
zero below one fourth of the crossover
frequency. Determine the value by the following
equation:
C3 >
2
π × R3 × f C
Determine if the second compensation
capacitor, C4 is required. It is required if the
ESR zero of the output capacitor happens at
less than half of the switching frequency. Or:
π × C2 × R ESR × f SW > 1
If this is the case, then add the second
compensation capacitor.
MP2106 Rev. 1.81
3/7/2011
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10
MP2106 – 1.5A, 15V, 800kHz SYNCHRONOUS BUCK CONVERTER
PCB Layout Guide
PCB layout is very important to achieve stable
operation. It is highly recommended to duplicate
EVB layout for optimum performance.
If change is necessary, please follow these
guidelines and take Figure4 for reference.
1)
Keep the path of switching current short and
minimize the loop area formed by Input cap,
high-side MOSFET and low-side MOSFET.
2)
Bypass ceramic capacitors are suggested to
be put close to the VIN Pin.
3)
Ensure all feedback connections are short
and direct. Place the feedback resistors and
compensation components as close to the
chip as possible.
4)
Route SW away from sensitive analog areas
such as FB.
5)
Connect IN, SW, and especially GND
respectively to a large copper area to cool
the chip to improve thermal performance and
long-term reliability.
Top Layer
Bottom Layer
Figure4—PCB Layout (Double Layers)
MP2106 Rev. 1.81
3/7/2011
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
11
MP2106 – 1.5A, 15V, 800kHz SYNCHRONOUS BUCK CONVERTER
PACKAGE INFORMATION
MSOP10
0.114(2.90)
0.122(3.10)
6
10
0.114(2.90)
0.122(3.10)
PIN 1 ID
(NOTE 5)
0.007(0.18)
0.011(0.28)
0.187(4.75)
0.199(5.05)
5
1
0.0197(0.50)BSC
BOTTOM VIEW
TOP VIEW
GAUGE PLANE
0.010(0.25)
0.030(0.75)
0.037(0.95)
0.043(1.10)MAX
SEATING PLANE
0.002(0.05)
0.006(0.15)
FRONT VIEW
0o-6o
0.016(0.40)
0.026(0.65)
0.004(0.10)
0.008(0.20)
SIDE VIEW
NOTE:
0.181(4.60)
0.040(1.00)
0.012(0.30)
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS
IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURR.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) PIN 1 IDENTIFICATION HAS THE HALF OR FULL CIRCLE OPTION.
6) DRAWING MEETS JEDEC MO-817, VARIATION BA.
7) DRAWING IS NOT TO SCALE.
0.0197(0.50)BSC
RECOMMENDED LAND PATTERN
MP2106 Rev. 1.81
3/7/2011
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
12
MP2106 – 1.5A, 15V, 800kHz SYNCHRONOUS BUCK CONVERTER
QFN10 (3mm x 3mm)
2.90
3.10
0.30
0.50
PIN 1 ID
MARKING
0.18
0.30
2.90
3.10
PIN 1 ID
INDEX AREA
1.45
1.75
PIN 1 ID
SEE DETAIL A
10
1
2.25
2.55
0.50
BSC
5
6
TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION A
R0.20 TYP.
PIN 1 ID OPTION B
R0.20 TYP.
0.80
1.00
0.20 REF
0.00
0.05
SIDE VIEW
DETAIL A
NOTE:
2.90
0.70
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VEED-5.
5) DRAWING IS NOT TO SCALE.
1.70
0.25
2.50
0.50
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP2106 Rev. 1.81
3/7/2011
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
13
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