MP2263
The Future of Analog IC Technology
Wide Input 3.3V - 30V, 3A, 12µA IQ,
Synchronous, Step-Down Converter with
External Soft Start and Power Good
in Small 2x3mm QFN Package
DESCRIPTION
FEATURES
The MP2263 is a frequency-programmable
(350kHz to 2.5MHz), synchronous, step-down,
switching regulator with integrated, internal,
high-side and low-side power MOSFETs. The
MP2263 provides 3A of highly efficient output
current with current-mode control for fast loop
response.
The wide 3.3V-to-30V input range accommodates
a variety of step-down applications. A 1μA
shutdown mode quiescent current allows the
MP2263 to be used in battery-powered
applications.
High power conversion efficiency over a wide
load range is achieved by scaling down the
switching frequency at light-load condition to
reduce switching and gate driving losses.
An open-drain power good signal indicates the
output.
APPLICATIONS
Frequency foldback helps prevent inductor
current runaway during start-up. Thermal
shutdown provides reliable and fault-tolerant
operation. High-duty cycle and low drop-out
mode are provided for battery-powered systems.
The MP2263 is available
(2mmx3mm) package.
in
a
QFN-15
Wide 3.3V to 30V Operating Voltage Range
3A Continuous Output Current
1μA Low Shutdown Supply Current
12μA Sleep Mode Quiescent Current
90mΩ/38mΩ High-Side/Low-Side RDS(ON) for
Internal Power MOSFETs
350kHz to 2.5MHz Programmable Switching
Frequency
Power Good Output
External Soft Start
80ns Minimum On Time
Selectable Forced PWM Mode and Auto
PFM/PWM Mode
Low Dropout Mode
Hiccup Over-Current Protection (OCP)
Available in a QFN-15 (2mmx3mm)
Package
Battery-Powered Systems
Smart Homes
Wide Input Range Power Supplies
Standby Power Supplies
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under Quality
Assurance. “MPS” and “The Future of Analog IC Technology” are registered
trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
100
95
90
85
80
75
70
65
60
55
50
0.001
MP2263 Rev. 1.02
3/1/2019
0.01
0.1
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1
10
1
MP2263 – 30V, 3A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number*
Package
Top Marking
MP2263GD
QFN-15 (2mmx3mm)
See Below
* For Tape & Reel, add suffix –Z (e.g. MP2263GD–Z)
TOP MARKING
ATL: Product code of MP2263GD
Y: Year code
WW: Week code
LLL: Lot number
PACKAGE REFERENCE
TOP VIEW
QFN-15 (2mmx3mm)
MP2263 Rev. 1.02
3/1/2019
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2
MP2263 – 30V, 3A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance (4)
Supply voltage (VIN) ........................ -0.3V to 40V
Switch voltage (VSW) ................-0.6V (-5V < 5ns)
to VIN + 0.3V (43V < 5ns)
BST voltage (VBST) ..................... VSW (MAX) + 6.5V
EN voltage (VEN) ............................. -0.3V to 40V
BIAS voltage ................................... -0.3V to 20V
All other pins ..................................... -0.3V to 6V
Continuous power dissipation (TA = +25°C) (2)
QFN-15 (2mmx3mm) .................................. 1.7W
Operating junction temperature ................ 150°C
Lead temperature...................................... 260°C
Storage temperature ................... -65°C to 150°C
QFN-15 (2mmx3mm) .............. 70 ....... 15 ... °C/W
Recommended Operating Conditions (3)
θJA
θJC
NOTES:
1) Absolute maximum ratings are rated under room temperature
unless otherwise noted. Exceeding these ratings may damage
the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation
produces an excessive die temperature, causing the regulator
to go into thermal shutdown. Internal thermal shutdown
circuitry protects the device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
Supply voltage (VIN) ......................... 3.3V to 30V
Operating junction temp (TJ) .....-40°C to +125°C
MP2263 Rev. 1.02
3/1/2019
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3
MP2263 – 30V, 3A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 12V, VEN = 2V, TJ = -40°C to +125°C(5), typical values are at TJ = +25°C, unless otherwise
noted.
Parameter
VIN under-voltage lockout
threshold rising
VIN under-voltage lockout
threshold hysteresis
Symbol
INUVVth
Min
Typ
Max
Units
2.5
2.8
3.2
V
INUVHYS
VIN quiescent current
IQ
VIN shutdown current
ISHDN
FB voltage
VFB
Switching frequency
FSW
Minimum on time(6)
Switch current limit
Valley current limit
ZCD current
LS reverse current limit
Switch leakage current
HS switch on resistance
LS switch on resistance
Condition
TON_MIN
ILIMIT_HS
ILIMIT_LS
IZCD
ILIMIT_REVERSE
ISW_LKG
RON_HS
RON_LS
150
mV
FB = 0.85V, no load,
sleep mode
12
µA
EN = 0V
1
5
µA
800
800
500
1000
2500
80
5.2
4.4
0.1
3
0.01
90
38
816
808
575
1150
2750
mV
mV
kHz
kHz
kHz
ns
A
A
A
A
µA
mΩ
mΩ
TJ = -40°C to +125°C
TJ = 25°C
RFREQ = 164k
RFREQ = 82k
RFREQ = 27k
Duty cycle = 40%
VOUT = 3.3V, L = 4.7µH
784
792
425
850
2250
4.1
3.1
VBST - VSW = 5V
6.7
5.7
1
VCC 0.4
MODE high level
MODE low level
MODE internal pull-down
resistance
Soft-start current
EN rising threshold voltage
EN hysteresis voltage
V
0.4
RMODE
ISS
VSS = 0.8V
0.9
VEN_RISING
1.55
MΩ
10
µA
1.05
1.2
120
VEN_HYS
V
V
mV
PG OV rising (VFB/0.8V)
PGVth_OV_Rising
105
110
115
%
PG OV falling (VFB/0.8V)
PGVth_OV_Falling
113
118
123
%
PG UV rising (VFB/0.8V)
PGVth_UV_Rising
85
90
95
%
PG UV falling (VFB/0.8V)
PGVth_UV_Falling
79
84
89
%
0.2
0.4
V
PG output voltage low
VPG_LOW
PG deglitch timer rising
TPG_DEGLITCH_Rising
34
µs
TPG_DEGLITCH_Falling
57
µs
TSD
170
20
°C
°C
PG deglitch timer falling
shutdown(6)
Thermal
Thermal shutdown hysteresis(6)
ISINK = 2mA
TSD_HYS
NOTES:
5) Not tested in production. Guaranteed by over-temperature correlation.
6) Guaranteed by characterization test.
MP2263 Rev. 1.02
3/1/2019
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4
MP2263 – 30V, 3A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
PIN FUNCTIONS
Pin #
QFN-15
(2mmx3mm)
Name
1
MODE
2
VIN
3, 8
PGND
4
EN
Enable. Pull EN below the specified threshold to shut down the MP2263. Pull EN
above the specified threshold to enable the MP2263.
5
NC
No connection. NC must be left floating.
6
PG
Power good output. The output of PG is an open drain.
7
BIAS
9
SW
10
BST
11
VCC
12
AGND
13
SS
14
FB
15
FREQ
MP2263 Rev. 1.02
3/1/2019
Description
Mode selection. Pull MODE low or float MODE to set auto PFM/PWM mode; pull
MODE to VCC to set forced PWM mode. MODE is pulled down internally. Select
MODE before the part starts up.
Input supply. VIN supplies power to all of the internal control circuitries and the power
switch connected to SW. A decoupling capacitor to ground must be placed close to
VIN to minimize switching spikes.
Power ground.
Bias input. BIAS must be connected to GND if the bias function is not used.
Switch node. SW is the output of the internal power switch.
Bootstrap. BST is the positive power supply for the high-side MOSFET driver
connected to SW. Connect a bypass capacitor between BST and SW.
Internal LDO output. VCC supplies power to the internal control circuit and gate
drivers. A decoupling capacitor to ground is required close to VCC.
Analog ground.
Soft-start input. Place a capacitor from SS to GND to set the soft-start period. The
MP2263 sources 10µA from SS to the soft-start capacitor at start-up. As the SS
voltage rises, the feedback threshold voltage increases to limit the inrush current
during start-up.
Feedback input. Connect FB to the center point of the external resistor divider. The
feedback threshold voltage is 0.8V.
Switching frequency set. Connect a resistor from FREQ to ground to set the
switching frequency.
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5
MP2263 – 30V, 3A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VOUT = 3.3V, L = 4.7μH, FSW = 500kHz, CSS = 12nF, TA = 25°C, BIAS is connected to GND,
unless otherwise noted.
95
90
85
100
100
100
VIN=5V
95
VIN=12V
95
90
90
VIN=12V
85
VIN=19V
80
80
VIN=6.5V
75
70
65
60
0.001
0.01
0.1
1
LOAD CURRENT (A)
10
75
70
70
65
65
60
60
55
50
0.001
55
100
95
95
VIN=5V
90
80
75
VIN=19V
VIN=12V
0.01
0.1
1
LOAD CURRENT (A)
10
50
0.001
90
80
80
75
VIN=19V
VIN=12V
65
65
60
60
60
55
55
55
50
0.001
50
0.001
0.2
0.15
0.15
0.1
0.1
IOUT=0.01A
-0.15
-0.2
0
5
10
15
20
INPUT VOLTAGE (V)
MP2263 Rev. 1.02
3/1/2019
25
VIN=12V
VIN=19V
20
25
30
VOUT=5V
15
VIN=5V
VOUT=3.3V
10
-0.1
-0.2
10
30
-0.05
-0.15
0.01
0.1
1
LOAD CURRENT (A)
Case Temperature Rise
vs. Load Current
0
IOUT=3A
-0.1
50
0.001
VIN=12V
35
0.05
IOUT=1.5A
-0.05
10
IOUT=0.01A to 3A
0.2
0
1
0.01
0.1
LOAD CURRENT (A)
Load Regulation
VIN=4.5V to 30V
VIN=19V
70
65
Line Regulation
10
VIN=5V
85 VIN=12V
70
0.05
0.01
0.1
1
LOAD CURRENT (A)
85
70
10
VIN=19V
95
VIN=5V
75
0.01
0.1
1
LOAD CURRENT (A)
VIN=12V
100
90
85
80
VIN=19V
75
100
VIN=5V
85
5
0
0.5
1
1.5
2
2.5
LOAD CURRENT (A)
3
0
0
0.5
1
1.5
2
2.5
3
3.5
LOAD CURRENT (A)
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6
MP2263 – 30V, 3A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VOUT = 3.3V, L = 4.7μH, FSW = 500kHz, CSS = 12nF, TA = 25°C, BIAS is connected to GND,
unless otherwise noted.
14
5.6
1.6
1.4
13
1.2
5.4
12
5.2
1
0.8
11
0.6
10
5
0.4
9
4.8
0
10 20 30 40 50 60 70 80
60
0.2
0
5
10
15
20
25
30
0
0
5
10
15
20
25
30
180
140
40
100
20
60
20
0
-20
-20
-60
-100
-40
-60
1000
8
10000
MP2263 Rev. 1.02
3/1/2019
100000
-140
-180
1000000
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7
MP2263 – 30V, 3A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VOUT = 3.3V, L = 4.7μH, FSW = 500kHz, CSS = 12nF, TA = 25°C, BIAS is connected to GND,
unless otherwise noted.
MP2263 Rev. 1.02
3/1/2019
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8
MP2263 – 30V, 3A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VOUT = 3.3V, L = 4.7μH, FSW = 500kHz, CSS = 12nF, TA = 25°C, BIAS is connected to GND,
unless otherwise noted.
MP2263 Rev. 1.02
3/1/2019
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MP2263 – 30V, 3A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
BLOCK DIAGRAM
Figure 1: Functional Block Diagram
MP2263 Rev. 1.02
3/1/2019
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MP2263 – 30V, 3A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
OPERATION
The MP2263 is a synchronous, step-down,
switching regulator with integrated, internal, highside and low-side power MOSFETs. It provides
3A of highly efficient output current with currentmode control. The MP2263 has a wide input
voltage range, programmable 350kHz to 2.5MHz
switching frequency, external soft start, and
current limit. Its very low operational quiescent
current makes it suitable for battery-powered
applications.
PWM Control
At moderate-to-high output currents, the MP2263
operates in a fixed-frequency, peak-currentcontrol mode to regulate the output voltage. A
PWM cycle is initiated by the internal clock. At
the rising edge of the clock, the high-side power
MOSFET (HS-FET) turns on and remains on until
its current reaches the value set by the COMP
voltage (VCOMP). When the high-side power
switch is off, the low-side MOSFET (LS-FET)
turns on and remains on until the next cycle
begins. If the current in the HS-FET does not
reach the COMP-set current value in one PWM
period, the HS-FET remains on, saving a turn-off
operation.
Advanced Asynchronous Mode (AAM)
The MP2263 employs advanced asynchronous
mode (AAM) functionality to optimize efficiency
during light-load or no-load conditions. AAM is
selectable. AAM is enabled by connecting MODE
to a low level or floating MODE. AAM is disabled
by connecting MODE to a high level.
When AAM is enabled, the MP2263 first enters
non-synchronous operation for as long as the
inductor current approaches zero at light load. If
the load is further decreased or is at no load,
VCOMP is below VAAM, and the MP2263 enters
AAM or sleep mode, which consumes very low
quiescent current to improve light-load efficiency
further.
In AAM, the internal clock is reset whenever
VCOMP crosses over VAAM. The crossover time is
taken as the benchmark for the next clock. When
the load increases, and the DC value of VCOMP is
higher than VAAM, the operation mode is DCM or
CCM, which have a constant switching frequency.
MP2263 Rev. 1.02
3/1/2019
Figure 2: AAM and PWM Mode
The MP2263 has a mode selection function. Pull
MODE low or float MODE to set auto PFM/PWM
mode; pull MODE to VCC to set forced PWM
mode. MODE is pulled down internally. Select
MODE before the part starts up.
Error Amplifier (EA)
The error amplifier (EA) compares the FB voltage
with the internal reference (typically 0.8V) and
outputs a current proportional to the difference
between the two. This output current is then used
to charge the internal compensation network to
form VCOMP, which is used to control the power
MOSFET current.
Bias and VCC Regulator
Most of the internal circuitries are powered by the
internal regulator. The MP2263 has two internal
regulators (see Figure 3). The regulator LDO1
takes the VIN input and operates in the full VIN
range. When VIN is greater than 5.0V, the output
of the regulator is in full regulation, and VCC is
5V. When VIN is lower than 5V, the output
degrades.
Another regulator, LDO2, is powered by BIAS.
Connect BIAS to an external power source. Keep
the BIAS voltage higher than 4.8V. VCC and the
internal circuit are powered by BIAS. When VBIAS
is greater than 5V, the output of the regulator is
in full regulation, and VCC is 5V. When VBIAS is
lower than 5V, the output degrades.
LDO2 is enabled when VBIAS > 4.8V. Once LDO2
is enabled, LDO1 is disabled. For a 5V output
application, connect BIAS to VOUT for improved
efficiency. The diode (D1) between BIAS and the
internal circuit is used for current reverse
blocking. Since LDO1 has no reverse block
function, VBIAS must be less than VIN. Connect
BIAS to GND if BIAS is not used.
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11
MP2263 – 30V, 3A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
VIN
EN1
LDO1
BIAS
EN2
LDO2
D1
VCC
Figure 3: VCC Regulator
Bootstrap Charging
The bootstrap capacitor is charged and regulated
to about 5V by the dedicated internal bootstrap
regulator. When the voltage between the BST
and SW nodes is lower than its regulation, a
PMOS connected from VCC to BST is turned on.
The charging current path is from VCC to BST to
SW.
The effective duty cycle during dropout of the
regulator is mainly influenced by the voltage
drops across the power MOSFET, inductor
resistance, low-side diode and printed circuit
board resistance.
Enable Control (EN)
EN is a digital control pin that turns the regulator
on and off.
EN can be enabled by an external logic H/L
signal. When EN is pulled below the threshold
voltage, the chip enters the lowest shutdown
current mode. Forcing EN above the EN
threshold voltage turns on the MP2263.
For the programmable VIN under-voltage lockout
(UVLO), with a high enough VIN, the MP2263
can be enabled and disabled by EN (see Figure
4). This circuit can generate a programmable VIN
UVLO and hysteresis.
When the HS-FET is on, VIN is about equal to
SW, so the bootstrap capacitor cannot be
charged.
At higher duty cycle operation conditions, the
time period available to the bootstrap charging is
less, so the bootstrap capacitor may not be
charged sufficiently. In case the internal circuit
does not have sufficient voltage or time to charge
the bootstrap capacitor, extra external circuitry
can be used to ensure that the bootstrap voltage
is in the normal operation region.
Low-Dropout Operation
To improve dropout, the MP2263 is designed to
operate at almost 100% duty cycle for as long as
the BST to SW voltage is greater than 2.5V.
When the voltage from BST to SW drops below
2.5V, the HS-FET is turned off using an UVLO
circuit, which allows the LS-FET to conduct and
refresh the charge on the BST capacitor. In DCM
or PSM, the LS-FET is forced on to refresh the
BST voltage.
Since the supply current sourced from the BST
capacitor is low, the HS-FET can remain on for
more switching cycles than are required to
refresh the capacitor. Therefore, the effective
duty cycle of the switching regulator is high.
MP2263 Rev. 1.02
3/1/2019
Figure 4: Enable Divider Circuit
Frequency Programmable
The
MP2263
oscillating
frequency
is
programmed by an external resistor (Rfreq) from
the FREQ pin to ground.
The approximate value of Rfreq can be calculated
with Equation (1):
R freq (k)
86500
6.5
fs (kHz)
(1)
Soft Start (SS)
Soft start (SS) is implemented to prevent the
converter output voltage from overshooting
during start-up.
When the soft-start period begins, an internal
current source begins charging the external softstart capacitor. After the soft-start voltage
charges higher than the internal offset voltage
(typically 600mV), VOUT starts up.
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MP2263 – 30V, 3A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
When (SS - Voffest)/1.125 is lower than the internal
reference (REF), the error amplifier uses (SS Voffest)/1.125 as the reference. When (SS Voffest)/1.125 is higher than REF, REF regains
control.
CSS can be calculated with Equation (2):
Css(nF)
Tss(ms) Iss(A)
1.125 Vref (V)
(2)
The minimum TSS is 800µs, typically.
Pre-Bias Start-Up
The MP2263 is designed for monotonic start-up
into pre-biased loads. If the output is pre-biased
to a certain voltage during start-up, the BST
voltage is refreshed and charged. The voltage on
the soft-start capacitor is also charged. If the BST
voltage exceeds its rising threshold voltage, and
the soft-start capacitor voltage exceeds
1.125*VFB+Voffest, the MP2263 begins working
normally.
Thermal Shutdown
Thermal shutdown is implemented to prevent the
chip from running away thermally. When the
silicon die temperature is higher than its upper
threshold, the power MOSFETs shut down.
When the temperature is lower than its lower
threshold, thermal shutdown is removed, and the
chip is enabled again.
Current Comparator and Current Limit
The power MOSFET current is sensed accurately
via a current sense MOSFET. This current is fed
to the high-speed current comparator for currentmode control purposes. The current comparator
uses this sensed current as one of its inputs.
When the HS-FET is turned on, the comparator
is first blanked until the end of the turn-on
transition to avoid noise. The comparator then
compares the power switch current with VCOMP.
When the sensed current is higher than VCOMP,
the comparator outputs low to turn off the HSFET. The maximum current of the internal power
MOSFET is limited cycle-by-cycle internally.
MP2263 Rev. 1.02
3/1/2019
Hiccup Protection
When the output is shorted to ground, causing
the output voltage to drop below 70% of its
nominal output, the IC shuts down momentarily
and begins discharging the soft-start capacitor.
The IC restarts with a full soft start when the softstart capacitor is fully discharged. This hiccup
process is repeated until the fault is removed.
Start-Up and Shutdown
If both VIN and EN are higher than their
respective thresholds, the chip starts up. The
reference block starts first, generating stable
reference voltages and currents, and then the
internal regulator is enabled. The regulator
provides a stable supply for the rest of the
circuitries.
When the internal supply rail is up, an internal
timer holds the power MOSFET off for about
50µs to blank the start-up glitches. When the
soft-start block is enabled, the SS output is held
low to ensure that the rest of the circuitries are
ready before slowly ramping up.
Three events can shut down the chip: EN low,
VIN low, and thermal shutdown. In the shutdown
procedure, the signaling path is blocked first to
avoid any fault triggering. VCOMP and the internal
supply rail are then pulled down. The floating
driver is not subject to this shutdown command,
but its charging path is disabled.
Power Good Output
The MP2263 has an open-drain pin as the power
good indicator (PG). PG can indicate under
voltage (UV) and over voltage (OV). Pull PG up
to VCC through a 100kΩ resistor. In the UV
condition, when VFB exceeds 90% of VREF, PG
goes high. If VFB drops below 84% of VREF, an
internal MOSFET pulls PG down to ground. In
the OV condition, when VFB exceeds 118% of
VREF, PG goes low. If VFB goes below 110% of
VREF, PG goes high.
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MP2263 – 30V, 3A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
APPLICATION INFORMATION
Setting the Output
The external resistor divider is used to set the
output voltage (see the Typical Application on
page 1). Refer to Table 1 to choose R1. R2 can
then be calculated with Equation (3):
R2
R1
VOUT
0.8V
(3)
1
The feedback network is highly recommended
(see Figure 5).
Figure 5: Feedback Network
Table 1 lists the recommended feedback
network parameters for common output
voltages.
Table 1: Recommended Parameters for Common
Output Voltages(7)
VOUT (V) R1 (kΩ) R2 (kΩ) Cf (pF)
1.05
470
1500
5.6
1.2
750
1500
5.6
1.8
1000
806
5.6
2.5
1000
470
5.6
3.3
1000
324
5.6
5
1000
191
5.6
NOTE:
7) The recommended parameters are based on a 500kHz
switching frequency. A different input voltage, output inductor
value, or output capacitor value may affect the selection of R1,
R2, and Cf. For additional component parameters, please
refer to the Typical Application Circuits on pages 16 and 17.
Selecting the Inductor
For most applications, use a 1µH to 22µH
inductor with a DC current rating at least 25%
higher than the maximum load current. For the
highest efficiency, use an inductor with a DC
resistance less than 15mΩ. For most designs,
the inductance value can be derived from
Equation (4):
V (VIN VOUT )
(4)
L1 OUT
VIN IL fOSC
Where ∆IL is the inductor ripple current.
MP2263 Rev. 1.02
3/1/2019
Choose the inductor ripple current to be
approximately 30% of the maximum load
current. The maximum inductor peak current
can be calculated with Equation (5):
IL(MAX) ILOAD
IL
2
(5)
Selecting the Input Capacitor
The input current to the step-down converter is
discontinuous and therefore requires a
capacitor to supply AC current while
maintaining the DC input voltage. Use low ESR
capacitors for optimum performance. Ceramic
capacitors with X5R or X7R dielectrics are
recommended because of their low ESR and
small temperature coefficients. For most
applications, use two 10µF capacitors. Since
C1 absorbs the input switching current, it
requires an adequate ripple-current rating. The
RMS current in the input capacitor can be
estimated with Equation (6):
I C1 ILOAD
VOUT VOUT
1
VIN
VIN
(6)
The worst-case condition occurs at VIN = 2VOUT,
shown in Equation (7):
IC1
ILOAD
2
(7)
For simplification, choose an input capacitor
that has an RMS current rating greater than half
the maximum load current.
The input capacitor can be electrolytic, tantalum,
or ceramic. When using electrolytic or tantalum
capacitors, a small, high-quality, ceramic
capacitor (e.g.: 0.1μF) should be placed as
close to the IC as possible. When using
ceramic capacitors, ensure that they have
enough capacitance to provide sufficient charge
to prevent excessive voltage ripple at input. The
input voltage ripple caused by capacitance can
be estimated with Equation (8):
VIN
ILOAD
V
V
OUT 1 OUT
fS C1 VIN
VIN
(8)
Selecting the Output Capacitor
The output capacitor (C2) maintains the DC
output voltage. Use ceramic, tantalum, or low
ESR electrolytic capacitors. For best results,
use low ESR capacitors to keep the output
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14
MP2263 – 30V, 3A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
VOUT
(9)
VOUT VOUT
1
1
RESR
fS L1
VIN
8 fS C2
To achieve better performance, use four-layer
boards. Figure 6 shows the top and bottom
layers (Inner 1 and Inner 2 are both GND).
GND
Where L1 is the inductor value, and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
For ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency, and the capacitance causes the
majority of the output voltage ripple. For
simplification, the output voltage ripple can be
estimated with Equation (10):
∆VOUT
V
VOUT
1 OUT
VIN
8 fS 2 L1 C2
(10)
VIN
VOUT
GND
Top Layer
RESR
(11)
PG
VOUT
V
1 OUT
fS L1
VIN
EN
∆VOUT
VCC
For tantalum or electrolytic capacitors, the ESR
dominates the impedance at the switching
frequency. For simplification, the output ripple
can be approximated with Equation (11):
VOUT
voltage ripple low. The output voltage ripple can
be estimated with Equation (9):
The characteristics of the output capacitor
affect the stability of the regulation system. The
MP2263 can be optimized for a wide range of
capacitance and ESR values.
PCB Layout Guidelines (8)
Efficient PCB layout is critical for stable
operation. For best results, refer to Figure 6 and
follow the guidelines below.
1) Keep the connection of the input ground
and GND as short and wide as possible.
2) Keep the connection of the input capacitor
and IN as short and wide as possible.
3) Ensure all feedback connections are short
and direct.
4) Place
the
feedback
resistors
and
compensation components as close to the
chip as possible.
5) Route SW away from sensitive analog
areas, such as FB.
NOTE:
8) The recommended layout is based on Figure 8.
MP2263 Rev. 1.02
3/1/2019
Bottom Layer
Figure 6: Sample PCB Layout
Design Example
Table 2 shows a design example following the
application guidelines for the specifications
below:
Table 2: Design Example
VIN
12V
VOUT
3.3V
Io
3A
The detailed application schematic is shown in
Figure 8. The typical performance and circuit
waveforms are shown in the Typical
Performance Characteristics section. For
additional device applications, please refer to
the related evaluation board datasheets.
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15
MP2263 – 30V, 3A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS(9)
Figure 7: VIN = 12V, VOUT = 5V
Figure 8: VIN = 12V, VOUT = 3.3V
Figure 9: VIN = 12V, VOUT = 2.5V
MP2263 Rev. 1.02
3/1/2019
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16
MP2263 – 30V, 3A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS (continued)
Figure 10: VIN = 12V, VOUT = 1.8V
Figure 11: VIN = 12V, VOUT = 1.2V
Figure 12: VIN = 12V, VOUT = 1.05V
NOTE:
8) To use the bias function, connect BIAS to a power source higher than 4.8V. If the bias function is not used, connect BIAS to GND.
MP2263 Rev. 1.02
3/1/2019
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17
MP2263 – 30V, 3A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
PACKAGE INFORMATION
QFN-15 (2mmx3mm)
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP2263 Rev. 1.02
3/1/2019
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