MP2269
The Future of Analog IC Technology
3.3V - 30V, 1A, 12µA IQ,
Synchronous, Step-Down Converter
with External Soft Start and Power Good
in 2x3mm QFN Package
DESCRIPTION
FEATURES
The MP2269 is a frequency-programmable
(350kHz to 2.5MHz), synchronous, step-down,
switching regulator with integrated, internal,
high-side and low-side power MOSFETs. The
MP2269 provides 1A of highly efficient output
current with current-mode control for fast loop
response.
The wide 3.3V to 30V input range
accommodates a variety of step-down
applications. A 1μA shutdown mode quiescent
current allows the MP2269 to be used in
battery-powered applications.
High power conversion efficiency over a wide
load range is achieved by scaling down the
switching frequency at light-load condition to
reduce switching and gate driving losses.
An open-drain power good signal indicates the
output signal. Frequency foldback helps prevent
inductor current runaway during start-up.
Thermal shutdown provides reliable and faulttolerant operation. High duty cycle and low
drop-out mode are provided for batterypowered systems.
The MP2269 is available
(2mmx3mm) package.
in
a
QFN-15
Wide 3.3V to 30V Operating Voltage Range
1A Continuous Output Current
1μA Low Shutdown Supply Current
12μA Sleep Mode Quiescent Current
180mΩ/80mΩ High-Side/Low-Side RDS(ON)
for Internal Power MOSFETs
350kHz to 2.5MHz Programmable Switching
Frequency
Power Good Output
External Soft Start
80ns Minimum On Time
Selectable Forced PWM Mode and Auto
PFM/PWM Mode
Low Dropout Mode
Hiccup Over-Current Protection (OCP)
Available in a QFN-15 (2mmx3mm)
Package
APPLICATIONS
Battery-Powered Systems
Smart Homes
Wide Input Range Power Supplies
Standby Power Supplies
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under Quality
Assurance. “MPS” and “The Future of Analog IC Technology” are registered
trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
100
95
90
85
80
75
70
65
60
55
50
0.001
MP2269 Rev. 1.02
3/5/2019
0.01
0.1
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1
1
MP2269 - 30V, 1A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number*
MP2269GD
Package
QFN-15 (2mmx3mm)
Top Marking
See Below
* For Tape & Reel, add suffix –Z (e.g. MP2269GD–Z)
TOP MARKING
AUH: Product code of MP2269GD
Y: Year code
WW: Week code
LLL: Lot number
PACKAGE REFERENCE
TOP VIEW
QFN-15 (2mmx3mm)
MP2269 Rev. 1.02
3/5/2019
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MP2269 - 30V, 1A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance (4)
Supply voltage (VIN) ....................... -0.3V to 40V
Switch voltage (VSW) ...... -0.3V to VIN (MAX) + 0.3V
BST voltage (VBST) ..................... VSW (MAX) + 6.5V
EN voltage (VEN) ............................. -0.3V to 40V
PG voltage ...................................... -0.3V to 32V
BIAS voltage ................................... -0.3V to 20V
All other pins ..................................... -0.3V to 6V
Continuous power dissipation (TA = +25°C) (2)
QFN-15 (2mmx3mm) .................................. 1.7W
Operating junction temperature ................ 150°C
Lead temperature...................................... 260°C
Storage temperature ................... -65°C to 150°C
QFN-15 (2mmx3mm) ............. 70 ...... 15 ... °C/W
Recommended Operating Conditions (3)
θJA
θJC
NOTES:
1) Absolute maximum ratings are rated under room temperature
unless otherwise noted. Exceeding these ratings may
damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/ θJA. Exceeding the maximum allowable power dissipation
produces an excessive die temperature, causing the regulator
to go into thermal shutdown. Internal thermal shutdown
circuitry protects the device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
Supply voltage (VIN) ........................ 3.3V to 30V
Operating junction temp (TJ) .....-40°C to +125°C
MP2269 Rev. 1.02
3/5/2019
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MP2269 - 30V, 1A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 12V, VEN = 2V, TJ = -40°C to +125°C
noted.
Parameter
VIN under-voltage lockout
threshold rising
VIN under-voltage lockout
threshold hysteresis
(5)
Symbol
, typical values are at TJ = +25°C, unless otherwise
Condition
INUVVth
Min
Typ
Max
Units
2.5
2.8
3.2
V
150
mV
FB = 0.85V, no load, sleep
mode
12
µA
EN = 0V
1
5
µA
816
808
575
1150
2750
5
800
800
500
1000
2500
80
2.5
1.35
50
1.5
0.01
180
80
10
15
mV
mV
kHz
kHz
kHz
ns
A
A
mA
A
µA
mΩ
mΩ
µA
0.9
1.05
1.2
V
INUVHYS
VIN quiescent current
IQ
VIN shutdown current
ISHDN
FB voltage
VFB
Switching frequency
FSW
Minimum on time (6)
Switch current limit
Valley current limit
ZCD current
LS reverse current limit
Switch leakage current
HS switch on resistance
LS switch on resistance
Soft-start current
TON_MIN
ILIMIT_HS
ILIMIT_LS
IZCD
ILIMIT_REVERSE
ISW_LKG
RON_HS
RON_LS
ISS
EN rising threshold voltage
TJ = -40°C to +125°C
TJ = 25°C
RFREQ = 164kΩ
RFREQ = 82kΩ
RFREQ = 27kΩ
Duty cycle = 40%
VOUT = 3.3V, L = 6.5µH
VBST-VSW = 5V
VSS = 0.8V
VEN_RISING
EN hysteresis voltage
784
792
425
850
2250
1
110
VEN_HYS
mV
PG OV rising (VFB/0.8V)
PGVth_OV_Rising
105
110
115
%
PG OV falling (VFB/0.8V)
PGVth_OV_Falling
113.5
118
123.5
%
PG UV rising (VFB/0.8V)
PGVth_UV_Rising
85
90
95
%
PG UV falling (VFB/0.8V)
PGVth_UV_Falling
84
89
%
0.2
0.4
V
79
PG output voltage low
VPG_LOW
PG deglitch timer rising
TPG_DEGLITCH_Rising
34
µs
PG deglitch timer falling
TPG_DEGLITCH_Falling
57
µs
TSD
170
TSD_HYS
20
C
°C
Thermal shutdown
(6)
Thermal shutdown hysteresis
(6)
ISINK = 2mA
NOTE:
5) Not tested in production. Guaranteed by over-temperature correlation.
6) Guaranteed by characterization test.
MP2269 Rev. 1.02
3/5/2019
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4
MP2269 - 30V, 1A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
PIN FUNCTIONS
Pin #
QFN-15
(2mmx3mm)
Name
1
MODE
2
VIN
3, 8
PGND
4
EN
Enable. Pull EN below the specified threshold to shut down the MP2269. Pull EN up
above the specified threshold to enable the MP2269.
5
NC
No connection. Leave NC floating.
6
PG
Power good output. The output of PG is an open drain.
7
BIAS
9
SW
10
BST
11
VCC
12
AGND
13
SS
14
FB
15
FREQ
MP2269 Rev. 1.02
3/5/2019
Description
Mode selection. Pull MODE low or float MODE to set auto PFM/PWM mode; pull
MODE high to set forced PWM mode. MODE is pulled down internally. Select MODE
before the part starts up.
Input supply. VIN supplies power to all the internal control circuitries and the power
switch connected to SW. A decoupling capacitor to ground must be placed close to
VIN to minimize switching spikes.
Power ground.
Bias input. BIAS must be connected to GND if the bias function is not being used.
Switch node. SW is the output of the internal power switch.
Bootstrap. BST is the positive power supply for the high-side MOSFET driver
connected to SW. Connect a bypass capacitor between BST and SW.
Internal LDO output. VCC supplies power to the internal control circuit and gate
drivers. A decoupling capacitor to ground is required close to VCC.
Analog ground.
Soft-start input. Place a capacitor from SS to GND to set the soft-start period. The
MP2269 sources 10µA from SS to the soft-start capacitor during start-up. As the SS
voltage rises, the feedback threshold voltage increases to limit inrush current during
start-up.
Feedback input. Connect FB to the center point of the external resistor divider. The
feedback threshold voltage is 0.8V.
Switching frequency set. Connect a resistor from FREQ to ground to set the
switching frequency.
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MP2269 - 30V, 1A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VOUT = 3.3V, L = 6.5μH, FSW = 500kHz, CSS = 12nF, TA = 25°C, BIAS is connected to GND,
unless otherwise noted.
100
100
100
95
95
95
90
90
85
85
90
85
80
80
80
75
75
75
70
70
65
65
60
60
55
50
0.001
55
70
65
60
0.001
0.01
0.1
1
0.01
0.1
1
50
0.001
100
100
100
95
95
95
90
90
90
85
85
85
80
80
80
75
75
75
70
70
70
65
65
65
60
60
60
55
55
55
50
0.001
50
0.001
0.01
0.1
1
0.1
0.01
1
0.1
0.1
1
0.01
0.1
1
4
0.1
0.08
3.5
0.06
0.05
0.04
3
2.5
0.02
0
0
2
-0.02
1.5
-0.04
-0.05
-0.06
1
0.5
-0.08
-0.10
50
0.001
0.01
-0.1
5
MP2269 Rev. 1.02
3/5/2019
10
15
20
25
30
0
0.2
0.4
0.6
0.8
1
00
10 20 30 40 50 60 70 80
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MP2269 - 30V, 1A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VOUT = 3.3V, L = 6.5μH, FSW = 500kHz, CSS = 12nF, TA = 25°C, BIAS is connected to GND,
unless otherwise noted.
14
60
1.6
1.4
13
180
140
40
100
1.2
12
20
1
0.8
11
20
0
0.6
10
60
-20
-20
-60
0.4
9
8
0
5
10
MP2269 Rev. 1.02
3/5/2019
15
20
25
30
0
0
-100
-40
0.2
5
10
15
20
25
30
-60
1000
10000
100000
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-140
-180
1000000
7
MP2269 - 30V, 1A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VOUT = 3.3V, L = 6.5μH, FSW = 500kHz, CSS = 12nF, TA = 25°C, BIAS is connected to GND,
unless otherwise noted.
VOUT/AC
20mV/div.
VIN/AC
100mV/div.
VSW
10V/div.
IL
1A/div.
VOUT
2V/div.
VPG
5V/div.
VIN
5V/div.
VSW
5V/div.
IL
1A/div.
VOUT
2V/div.
VEN
5V/div.
VPG
5V/div.
VOUT/AC
20mV/div.
VIN/AC
50mV/div.
VOUT
2V/div.
VIN
5V/div.
VPG
5V/div.
VSW
10V/div.
VSW
5V/div.
IL
1A/div.
VOUT
2V/div.
VIN
10V/div.
VPG
5V/div.
VSW
5V/div.
IL
2A/div.
VOUT
2V/div.
VPG
5V/div.
VIN
5V/div.
VSW
5V/div.
IL
2A/div.
IL
1A/div.
VOUT
2V/div.
VPG
5V/div.
VEN
5V/div.
VOUT
2V/div.
VEN
5V/div.
VSW
10V/div.
VSW
5V/div.
VPG
5V/div.
VSW
10V/div.
IL
2A/div.
IL
1A/div.
IL
2A/div.
MP2269 Rev. 1.02
3/5/2019
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MP2269 - 30V, 1A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VOUT = 3.3V, L = 6.5μH, FSW = 500kHz, CSS = 12nF, TA = 25°C, BIAS is connected to GND,
unless otherwise noted.
Shutdown through EN
Short-Circuit
Protection Entry
IOUT = 1A
Short-Circuit
Protection Recovery
VOUT
2V/div.
VPG
5V/div.
VEN
5V/div.
VOUT
2V/div.
VOUT
2V/div.
VPG
5V/div.
VPG
5V/div.
VSW
10V/div.
VSW
10V/div.
VSW
10V/div.
IL
1A/div.
IL
1A/div.
IL
1A/div.
Load Transient Response
IOUT = 0.5A to 1A
VOUT/AC
100mV/div.
I OUT
1A/div.
MP2269 Rev. 1.02
3/5/2019
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MP2269 - 30V, 1A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
BLOCK DIAGRAM
Figure 1: Functional Block Diagram
MP2269 Rev. 1.02
3/5/2019
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MP2269 - 30V, 1A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
OPERATION
The MP2269 is a synchronous, step-down,
switching regulator with integrated, internal,
high-side and low-side power MOSFETs. It
provides 1A of highly efficient output current
with current-mode control. The MP2269
features a wide input voltage range,
programmable 350kHz to 2.5MHz switching
frequency, external soft start, and current limit.
Its very low operational quiescent current
makes it suitable
for battery-powered
applications.
PWM Control
At moderate-to-high output currents, the
MP2269 operates in a fixed-frequency, peakcurrent-control mode to regulate the output
voltage. A PWM cycle is initiated by the internal
clock. At the rising edge of the clock, the highside power MOSFET (HS-FET) is turned on
and remains on until its current reaches the
value set by the COMP voltage (VCOMP). When
the high-side power switch is off, the low-side
MOSFET (LS-FET) is turned on and remains on
until the next cycle begins. If the current in the
HS-FET does not reach the COMP-set current
value in one PWM period, the HS-FET remains
on, saving a turn-off operation.
Advanced Asynchronous Mode (AAM)
The MP2269 employs advanced asynchronous
mode (AAM) functionality to optimize efficiency
during light-load or no-load conditions. AAM
mode is selectable. Enable AAM by connecting
MODE to a low level or floating MODE; disable
AAM by connecting MODE to a high level.
If AAM is enabled, the MP2269 first enters nonsynchronous operation for as long as the
inductor current approaches zero at light load. If
the load is further decreased or is at no load,
VCOMP is below VAAM, and the MP2269 enters
AAM or sleep mode, which consumes very low
quiescent current and improves light-load
efficiency further.
In AAM, the internal clock is reset whenever
VCOMP crosses over VAAM, and the crossover
time is taken as the benchmark for the next
clock. When the load increases, and the DC
value of VCOMP is higher than VAAM, the
MP2269 Rev. 1.02
3/5/2019
operation mode is DCM or CCM, which have a
constant switching frequency.
Figure 2: AAM and PWM Mode
The MP2269 has a mode selection function
(see Figure 2). Pull MODE low or float MODE to
set auto PFM/PWM mode. Pull MODE high to
set forced PWM mode. MODE is pulled down
internally. Select MODE before the part starts
up.
Error Amplifier (EA)
The error amplifier (EA) compares the FB
voltage with the internal reference (typically
0.8V) and outputs a current proportional to the
difference between the two. This output current
is used to charge the internal compensation
network to form VCOMP, which is used to control
the power MOSFET current.
BIAS and VCC Regulator
Most of the internal circuitry is powered by the
internal regulator. The MP2269 has two internal
regulators (see Figure 3). The regulator LDO1
takes the VIN input and operates in the full VIN
range. When VIN is greater than 5V, the output
of the regulator is in full regulation, and VCC is
5V. When VIN is lower than 5V, the output
degrades.
Another regulator, LDO2, is powered by BIAS.
Connect BIAS to an external power source, and
keep the BIAS voltage higher than 4.8V. VCC
and the internal circuit are then powered by
BIAS. When VBIAS is greater than 5V, the output
of the regulator is in full regulation, and VCC is
5V. When VBIAS is lower than 5V, the output
degrades. LDO2 is enabled when VBIAS > 4.8V.
Once LDO2 is enabled, LDO1 is disabled. For a
5V output application, BIAS is recommended to
be connected to VOUT for improved efficiency.
The diode (D1) between BIAS and the internal
circuit is used for reverse blocking. Since LDO1
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MP2269 - 30V, 1A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
has no reverse block function, VBIAS must be
less than VIN. Connect BIAS to GND if BIAS is
not used.
VIN
EN1
LDO1
BIAS
EN2
LDO2
D1
VCC
Figure 3: VCC Regulator
Bootstrap Charging
The bootstrap capacitor is charged and
regulated to about 5V by the dedicated internal
bootstrap regulator. When the voltage between
the BST and SW nodes is lower than its
regulation, a PMOS connected from VCC to
BST is turned on. The charging current path is
from VCC to BST to SW. When the HS-FET is
on, VIN is about equal to SW, so the bootstrap
capacitor cannot be charged.
At higher duty cycle operation conditions, the
time period available to the bootstrap charging
is less, so the bootstrap capacitor may not be
charged sufficiently. If the internal circuit does
not have sufficient voltage or time to charge the
bootstrap capacitor, extra external circuitry can
be used to ensure that the bootstrap voltage is
in the normal operation region.
Low-Dropout Operation
To improve dropout, the MP2269 is designed to
operate at almost 100% duty cycle as long as
the BST to SW voltage is greater than 2.5V.
When the voltage from BST to SW drops below
2.5V, the HS-FET is turned off using an undervoltage lockout (UVLO) circuit that allows the
LS-FET to conduct and refresh the charge on
the BST capacitor. In DCM or PSM, the LS-FET
is forced on to refresh the BST voltage.
Since the supply current sourced from the BST
capacitor is low, the HS-FET can remain on for
more switching cycles than are required to
refresh the capacitor, making the effective duty
cycle of the switching regulator high.
MP2269 Rev. 1.02
3/5/2019
The effective duty cycle during the dropout of
the regulator is mainly influenced by the voltage
drops across the power MOSFET, inductor
resistance, low-side diode, and printed circuit
board resistance.
Enable (EN) Control
EN is a digital control pin that turns the
regulator on and off. EN can be enabled by an
external logic H/L signal. When EN is pulled
below the threshold voltage, the chip is put into
the lowest shutdown current mode. Forcing EN
above the EN threshold voltage turns on the
part.
For the programmable VIN under-voltage
lockout (UVLO), with a high-enough VIN, the
chip can be enabled and disabled by EN (see
Figure 4). This circuit can generate a
programmable VIN UVLO and hysteresis.
Figure 4: Enable Divider Circuit
Frequency Programmable
The
MP2269
oscillating
frequency
is
programmed by an external resistor (Rfreq) from
FREQ to ground.
The approximate value of
calculated with Equation (1):
R freq (k)
Rfreq can
86500
6.5
fs (kHz)
be
(1)
Soft Start (SS)
Soft start (SS) is implemented to prevent the
converter output voltage from overshooting
during start-up. When the soft-start period
begins, an internal current source begins
charging the external soft-start capacitor. After
the soft-start voltage (SS) charges higher than
the internal offset voltage (typically 600mV),
VOUT starts up. When (SS - Voffest)/1.125 is lower
than the internal reference (REF), the error
amplifier uses (SS - Voffest)/1.125 as the
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MP2269 - 30V, 1A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
reference. When (SS - Voffest)/1.125 is higher
than REF, REF regains control. CSS can be
calculated with Equation (2):
Css(nF)
Tss(ms) Iss(A)
1.125 Vref (V)
(2)
The minimum TSS is 800µs, typically.
Pre-Bias Start-Up
The MP2269 has been designed for monotonic
start-up into pre-biased loads. If the output is
pre-biased to a certain voltage during start-up,
the BST voltage is refreshed and charged. The
voltage on the soft-start capacitor is charged as
well. If the BST voltage exceeds its rising
threshold voltage, and the soft-start capacitor
voltage exceeds 1.125*VFB+Voffest, the part
begins working normally.
soft-start capacitor is fully discharged. This
hiccup process is repeated until the fault is
removed.
Start-Up and Shutdown
If both VIN and EN are higher than their
respective thresholds, the chip starts up. The
reference block starts first, generating a stable
reference voltage and current, and then the
internal regulator is enabled. The regulator
provides a stable supply for the rest of the
circuitries.
While the internal supply rail starts up, an
internal timer holds the power MOSFET off for
about 50µs to blank the start-up glitches. When
the soft-start block is enabled, it first holds its
SS output low to ensure that the rest of the
circuitries are ready and then ramps up slowly.
Thermal Shutdown
Thermal shutdown is implemented to prevent
the chip from running away thermally. When the
silicon die temperature is higher than its upper
threshold, the power MOSFETs are shut down.
When the temperature is lower than its lower
threshold, thermal shutdown is removed, and
the chip is enabled again.
Three events can shut down the chip: EN low,
VIN low, and thermal shutdown. In the
shutdown procedure, the signaling path is
blocked first to avoid any fault triggering. VCOMP
and the internal supply rail are then pulled down.
The floating driver is not subject to this
shutdown command, but its charging path is
disabled.
Current Comparator and Current Limit
The power MOSFET current is accurately
sensed via a current sense MOSFET. The
current is then fed to the high-speed current
comparator for current-mode control purposes.
The current comparator uses this sensed
current as one of its inputs. When the HS-FET
is turned on, the comparator is first blanked
until the end of the turn-on transition to avoid
noise. Then, the comparator compares the
power switch current with VCOMP.
Power Good (PG) Output
The MP2269 has an open-drain pin as the
power good indicator (PG). PG can indicate
under-voltage (UV) and over-voltage (OV). Pull
PG up to VCC through a 100kΩ resistor. At the
UV condition, when VFB exceeds 90% of VREF,
PG goes high. If VFB goes below 84% of VREF,
an internal MOSFET pulls PG down to ground.
At the OV condition, when VFB exceeds 118% of
VREF, PG goes low. If VFB goes below 110% of
VREF, PG goes high.
When the sensed current is higher than VCOMP,
the comparator outputs low to turn off the HSFET.
The maximum current of the internal power
MOSFET is limited cycle-by-cycle internally.
Hiccup Protection
When the output is shorted to ground, causing
the output voltage to drop below 70% of its
nominal output, the IC shuts down momentarily
and begins discharging the soft-start capacitor.
The IC restarts with a full soft start when the
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MP2269 - 30V, 1A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
APPLICATION INFORMATION
Setting the Output
The external resistor divider is used to set the
output voltage (see Typical Application on page
1). Choose R1 by referring to Table 1. R2 can
then be calculated with Equation (3):
R2
R1
VOUT
0.8V
(3)
1
The feedback network is highly recommended
(see Figure 5).
Figure 5: Feedback Network
Table 1 lists the recommended feedback
network parameters for common output
voltages.
Table 1: Recommended Parameters for Common
Output Voltages(7)
VOUT (V) R1 (kΩ) R2 (kΩ) Cf (pF)
1.05
470
1500
5.6
1.2
750
1500
5.6
1.8
1000
806
5.6
2.5
1000
470
5.6
3.3
1000
324
5.6
5
1000
191
5.6
NOTES:
7) The recommended parameters are based on a 500kHz
switching frequency. A different input voltage, output inductor
value, and output capacitor value may affect the selection of
R1, R2, and Cf. For additional component parameters, please
refer to the Typical Application Circuits on pages 17 and 18.
Selecting the Inductor
For most applications, use a 1µH to 22µH
inductor with a DC current rating at least 25%
higher than the maximum load current. For
highest efficiency, use an inductor with a DC
resistance less than 15mΩ.
MP2269 Rev. 1.02
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For most designs, the inductance value can be
derived from Equation (4):
L1
VOUT (VIN VOUT )
VIN IL fOSC
(4)
Where ∆IL is the inductor ripple current.
Choose the inductor ripple current at
approximately 30% of the maximum load
current. The maximum inductor peak current is
calculated with Equation (5):
IL(MAX) ILOAD
IL
2
(5)
Selecting the Input Capacitor
The input current to the step-down converter is
discontinuous and therefore requires a
capacitor to supply AC current while
maintaining the DC input voltage. Use low ESR
capacitors for the best performance. Ceramic
capacitors with X5R or X7R dielectrics are
recommended because of their low ESR and
small temperature coefficients. For most
applications, use one 10µF capacitor.
Since C1 absorbs the input switching current, it
requires an adequate ripple current rating. The
RMS current in the input capacitor can be
estimated with Equation (6):
I C1 ILOAD
VOUT VOUT
1
VIN
VIN
(6)
The worst-case condition occurs at VIN = 2VOUT,
shown in Equation (7):
I C1
ILOAD
2
(7)
For simplification, choose an input capacitor
with an RMS current rating greater than half of
the maximum load current.
The input capacitor can be electrolytic, tantalum,
or ceramic. When using electrolytic or tantalum
capacitors, a small, high-quality ceramic
capacitor (e.g.: 0.1μF) should be placed as
close to the IC as possible. When using
ceramic capacitors, ensure that they have
enough capacitance to provide a sufficient
charge to prevent excessive voltage ripple at
the input.
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MP2269 - 30V, 1A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
The input voltage ripple caused by the
capacitance can be estimated with Equation (8):
VIN
ILOAD
V
V
OUT 1 OUT
fS C1 VIN
VIN
(8)
Selecting the Output Capacitor
The output capacitor (C2) maintains the DC
output voltage. Use ceramic, tantalum, or low
ESR electrolytic capacitors. For best results,
use low ESR capacitors to keep the output
voltage ripple low. The output voltage ripple can
be estimated with Equation (9):
VOUT
(9)
VOUT
V
1
1 OUT RESR
fS L1
VIN
8 fS C2
Where L1 is the inductor value, and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
For ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency, and the capacitance causes the
majority of the output voltage ripple. For
simplification, the output voltage ripple can be
estimated with Equation (10):
∆VOUT
V
VOUT
1 OUT
VIN
8 fS L1 C2
2
PCB Layout Guidelines (8)
Efficient PCB layout is critical for stable
operation. For best results, refer to Figure 6 and
follow the guidelines below.
1. Keep the connection of the input ground
and GND as short and wide as possible.
2. Keep the connection of the input capacitor
and VIN as short and wide as possible.
3. Ensure all feedback connections are short
and direct.
4. Place
the
feedback
resistors
and
compensation components as close to the
chip as possible.
5. Route SW away from sensitive analog
areas such as FB.
NOTES:
8) The recommended layout is based on the Typical Application
circuit on page 17 and page 18.
(10)
For tantalum or electrolytic capacitors, the ESR
dominates the impedance at the switching
frequency. For simplification, the output ripple
can be approximated with Equation (11):
∆VOUT
VOUT
V
1 OUT
fS L1
VIN
RESR
(11)
Top Layer
The characteristics of the output capacitor
affect the stability of the regulation system. The
MP2269 can be optimized for a wide range of
capacitance and ESR values.
Bottom Layer
Figure 6: Sample PCB Layout
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MP2269 - 30V, 1A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
Design Example
Table 2 shows a design example following the
application guidelines for the specifications
below.
Table 2: Design Example
12V
VIN
3.3V
VOUT
1A
IOUT
The detailed application schematic is shown in
Figure 7 through Figure 12. The typical
performance and circuit waveforms are shown
in the Typical Performance Characteristics
section. For additional device applications,
please refer to the related evaluation board
datasheet.
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MP2269 - 30V, 1A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS (9)
Figure 7: VIN = 12V, VOUT = 5V
Figure 8: VIN = 12V, VOUT = 3.3V
Figure 9: VIN = 12V, VOUT = 2.5V
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MP2269 - 30V, 1A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS (continued)
Figure 10: VIN = 12V, VOUT = 1.8V
Figure 11: VIN = 12V, VOUT = 1.2V
Figure 12: VIN = 12V, VOUT = 1.05V
NOTE:
9) To use the BIAS function, connect BIAS to a power source higher than 4.8V. If the BIAS function is not used, connect BIAS to GND.
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MP2269 - 30V, 1A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
PACKAGE INFORMATION
QFN-15 (2mmx3mm)
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
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