MP28257
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The Future of Analog IC Technology
4A, Fast Transient, 4.2V-to-20V Input
Synchronous Step-Down Converter
2mmx3mm QFN12
DESCRIPTION
FEATURES
The MP28257 is a fully-integrated, synchronous,
step-down, switch-mode converter with a
programmable frequency. It offers a very
compact solution that can provide up to 4A of
continuous output current over a wide input
supply range with excellent load and line
regulation, and can operate at high efficiency
over a wide output current load range.
Constant-on-time control mode provides fast
transient response and eases loop stabilization.
Protections include short-circuit protection,
over-current protection, over-voltage protection,
under-voltage protection, and thermal shut
down.
The MP28257 requires a minimal number of
readily-available standard external components.
The device is available in a space saving
2mmx3mm QFN12 package that complies with
ROHS.
Wide 4.2V-to-20V Operating Input Range
4A Continuous Output Current
Internal 120mΩ High-Side, 50mΩ LowSide Power MOSFETs
Stable with Ceramic Output Capacitors
Proprietary Switching Loss-Reduction
Technology
Power-Good Indicator
Soft Startup/Shutdown
Programmable Switching Frequency
SCP, OCP, OVP, UVP Protection and
Thermal Shutdown
Output Adjustable from 0.815V to 13V
Available in a 2mmx3mm QFN12
Package
APPLICATIONS
Networking Systems
Distributed Power Systems
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Quality Assurance. “MPS” and “The
Future of Analog IC Technology” are Registered Trademarks of Monolithic
Power Systems, Inc.
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TYPICAL APPLICATION
MP28257 Rev 1.01
www.MonolithicPower.com
4/13/2020
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© 2020 MPS. All Rights Reserved.
1
MP28257 –4A, 4.2V-TO-20V, FAST TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTER
ORDERING INFORMATION
OCP Protection
MP28257DD*
Latch-off Mode
Package
QFN12 (2x3mm)
Top Marking
Free Air Temperature (TA)
ABF
-40°C to +85°C
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Part Number
* For Tape & Reel, add suffix –Z (e.g. MP28257DD–Z).
For RoHS Compliant Packaging, add suffix –LF (e.g. MP28257DD–LF–Z)
PACKAGE REFERENCE
TOP VIEW
GND
12
11
GND
10
SW
GND
1
SW
2
BST
3
9
IN
VCC
4
8
FREQ
EN
5
7
FB
SW
6
PG
QFN12 (2x3mm)
ABSOLUTE MAXIMUM RATINGS (1)
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Supply Voltage VIN ........................................ 22V
VSW ...................................... -0.3V to (VIN + 0.3V)
VBST.......................................................... VSW+6V
All other pins ................................... -0.3V to +6V
Continuous Power Dissipation (TA = 25°C) (2)
QFN12 (2x3mm) ......................................... 1.8W
Junction Temperature .............................. 150°C
Lead Temperature .................................... 260°C
Storage Temperature ................-65°C to +150°C
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Recommended Operating Conditions (3)
Supply Voltage VIN ........................... 4.2V to 20V
Output Voltage VOUT ..................... 0.815V to 13V
Maximum Junction Temp. (TJ) .................. 125°C
Thermal Resistance (4)
θJA
θJC
QFN12 (2x3mm) ..................... 70 ....... 15 ... °C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
MP28257 Rev 1.01
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2
MP28257 –4A, 4.2V-TO-20V, FAST TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = 25°C, unless otherwise noted.
Switch leakage
SWLKG
Current limit
One-shot on time
Minimum off time
Fold-back off time (5)
OCP hold-off time (5)
ILIMIT
tON
tOFF
tFB
tOC
Feedback voltage
VFB
Feedback current
Soft start time
EN rising threshold
EN threshold hysteresis
EN input current
EN Input Current
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Power-good rising threshold
Power-good falling threshold
Power-good delay
Power-good sink current
Power-good leakage current
VIN
under-voltage
lockout
threshold rising
VIN
under-voltage
lockout
threshold hysteresis
Thermal shutdown (5)
Thermal shutdown hysteresis (5)
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Symbol
IIN
IIN
HSRDS-ON
LSRDS-ON
Condition
VEN = 0V
VEN = 2V, VFB = 0.9V
Min
Typ
1
360
120
50
Max
Units
μA
μA
mΩ
mΩ
0
10
μA
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Parameters
Supply current (shutdown)
Supply current (quiescent)
HS switch-on resistance (5)
LS Switch-on resistance (5)
IFB
tSS
ENVth-Hi
ENVth-Hys
IEN
IEN
PGVth-Hi
PGVth-Lo
PGTd
IPG
IPG_LEAK
VEN = 0V, VSW = 0V or
12V
After Soft-Start Time-out
R7 = 300kΩ, VOUT = 1.2V
ILIM = 1
ILIM = 1
TA = 25°C
TA = -40°C to 85°C
VFB = 800mV
5.5
807
803
1.05
VEN = 2V
VEN = 0V
VEN=2V
VEN=0V
Power-good
Fault condition
PG = 0.4V
VPG = 3.3V
7
250
130
4.5
50
815
10
1
1.35
500
2
0
2
0
90
85
500
4
INUVVth
150
823
827
50
1.6
A
ns
ns
μs
μs
mV
mV
nA
ms
V
mV
μA
μA
10
%
%
μs
mA
nA
3.1
V
INUVHYS
300
mV
TSD
TSD-HYS
150
25
°C
°C
Note:
5) Guaranteed by design.
MP28257 Rev 1.01
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4/13/2020
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© 2020 MPS. All Rights Reserved.
3
MP28257 –4A, 4.2V-TO-20V, FAST TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTER
PIN FUNCTIONS
Name
9
IN
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QFN12
(2x3mm)
Pin #
1, 11, 12
GND
2, 10,
Exposed Pad
SW
3
BST
4
5
7
8
EN
FB
FREQ
PG
Supply Voltage. The MP28257 operates from a 4.2V to 20V input rail. C1 decouples
the input rail. Use wide PCB traces and multiple vias to make the connection.
System Ground. Reference ground for the regulated output voltage. These pins
require special consideration during PCB layout.
Switch Output. Connect with wide PCB traces.
Bootstrap. Requires a capacitor connected between SW and BST pins to form a
floating supply across the high-side switch driver.
Internal Bias Supply. Decouple with a 1µF ceramic capacitor as close to the pin as
possible.
EN = 1 to enable the MP28257. For automatic start-up, connect EN pin to VIN with a
pull-up resistor.
Feedback. Sets the output voltage when connected to the tap of an external resistor
divider, connected between output and GND.
Frequency. Set during CCM operation. Connect a resistor R7 to IN to set the switching
frequency. Decouple with a 1nF capacitor.
Power-Good Output. The output of this pin is an open drain that goes high if the output
voltage is higher than 90% of the nominal voltage. There is a 0.5ms delay between
when the feedback exceeds 90% to when the PG pin goes high.
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VCC
Description
MP28257 Rev 1.01
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4/13/2020
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© 2020 MPS. All Rights Reserved.
4
MP28257 –4A, 4.2V-TO-20V, FAST TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
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VIN = 12V, VOUT = 1.2V, L = 2μH, TA = 25°C, unless otherwise noted.
MP28257 Rev 1.01
www.MonolithicPower.com
4/13/2020
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© 2020 MPS. All Rights Reserved.
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MP28257 –4A, 4.2V-TO-20V, FAST TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 1.2V, L = 2μH, TA = 25°C, unless otherwise noted.
VOUT/AC
10mV/div.
Start up through VIN
Start up through VIN
IOUT = 4A
IOUT = 0A
IOUT = 4A
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VIN/AC
100mV/div.
Input/Output Voltage Ripple
VIN
10V/div.
VIN
10V/div.
VOUT
1V/div.
VSW
5V/div.
IL
5A/div.
VIN
10V/div.
VOUT
1V/div.
VSW
2V/div.
VSW
10V/div.
VSW
10V/div.
IL
1A/div.
IL
5A/div.
Shutdown through VIN
Shutdown through VIN
Start up through EN
IOUT = 0A
IOUT = 4A
IOUT = 0A
VIN
5V/div.
VOUT
1V/div.
VSW
10V/div.
IL
5A/div.
VOUT
1V/div.
VSW
5V/div.
VSW
10V/div.
IL
5A/div.
IL
1A/div.
Start up through EN
Shutdown through EN
Shutdown through EN
IOUT = 4A
IOUT = 0A
IOUT = 4A
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VEN
5V/div.
VEN
5V/div.
VOUT
1V/div.
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IL
1A/div.
VOUT
1V/div.
VEN
5V/div.
VOUT
1V/div.
VSW
10V/div.
IL
1A/div.
VEN
5V/div.
VOUT
1V/div.
VSW
10V/div.
IL
5A/div.
MP28257 Rev 1.01
www.MonolithicPower.com
4/13/2020
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© 2020 MPS. All Rights Reserved.
6
MP28257 –4A, 4.2V-TO-20V, FAST TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
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VIN = 12V, VOUT = 1.2V, L = 2μH, TA = 25°C, unless otherwise noted.
VOUT/AC
50mV/div.
VOUT/AC
50mV/div.
VOUT/AC
50mV/div.
VSW
10V/div.
IL
5A/div.
IL
5A/div.
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IL
2A/div.
VSW
10V/div.
MP28257 Rev 1.01
www.MonolithicPower.com
4/13/2020
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© 2020 MPS. All Rights Reserved.
7
MP28257 –4A, 4.2V-TO-20V, FAST TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTER
BLOCK DIAGRAM
EN
Current Sense
Amplifer
5V LDO
Over-Current
Timer
+
-
REFERENCE
ILIM
RSEN
OC
BST
OFF
Timer
HS IIimit
Comparator
VCC
xS Q
0.4V
1MEG
+
VCC
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IN
FREQ
PWM
HS
Driver
HS_FET
1.0V
xR
0.8V
LOGIC
SW
SOFT
START/STOP
PG
PGOOD
Comparator
+
FB
+
+
-
START
VCC
ON
Timer
LS
Driver
Loop
Comparator
LS_FET
Current
Modulator
+
-
UV
UV Detect
Comparator
GND
0
0
+
-
OV
OV Detect
Comparator
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Figure 1: Functional Block Diagram
MP28257 Rev 1.01
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4/13/2020
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MP28257 –4A, 4.2V-TO-20V, FAST TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTER
OPERATION
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PWM Operation
The MP28257 is a fully-integrated, synchronous,
rectified, step-down switch converter. The device
uses constant-on-time (COT) control to provide
fast transient response and easy loop
stabilization. At the beginning of each cycle, the
high-side MOSFET (HS-FET) turns ON
whenever the feedback voltage (VFB) is lower
than the reference voltage (VREF)—a low VFB
indicates insufficient output voltage. The input
voltage and the frequency-set resistor determine
the ON period as follows:
9.3 R7 (k )
(1)
t ON (ns)
40ns
VIN (V) 0.4
After the ON period elapses, the HS-FET enters
the OFF state. By cycling the HS-FET between
the ON and OFF states, the converter regulates
the output voltage. The integrated low-side
MOSFET (LS-FET) turns on when the HS-FET is
in its OFF state to minimize the conduction loss.
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Shoot-through occurs when there is both the HSFET and LS-FET are turned on at the same time,
causing a dead short between input and GND.
Shoot-through dramatically reduces efficiency,
and the MP28257 avoids this by internally
generating a dead-time (DT) between when the
HS-FET is off and the LS-FET is on, and when
the LS-FET is off and the HS-FET is on. The
device enters either heavy-load operation or
light-load operation depending on the amplitude
of the output current.
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Heavy-Load Operation
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LS-FET repeat the on/off operation described for
PWM operation, the inductor current never goes
to zero, and the switching frequency (fSW) is fairly
constant. Figure 2 shows the timing diagram
during this operation.
Light-Load Operation
During light-load operation—when the output
current is low—the MP28257 automatically
reduces the switching frequency to maintain high
efficiency, and the inductor current drops near
zero.. When the inductor current reaches zero,
the LS-FET driver goes into tri-state (high Z). The
current modulator controls the LS-FET and limits
the inductor current to around -1mA as shown in
Figure 3. Hence, the output capacitors discharge
slowly to GND through LS-FET, R1, and R2. This
operation greatly improves device efficiency
when the output current is low.
Figure 3: Light-Load Operation
Light-load operation is also called skip mode
because the HS-FET does not turn on as
frequently as during heavy-load conditions. The
frequency at which the HS-FET turns on is a
function of the output current—as the output
current increases, the time period that the current
modulator regulates becomes shorter, and the
HS-FET turns on more frequently. The switching
frequency increases in turn. The output current
reaches the critical level when the current
modulator time is zero, and can be determined
using the following equation:
(VIN VOUT ) VOUT
(2)
2 L fSW VIN
The device reverts to PWM mode once the
output current exceeds the critical level. After that,
the switching frequency stays fairly constant over
the output current range.
IOUT
Figure 2: Heavy-Load Operation
During heavy-load operation—when the output
current is high—the MP28257 enters continuousconduction mode (CCM) where the HS-FET and
MP28257 Rev 1.01
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MP28257 –4A, 4.2V-TO-20V, FAST TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTER
Jitter can affect system stability, with noise
immunity proportional to the steepness of VFB’s
downward slope. However, VFB ripple does not
directly affect noise immunity.
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BST
LSG
N1
VNOISE
V S L O PE1
C3
VFB
VCC
VREF
C5
SW
HS D river
L
J itter
COUT
Figure 4: Floating Driver and Bootstrap
Charging
The floating power MOSFET driver is powered by
an external bootstrap capacitor. This floating
driver has its own UVLO protection with a rising
threshold of 2.2V and a hysteresis of 150mV.
The bootstrap capacitor is charges from VCC
through N1 (Figure 4): N1 turns on when the LSFET turns on, and turns off when the LS-FET
turns off.
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Switching Frequency
The MP28257 uses COT control because there
is no dedicated oscillator in the IC. The input
voltage is feed-forwarded to the on-time one-shot
timer through the resistor R7. The duty ratio is
kept as VOUT/VIN, and the switching frequency is
fairly constant over the input voltage range. The
switching frequency can be determined with the
following equation:
106
(3)
f (kHz)
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SW
Figure 5—Jitter in PWM Mode
VNOISE
VS LOPE 2
V FB
V REF
HS D river
Jitter
Figure 6—Jitter in Skip Mode
Ramp with Large ESR Cap
In the case of POSCAP or other types of
capacitor with larger ESR is applied as output
capacitor. The ESR ripple dominates the output
ripple, and the slope on the FB is quite ESR
related. Figure 7 shows an equivalent circuit in
PWM mode with the HS-FET off and without an
external ramp circuit. Turn to application
information section for design steps with large
ESR caps.
9.3 R7 (k ) VIN (V)
tDELAY (ns)
VIN (V) 0.4 VOUT (V)
Where TDELAY is the comparator delay, and
equals approximately 40ns.
The MP28257 is optimized to operate at a high
switching frequency a high efficiency. The high
switching frequency makes it possible to use
small-sized LC filter components to save system
PCB space.
Figure 7—Simplified Circuit in PWM Mode
without External Ramp Compensation
Jitter and FB Ramp Slope
Jitter occurs in both PWM and skip modes when
noise in the VFB ripple propagates a delay to the
HS-FET driver, as shown in Figures 5 and 6.
MP28257 Rev 1.01
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MP28257 –4A, 4.2V-TO-20V, FAST TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTER
RESR
TSW
T
ON
2
0.7
COUT
(4)
TSW
T
+ ON -RESRCOUT
Io 10-3
0.7
π
2
(9)
-Vslope1
VOUT +
2 L COUT
TSW -Ton
TSW is the switching period.
Ramp with small ESR Cap
When the output capacitors are ceramic ones,
the ESR ripple is not high enough to stabilize the
system, and external ramp compensation is
needed. Skip to application information section
for design steps with small ESR caps
.
As can be seen from equation 8, if there is
instability in PWM mode, we can reduce either
R4 or C4. If C4 can not be reduced further due to
limitation from equation 5, then we can only
reduce R4. For a stable PWM operation, the
Vslope1 should be design follow equation 9.
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To realize the stability when no external ramp is
used, usually the ESR value should be chosen
as follow:
Io is the load current.
In skip mode, the downward slope of the VFB
ripple is the same whether the external ramp is
used or not. Figure9 shows the simplified circuit
of the skip mode when both the HS-FET and LSFET are off.
Figure 9—Simplified Circuit in skip Mode
Figure 8—Simplified Circuit in PWM Mode
with External Ramp Compensation
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Figure 8 shows a simplified external ramp
compensation (R4 and C4) for PWM mode, with
HS-FET off. Chose R1, R2, R9 and C4 of the
external ramp to meet the following condition:
(5)
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1
1 R R2
1
R9
2 FSW C 4 5 R1 R 2
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where:
IR4 IC4 IFB IC4
(6)
And the Vramp on the VFB can then be estimated
as:
VRAMP
VIN VOUT
R1 // R2
TON
R 4 C4
R1 // R2 R9
(7)
The downward slope of the VFB ripple then
follows
VSLOPE1
VOUT
VRAMP
Toff
R 4 C4
(8)
The downward slope of the VFB ripple in skip
mode can be determined as follow:
VSLOPE2
VREF
(R1 R2 // Ro) COUT
(10)
where Ro is the equivalent load resistor.
As described in Figure 6, VSLOPE2 in the skip mode
is lower than that is in the PWM mode, so it is
reasonable that the jitter in the skip mode is
larger. If one wants a system with less jitter
during light load condition, the values of the VFB
resistors should not be too big, however, that will
decrease the light load efficiency.
When using a large-ESR capacitor on, the output,
add a ceramic capacitor with a value of 10uF or
less to in parallel to minimize the effect of ESL.
Soft Start/Stop
MP28257 employs a soft-start/stop (SS)
mechanism to ensure a smooth output during
power up and power shut-down. When the EN
pin goes high, the internal SS voltage slowly
ramps up. The output voltage smoothly ramps up
with the SS voltage. Once SS voltage rises
MP28257 Rev 1.01
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MP28257 –4A, 4.2V-TO-20V, FAST TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTER
UVP accompanies a drop in the current limit and
this results in SCP.
UVLO Protection
MP28257 has under-voltage lock-out (UVLO)
protection. The MP28257 powers up when the
input voltage exceeds the UVLO rising threshold
voltage. It shuts off when the input voltage falls
below the UVLO falling threshold voltage. This is
non-latch protection.
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above the VREF, it continues to ramp up while the
PWM comparator only compares the VREF and
the FB voltage. At this point, the soft-start
finishes and it enters steady state operation. The
SS time is set about 1ms internally.
When the EN pin goes low, an internal current
source discharges the internal SS voltage. Once
the SS voltage falls below the VREF, the PWM
comparator will only compare the VREF to the SS
voltage. The output voltage then decreases
smoothly with the SS voltage until the voltage
level zeros out.
Power-Good (PG)
The PG pin is the open drain of a MOSFET that
connects to VCC or some other voltage source
through a resistor (e.g.. 100kΩ). The MOSFET
turns on with the application of an input voltage
so that the PG pin is pulled to GND before SS is
ready. After FB voltage reaches 90% of VREF, the
PG pin is pulled high after a 0.5ms delay.
Thermal Shutdown
The MP28257 employs thermal shutdown by
internally monitoring the junction temperature of
the IC. If the junction temperature exceeds the
threshold value (typically 150°C), the converter
shuts off. This is non-latch protection. There is
about 25°C hysteresis. Once the junction
temperature drops around 125°C, it initiates a
soft start.
When the FB voltage drops to 70% of VREF, the
PG pin will be pulled low.
Over-Current Protection (OCP) and ShortCircuit Protection (SCP)
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MP28257 has cycle-by cycle over-current limit
control. It monitors the inductor current during the
ON state. Once the inductor current exceeds the
current limit, the HS-FET turns off and the OCP
timer—set at 50μs—starts. The OCP triggers. If
the inductor current reaches or exceeds the
current limit every cycle if in those the 50μs, the
device enters latch-off mode
N
O
T
The MP28257 SCP triggers when dead shorts
occur—when the inductor current exceeds the
current limit and the FB voltage is lower than
50% of the VREF—and will trigger the OCP. The
MP28257 needs power cycle to restart after it
triggers OCP or SCP.
Over/Under-Voltage Protection (OVP/UVP)
MP28257 monitors the output voltage through a
resistor-divided FB voltage to detect over- and
under-voltage on the output. When the FB
voltage is higher than 125% of the VREF, it
triggers the OVP. Once it triggers the OVP, the
LS-FET is always on while the HS-FET is off. It
needs to power cycle to turn on again.
Conversely, the UVP triggers when the FB
voltage falls below 50% of VREF (0.815V). Usually
MP28257 Rev 1.01
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12
MP28257 –4A, 4.2V-TO-20V, FAST TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTER
APPLICATION INFORMATION
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Setting the Output Voltage-Large ESR Caps
in equation 7. R2 should be chosen reasonably,
a small R2 will lead to considerable quiescent
current loss while too large R2 makes the FB
noise sensitive. It is recommended to choose a
value within 5kΩ-50kΩ for R2, using a
comparatively larger R2 when Vo is low,
etc.,1.05V, and a smaller R2 when Vo is high.
And the value of R1 then is determined as follow:
R2
(12)
R=
For applications that electrolytic capacitor or POS
capacitor with a controlled output of ESR is set
as output capacitors. The output voltage is set by
feedback resistors R1 and R2. As Figure 10
shows.
1
Figure10—Simplified Circuit of POS Capacitor
R
First, choose a value for R2. R2 should be
chosen reasonably, a small R2 will lead to
considerable quiescent current loss while too
large R2 makes the FB noise sensitive. It is
recommended to choose a value within 5kΩ50kΩ for R2, using a comparatively larger R2
when Vo is low, etc.,1.05V, and a smaller R2
when Vo is high. Then R1 is determined as follow
with the output ripple considered:
1
VOUT VOUT VREF
2
(11)
R1
R2
VREF
VOUT is the output ripple determined by equation
20.
N
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T
Setting the Output Voltage-Small ESR Caps
Figure11—Simplified Circuit of Ceramic
Capacitor
When low ESR ceramic capacitor is used in the
output, an external voltage ramp should be
added to FB through resistor R4 and capacitor
C4.The output voltage is influenced by ramp
voltage VRAMP besides R divider as shown in
Figure 11. The VRAMP can be calculated as shown
VFB(AVG)
R2
(VOUT -VFB(AVG) ) R4 +R9
The VFB(AVG) is the average value on the FB,
VFB(AVG) varies with the Vin, Vo, and load
condition, etc., its value on the skip mode would
be lower than that of the PWM mode, which
means the load regulation is strictly related to the
VFB(AVG). Also the line regulation is related to the
VFB(AVG) ,If one wants to gets a better load or line
regulation, a lower Vramp is suggested once it
meets equation 9.
For PWM operation, VFB(AVG) value can be
deduced from equation 13.
R1 //R2
1
VFB(AVG) VREF VRAMP
2
R1 //R2 R9
(13)
Usually, R9 is set to 0Ω, and it can also be set
following equation 14 for a better noise immunity.
It should also set to be 5 timers smaller than
R1//R2 to minimize its influence on Vramp.
R9
1
2 C4 2FSW
(14)
Using equation 12 to calculate the output voltage
can be complicated. To simplify the calculation of
R1 in equation 12, a DC-blocking capacitor Cdc
can be added to filter the DC influence from R4
and R9. Figure 12 shows a simplified circuit with
external ramp compensation and a DC-blocking
capacitor. With this capacitor, R1 can easily be
obtained by using equation 15 for PWM mode
operation.
1
(VOUT VREF VRAMP )
2
R1
R2
1
VREF VRAMP
2
(15)
Cdc is suggested to be at least 10 times larger
than C4 for better DC blocking performance, and
should also not larger than 0.47uF considering
start up performance. In case one wants to use
MP28257 Rev 1.01
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13
MP28257 –4A, 4.2V-TO-20V, FAST TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTER
VIN
IOUT
V
V
OUT (1 OUT )
fSW CIN VIN
VIN
(18)
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larger Cdc for a better FB noise immunity,
combined with reduced R1 and R2 to limit the
Cdc in a reasonable value without affecting the
system start up. Be noted that even when the
Cdc is applied, the load and line regulation are
still Vramp related.
Under worst-case conditions where VIN = 2VOUT:
VIN
I
1
OUT
4 fSW CIN
(19)
Output Capacitor
The output capacitor is required to maintain the
DC output voltage. Ceramic or POSCAP
capacitors are recommended. The output voltage
ripple can be estimated as:
VOUT
Figure12—Simplified Circuit of Ceramic
Capacitor with DC blocking capacitor
Input Capacitor
The input current to the step-down converter is
discontinuous and therefore requires a capacitor
to supply the AC current to the step-down
converter while maintaining the DC input voltage.
Ceramic capacitors are recommended for best
performance and should be placed as close to
the VIN pin as possible. Use capacitors with X5R
and X7R ceramic dielectrics because they are
fairly stable with temperature fluctuations.
R
The capacitors must also have a ripple current
rating greater than the maximum input ripple
current of the converter. The input ripple current
can be estimated as follows:
VOUT
V
(16)
ICIN IOUT
(1 OUT )
VIN
VIN
N
O
T
The worst-case condition occurs at VIN = 2VOUT,
where:
ICIN
IOUT
2
(17)
For simplification, choose the input capacitor with
an RMS current rating greater than half of the
maximum load current.
The input capacitance value determines the input
voltage ripple of the converter. If there is an input
voltage ripple requirement in the system, choose
the input capacitor that meets the specification.
The input voltage ripple can be estimated as
follows:
VOUT
V
1
(1 OUT ) (RESR
) (20)
FSW L
VIN
8 FSW COUT
In the case of ceramic capacitors, the impedance
at the switching frequency is dominated by the
capacitance. The output voltage ripple is mainly
caused by the capacitance. For simplification, the
output voltage ripple can be estimated as:
VOUT
VOUT
V
(1 OUT )
8 FSW 2 L COUT
VIN
(21)
The output voltage ripple caused by ESR is very
small. Therefore, an external ramp is needed to
stabilize the system. The external ramp can be
generated through resistor R4 and capacitor C4
following equation 5, 8 and 9.
In the case of POSCAP capacitors, the ESR
dominates the impedance at the switching
frequency. The ramp voltage generated from the
ESR is high enough to stabilize the system.
Therefore, an external ramp is not needed. A
minimum ESR value around 12mΩ is required to
ensure stable operation of the converter. For
simplification, the output ripple can be
approximated as:
VOUT
VOUT
V
(1 OUT ) RESR
FSW L
VIN
(22)
Maximum output capacitor limitation should be
also considered in design application. MP28258
has an around 1ms soft-start time period. If the
output capacitor value is too high, the output
voltage can’t reach the design value during the
soft-start time, and then it will fail to regulate. The
maximum output capacitor value Co_max can be
limited approximately by:
CO _ MAX (ILIM _ AVG IOUT ) Tss / VOUT
MP28257 Rev 1.01
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4/13/2020
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(23)
14
MP28257 –4A, 4.2V-TO-20V, FAST TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTER
Where, ILIM_AVG is the average start-up current
during soft-start period. Tss is the soft-start time.
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Inductor
The inductor is necessary to supply constant
current to the output load while being driven by
the switched input voltage. A larger-value
inductor will result in less ripple current that will
result in lower output ripple voltage. However, a
larger-value inductor will have a larger physical
footprint, higher series resistance, and/or lower
saturation current. A good rule for determining
the inductance value is to design the peak-topeak ripple current in the inductor to be in the
range of 30% to 40% of the maximum output
current, and that the peak inductor current is
below the maximum switch current limit. The
inductance value can be calculated by:
L
VOUT
V
(1 OUT )
fSW IL
VIN
(24)
Where ∆IL is the peak-to-peak inductor ripple
current.
O
T
R
The inductor should not saturate under the
maximum inductor peak current, where the peak
inductor current can be calculated by:
VOUT
V
(25)
ILP IOUT
(1 OUT )
2fSW L
VIN
N
Recommend Design Example
Some design examples and recommended
maximum output capacitor value with typical
outputs are provided below when the ceramic
capacitors is applied with R9=0ohm:
Table 1: 1.2V VOUT (L = 2μH)
VIN VOUT
(V) (V)
C1
R7
(Ω)
R4
(Ω)
C4
(F)
R1
(Ω)
R2
(Ω)
FSW
(Hz)
12
1.2 10μF*1 300k 499k 220p
12.1k 24.3k 450k
5
1.2 10μF*1 300k 390k 220p
12.1k 24.3k 440k
3.3 1.2 10μF*1 300k 243k 220p
12.1k 24.3k 435k
Table 2: 1.8V VOUT (L = 2μH)
VIN VOUT
(V) (V)
C1
R7
(Ω)
R4
(Ω)
C4
(F)
R1
(Ω)
R2
(Ω)
FSW
(Hz)
12
1.8 10μF*1 402k 499k 220p
30.1k 24.3k 480k
5
1.8 10μF*1 402k 390k 220p
30.1k 24.3k 460k
3.3 1.8 10μF*2 402k 280k 220p
30.1k 24.3k 450k
Note: For 1.8V VOUT from 3.3V VIN, a larger C1 is recommended to
sustain maximum 4A load.
Table 3: 2.5V VOUT (L = 4.2μH)
VIN VOUT
(V) (V)
C1
R7
(Ω)
R4
(Ω)
C4
(F)
R1
(Ω)
R2
(Ω)
FSW
(Hz)
12
2.5
10μF*1 500k 453k 390p
21.5k
10k
500k
5
2.5
10μF*1 500k 453k 390p
21.5k
10k
500k
Table 4: 3.3V VOUT (L = 6.5μH)
VIN VOUT
(V) (V)
C1
R7
(Ω)
R4
(Ω)
C4
(F)
R1
(Ω)
R2
(Ω)
FSW
(Hz)
12
3.3
10μF*1 680k 470k 330p
31.6k
10k
500k
5
3.3
10μF*1 680k 470k 330p
31.6k
10k
500k
Table 5: 5V VOUT (L = 8.8μH)
VIN VOUT
(V) (V)
12
5
C1
R7
(Ω)
10μF*1
1M
R4
(Ω)
C4
(F)
750k 330p
R1
(Ω)
R2
(Ω)
FSW
(Hz)
53.6k
10k
500k
The detailed application schematic is shown in
Figure 13 when large ESR caps are used, and
Figure14 and Figure 15 when low ESR caps are
applied. The typical performance and circuit
waveforms have been shown in the Typical
Performance Characteristics section. For more
possible applications of this device, please refer
to related Evaluation Board Data Sheets.
MP28257 Rev 1.01
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15
MP28257 –4A, 4.2V-TO-20V, FAST TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTER
Typical Application Schematic
R3
0
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9
C1A
TBD
25V
IN
BST
R7
TBD
MP28257
C7
1nF
8
4
R10
100k
L1
TBD
SW 2
10
SW
FREQ
VOUT
VCC
GND
R1
TBD
R5
499k
GND
PG
1
7
GND
FB
5 EN
6
PG
EN
GND
VIN
3
R2
TBD
11 12
Figure 13—Typical Application Schematic with No External Ramp
9
C1A
TBD
25V
R3
0
8
L1
TBD
SW 2
10
SW
FREQ
R1
TBD
R9
0
1
7
GND
FB
VOUT
GND
TBD
R5
499k
5 EN
6
PG
C2E
NS
C4
TBD
R4
VCC
GND
PG
3
MP28257
4
EN
BST
R7
TBD
C7
1nF
R10
100k
IN
GND
VIN
R2
TBD
11 12
R
Figure 14—Typical Application Schematic with Low ESR Ceramic Capacitor
C1A
TBD
25V
BST
3
R3
0
MP28257
8
4
SW 2
10
SW
FREQ
VCC
L1
TBD
R4
TBD
C4
FB
1
VOUT
GND
R1
TBD
7
GND
5 EN
6
PG
C2E
NS
TBD
Cdc
TBD
R5
499k
GND
PG
IN
R7
TBD
C7
1nF
R10
100k
EN
9
GND
N
O
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VIN
R2
TBD
11 12
Figure 15—Typical Application Schematic with Low ESR Ceramic Capacitor\
and DC Blocking Capacitor.
MP28257 Rev 1.01
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16
MP28257 –4A, 4.2V-TO-20V, FAST TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTER
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Layout Recommendation
1) The high current paths (GND, IN, and SW)
should be placed very close to the device
with short, wide, and direct traces.
Put the input capacitors as close to the IN
and GND pins as possible.
3)
Put the decoupling capacitor as close to the
VCC and GND pins as possible.
4)
Keep the switching node SW short and away
from the feedback network.
5)
The external feedback resistors should be
placed next to the FB pin. Make sure that
there is no via on the FB trace.
6)
Keep the BST voltage path (BST, C3, and
SW) as short as possible.
7)
Four-layer layout is recommended to achieve
better thermal performance.
N
O
T
R
2)
MP28257 Rev 1.01
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17
MP28257 –4A, 4.2V-TO-20V, FAST TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTER
PACKAGE INFORMATION
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QFN12 (2x3mm)
1.90
2.10
PIN 1 ID
MARKING
12
0.35
0.45
2.90
3.10
PIN 1 ID
INDEX AREA
0.45
0.55
0.20
0.30
11
1
0.35
0.45
1.10
0.40
0.00
0.20
0.30
0.50
BSC
0.35
0.45
TOP VIEW
5
7
0.35
0.45
6
BOTTOM VIEW
0.80
1.00
0.20 REF
0.00
0.05
SIDE VIEW
1.90
0.60
1.80
R
0.25
1.30
0.90
N
O
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0.60
0.20
0.00
NOTE:
1)
2)
3)
4)
5)
ALL DIMENSIONS ARE IN MILLIMETERS.
EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
LEAD COPLANARITY SHALL BE0.10 MILLIMETER MAX.
JEDEC REFERENCE DRAWING IS JEDEC MO-220
DRAWING IS NOT TO SCALE.
0.25
0.50
0.70
1.45
0.70
0.25
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP28257 Rev 1.01
www.MonolithicPower.com
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MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
18
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