MP2364DS

TM MP2364 Dual 1.5A, 23V, 1.4MHz Step-Down Converter The Future of Analog IC Technology TM DESCRIPTION The MP2364 is a dual monolithic step-down switch mode converter with built-in internal power MOSFETs. It achieves 1.5A continuous output current for each output over a wide input supply range with excellent load and line regulation. Current mode operation provides fast transient response and eases loop stabilization. Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. In shutdown mode, the regulator draws 40µA of supply current. The MP2364 requires a minimum number of readily available standard external components. FEATURES • • • • • • • • • • • • • • 1.5A Current for Each Output 0.18Ω Internal Power MOSFET Switches Stable with Low ESR Output Ceramic Capacitors Up to 90% Efficiency 40µA Shutdown Mode Fixed 1.4MHz Frequency Thermal Shutdown Cycle-by-Cycle Over Current Protection Wide 4.75V to 23V Operating Input Range Each Output Adjustable from 0.92V to 16V Configurable for Single Output with Double the Current Programmable Under Voltage Lockout Programmable Soft-Start Available in TSSOP20 with Exposed Pad and SOIC Packages Distributed Power Systems I/O and Core supplies DSL Modems Set top boxes Cable Modems EVALUATION BOARD REFERENCE Board Number EV2364DF-01A Dimensions 2.2”X x 1.6”Y x 0.4”Z APPLICATIONS • • • • • “MPS” and “The Future of Analog IC Technology” are Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION 12V Efficiency vs Load Current 100 1 2 3 SSA NC1 BSA INA SWA PGA SGA FBB COMPB ENB ENA COMPA FBA SGB 20 19 18 17 16 15 14 13 10nF 12 11 3.3V @ 1.5A OFF ON 82pF 2A Schottky 2.2nF 90 VOUT=3.3V VOUT=5V 10nF 2A Schottky 4 5 6 7 8 9 EFFICIENCY (%) MP2364 PGB SWB INB NC2 BSB SSB 2.5V @ 1.5A 80 70 60 50 VOUT=2.5V OFF ON 10 3.3nF 0 MP2364_TAC_S01 0.5 1.0 LOAD CURRENT (A) 1.5 MP2364_EC01 MP2364 Rev. 1.4 3/22/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 1 TM MP2364 — DUAL 1.5A, 23V, 1.4MHz STEP-DOWN CONVERTER PACKAGE REFERENCE TOP VIEW SSA NC1 BSA INA SWA PGA SGA FBB COMPB ENB 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ENA COMPA FBA SGB PGB SWB INB NC2 BSB SSB TOP VIEW SSA BSA INA SWA GNDA FBB COMPB ENB 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ENA COMPA FBA GNDB SWB INB BSB SSB EXPOSED PAD FOR TSSOP20F ONLY MP2364_PD02_SOIC16 MP2364_PD01-TSSOP20F Part Number* MP2364DF * Package TSSOP20F Temperature –40°C to +85°C Part Number* MP2364DS * Package SOIC16 Temperature –40°C to +85°C For Tape & Reel, add suffix –Z (eg. MP2364DF–Z) For Lead Free, add suffix –LF (eg. MP2364DF–LF–Z) For Tape & Reel, add suffix –Z (eg. MP2364DS–Z) For Lead Free, add suffix –LF (eg. MP2364DS–LF–Z) ABSOLUTE MAXIMUM RATINGS (1) Supply Voltage (INA, INB ) ................................ 25V Switch Voltage (SWA, SWB) .............................. 26V Bootstrap Voltage (BSA, BSB) .................. VSW + 6V Feedback Voltage (FBA, FBB) ............–0.3V to +6V Enable/UVLO Voltage (ENA, ENB)......–0.3V to +6V Comp Voltage (COMPA, COMPB)...........–0.3V to +6V Soft Start Voltage (SSA, SSB).............–0.3V to +6V Junction Temperature .............................+150°C Lead Temperature ..................................+260°C Storage Temperature.............. –65°C to +150°C Recommended Operating Conditions (2) Supply Voltage (VIN) ...................... 4.75V to 23V Operating Temperature.................–40°C to +85°C Thermal Resistance (3) TSSOP20F ............................. 40 ....... 6.... °C/W SOIC16.................................. 105 ..... 40... °C/W Notes: 1) Exceeding these ratings may damage the device. 2) The device is not guaranteed to function outside of its operating conditions. 3) Measured on approximately 1” square of 1 oz copper. θJA θJC MP2364 Rev. 1.4 3/22/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 2 TM MP2364 — DUAL 1.5A, 23V, 1.4MHz STEP-DOWN CONVERTER ELECTRICAL CHARACTERISTICS VIN = 12V, TA = +25°C, unless otherwise noted. Parameter Feedback Voltage Symbol Condition VFB 4.75V ≤ VIN ≤ 23V Min 0.892 Typ 0.920 0.18 10 VEN = 0V, VSW = 0V 2.5 3.0 1.95 400 ∆IC = ±10 µA VFB = 0V 630 930 1.4 210 9 ICC > 100µA VEN Rising 0.7 2.37 1.0 1.0 2.50 210 VEN ≤ 0.4V VEN ≥ 3V VFB = 0.8V tON 40 2.4 160 70 100 70 2.8 1.3 2.62 1230 10 Max 0.948 Units V Ω Ω µA A A/V V/V µA/V MHz KHz kΩ V µA V mV µA mA °C % ns Upper Switch-On Resistance RDS(ON)1 Lower Switch-On Resistance RDS(ON)2 Upper Switch Leakage Current Limit (4) Current Limit Gain Output Current to Comp Pin GCS Voltage Error Amplifier Voltage Gain AVEA Error Amplifier GEA Transconductance Oscillator Frequency fOSC Short Circuit Frequency fSC Soft-Start Pin Equivalent Output Resistance EN Shutdown Threshold VEN Voltage Enable Pull-Up Current IEN EN UVLO Threshold Rising VUVLO EN UVLO Threshold Hysteresis Supply Current (Shutdown) Supply Current (Quiescent) Thermal Shutdown Maximum Duty Cycle Minimum On Time IOFF ION DMAX Note: 4) Equivalent output current = 1.5A ≥ 50% Duty Cycle 2.0A ≤ 50% Duty Cycle Assumes ripple current = 30% of load current. Slope compensation changes current limit above 40% duty cycle. MP2364 Rev. 1.4 3/22/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 3 TM MP2364 — DUAL 1.5A, 23V, 1.4MHz STEP-DOWN CONVERTER PIN FUNCTIONS (TSSOP20F) Pin # 1 2 3 4 5 6 Name SSA Description Soft-Start Control for Channel A. 9kΩ output resistance from the pin. Set RC time constant with external capacitor for soft start ramp time. Ramp Time = 2.2 x 9kΩ x C. NC No Connect BSA High-Side Driver Boost Pin. Connect a 10nF capacitor from this pin to SWA. Supply Voltage Channel A. The MP2364 operates from a +4.75V to +23V unregulated input. INA Input Ceramic Capacitors should be close to this pin. SWA Switch Channel A. This connects the inductor to either INA through M1A or to PGA through M2A. Power Ground Channel A. This is the Power Ground Connection to the input capacitor PGA ground. Signal Ground Channel A. This pin is the signal ground reference for the regulated output voltage. For this reason care must be taken in its layout. This node should be placed outside SGA of the D1 to C1 ground path to prevent switching current spikes from inducing voltage noise into the part. Feedback Voltage for Channel B. This pin is the feedback voltage. The output voltage is ratio scaled FBB through a voltage divider, and the center point of the divider is connected to this pin. The voltage is compared to the on board 0.92V reference. Compensation Channel B. This is the output of the transconductance error amplifier. A series COMPB RC is placed on this pin for proper control loop compensation. Please refer to more in the datasheet. Enable/UVLO Channel B. A voltage greater than 2.62V enables operation. Leave ENB unconnected for automatic startup. An Under Voltage Lockout (UVLO) function can be ENB implemented by the addition of a resistor divider from VIN to GND. For complete low current shutdown the ENB pin voltage needs to be less than 700mV. Soft-Start Control for Channel B. 9kΩ output resistance from the pin. Set RC time constant SSB with external capacitor for soft start ramp time. Ramp Time = 2.2x9kΩxC. BSB High-Side Driver Boost Pin. Connect a 10nF capacitor from this pin to SWB. NC No Connect. Supply Voltage Channel B. The MP2364 operates from a +4.75V to +23V unregulated input. INB Input Ceramic Capacitors should be close to this pin. SWB Switch Channel B. This connects the inductor to either INB through M1B or to PGB through M2B. Power Ground Channel B. This is the Power Ground Connection to the input capacitor PGB ground. Signal Ground Channel B. This pin is the signal ground reference for the regulated output voltage. For this reason care must be taken in its layout. This node should be placed outside SGB of the D1 to C1 ground path to prevent switching current spikes from inducing voltage noise into the part. Feedback Voltage for Channel A. This pin is the feedback voltage. The output voltage is ratio scaled FBA through a voltage divider, and the center point of the divider is connected to this pin. The voltage is compared to the on board 0.92V reference. Compensation Channel A. This is the output of the transconductance error amplifier. A series COMPA RC is placed on this pin for proper control loop compensation. Please refer to more in the datasheet. Enable/UVLO Channel A. A voltage greater than 2.62V enables operation. Leave ENA unconnected for automatic startup. An Under Voltage Lockout (UVLO) function can be ENA implemented by the addition of a resistor divider from VIN to GND. For complete low current shutdown the ENA pin voltage needs to be less than 700mV. 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MP2364 Rev. 1.4 3/22/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 4 TM MP2364 — DUAL 1.5A, 23V, 1.4MHz STEP-DOWN CONVERTER PIN FUNCTIONS (SOIC16) Pin # 1 2 3 4 5 6 Name SSA Description Soft-Start Control for Channel A. 9kΩ output resistance from the pin. Set RC time constant with external capacitor for soft start ramp time. Ramp Time = 2.2 x 9kΩ x C. BSA High-Side Driver Boost Pin. Connect a 10nF capacitor from this pin to SWA. Supply Voltage Channel A. The MP2364 operates from a +4.75V to +23V unregulated input. INA Input Ceramic Capacitors should be close to this pin. SWA Switch Channel A. This connects the inductor to either INA through M1A or to PGA through M2A. GNDA Ground A. Feedback Voltage for Channel B. This pin is the feedback voltage. The output voltage is ratio scaled FBB through a voltage divider, and the center point of the divider is connected to this pin. The voltage is compared to the on board 0.92V reference. Compensation Channel B. This is the output of the transconductance error amplifier. A series COMPB RC is placed on this pin for proper control loop compensation. Please refer to more in the datasheet. Enable/UVLO Channel B. A voltage greater than 2.62V enables operation. Leave ENB unconnected for automatic startup. An Under Voltage Lockout (UVLO) function can be ENB implemented by the addition of a resistor divider from VIN to GND. For complete low current shutdown the ENB pin voltage needs to be less than 700mV. Soft-Start Control for Channel B. 9kΩ output resistance from the pin. Set RC time constant SSB with external capacitor for soft start ramp time. Ramp Time = 2.2x9kΩxC. BSB High-Side Driver Boost Pin. Connect a 10nF capacitor from this pin to SWB. Supply Voltage Channel B. The MP2364 operates from a +4.75V to +23V unregulated input. INB Input Ceramic Capacitors should be close to this pin. SWB Switch Channel B. This connects the inductor to either INB through M1B or to PGB through M2B. GNDB Ground B. Feedback Voltage for Channel A. This pin is the feedback voltage. The output voltage is ratio scaled FBA through a voltage divider, and the center point of the divider is connected to this pin. The voltage is compared to the on board 0.92V reference. Compensation Channel A. This is the output of the transconductance error amplifier. A series COMPA RC is placed on this pin for proper control loop compensation. Please refer to more in the datasheet. Enable/UVLO Channel A. A voltage greater than 2.62V enables operation. Leave ENA unconnected for automatic startup. An Under Voltage Lockout (UVLO) function can be ENA implemented by the addition of a resistor divider from VIN to GND. For complete low current shutdown the ENA pin voltage needs to be less than 700mV. 7 8 9 10 11 12 13 14 15 16 MP2364 Rev. 1.4 3/22/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 5 TM MP2364 — DUAL 1.5A, 23V, 1.4MHz STEP-DOWN CONVERTER OPERATION The MP2364 is a dual channel current mode regulator. The COMP pin voltage is proportional to the peak inductor current. At the beginning of a cycle, the upper transistor M1 is off, and the lower transistor M2 is on (see Figure 1). The COMP pin voltage is higher than the current sense amplifier output, and the current comparator’s output is low. The rising edge of the 1.4MHz CLK signal sets the RS Flip-Flop. Its output turns off M2 and turns on M1 thus connecting the SW pin and inductor to the input supply. The increasing inductor current is sensed and amplified by the Current Sense Amplifier. Ramp compensation is summed to Current Sense Amplifier output and compared to the Error Amplifier output by the Current Comparator. When the sum of the Current Sense Amplifier output and the Slope Compensation signal exceeds the COMP pin voltage, the RS FlipFlop is reset. The MP2364 reverts to its initial M1 off, M2 on state. INA/ INB INTERNAL REGULATORS OSCILLATOR SLOPE COMP CLK If the sum of the Current Sense Amplifier output and the Slope Compensation signal does not exceed the COMP voltage, the falling edge of the CLK resets the Flip-Flop. The output of the Error Amplifier integrates the voltage difference between the feedback and the 0.92V bandgap reference. The polarity is such that a voltage at the FB pin lower than 0.92V increases the COMP pin voltage. Since the COMP pin voltage is proportional to the peak inductor current, an increase in its voltage increases current delivered to the output. The lower 10Ω switch ensures that the bootstrap capacitor voltage is charged during light load conditions. External Schottky Diode D1 carries the inductor current when M1 is off (see Figure 1). CURRENT SENSE AMPLIFIER + -- 5V 210/1400KHz + BSA/ BSB Q Q SWA/ SWB + S R 0.7V ENA/ ENB -- SHUTDOWN COMPARATOR LOCKOUT COMPARATOR -- CURRENT COMPARATOR -2.29V/ 2.50V 1.8V + -ERROR AMPLIFIER + COMPA/ COMPB PGA/ PGB 0.92V SGA/ SGB SSA/ SSB MP2364_BD02 FREQUENCY FOLDBACK COMPARATOR -- 0.4V + FBA / FBB Figure 1—Functional Block Diagram (Diagram portrays ½ of the MP2364) MP2364 Rev. 1.4 3/22/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 6 TM MP2364 — DUAL 1.5A, 23V, 1.4MHz STEP-DOWN CONVERTER APPLICATION INFORMATION COMPONENT SELECTION The MP2364 has two channels: A and B. The following formulas are used for component selection of both channels. Refer to components with reference “A” for channel A, and components with reference “B” for channel B, respectively, as indicated in Figure 3 (i.e. – R1A for Channel A and R1B for Channel B). Setting the Output Voltage The output voltage is set using a resistive voltage divider from the output voltage to FB pin. The voltage divider divides the output voltage down to the feedback voltage by the ratio: VFB = VOUT R2 R1 + R2 switch current limit. The inductance value can be calculated by: L1 = ⎛ ⎞ VOUT V × ⎜1 − OUT ⎟ ⎜ fS × ∆IL ⎝ VIN ⎟ ⎠ Where VIN is the input voltage, fS is the switching frequency, and ∆IL is the peak-topeak inductor ripple current. Choose an inductor that will not saturate under the maximum inductor peak current. The peak inductor current can be calculated by: ILP = ILOAD + ⎛ ⎞ VOUT V × ⎜1 − OUT ⎟ ⎜ 2 × fS × L1 ⎝ VIN ⎟ ⎠ Where ILOAD is the load current. Output Rectifier Diode The output rectifier diode supplies the current to the inductor when the high-side switch is off. To reduce losses due to the diode forward voltage and recovery times, use a Schottky diode. Choose a diode whose maximum reverse voltage rating is greater than the maximum input voltage, and whose current rating is greater than the maximum load current. Input Capacitor The input current to the step-down converter is discontinuous, therefore a capacitor is required to supply the AC current to the step-down converter while maintaining the DC input voltage. Use low ESR capacitors for the best performance. Ceramic capacitors are preferred, but tantalum or low-ESR electrolytic capacitors may also suffice. Since the input capacitor (C1) absorbs the input switching current it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated by: I C1 = ILOAD × VOUT ⎛ VOUT ×⎜ 1− VIN ⎜ VIN ⎝ ⎞ ⎟ ⎟ ⎠ Thus the output voltage is: VOUT = 0.92 V × R1 + R2 R2 Where VFB is the feedback voltage and VOUT is the output voltage A typical value for R2 can be as high as 100kΩ, but a typical value is 10kΩ. Using that value, R1 is determined by: R1 = R2 × ( VOUT − 1) 0.92V For example, for a 3.3V output voltage, R2 is 10kΩ, and R1 is 25.9kΩ. Inductor The inductor is required to supply constant current to the output load while being driven by the switched input voltage. A larger value inductor will result in less ripple current that will result in lower output ripple voltage. However, the larger value inductor will have a larger physical size, higher series resistance, and/or lower saturation current. A good rule for determining the inductance to use is to allow the peak-to-peak ripple current in the inductor to be approximately 30% of the maximum switch current limit. Also, make sure that the peak inductor current is below the maximum The worst-case condition occurs at VIN = 2VOUT, where: IC1 = ILOAD 2 MP2364 Rev. 1.4 3/22/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 7 TM MP2364 — DUAL 1.5A, 23V, 1.4MHz STEP-DOWN CONVERTER For simplification, choose the input capacitor whose RMS current rating greater than half of the maximum load current. The input capacitor can be electrolytic, tantalum or ceramic. When using electrolytic or tantalum capacitors, a small, high quality ceramic capacitor, i.e. 0.1µF, should be placed as close to the IC as possible. When using ceramic capacitors, make sure that they have enough capacitance to provide sufficient charge prevent excessive voltage ripple at input. The input voltage ripple caused by capacitance can be estimated by: ∆VIN = ILOAD VOUT ⎛ V × × ⎜1 − OUT ⎜ C1 VIN ⎝ VIN ⎞ ⎟ ⎟ ⎠ MP2364 can be optimized for a wide range of capacitance and ESR values. Compensation Components The MP2364 employs current mode control on each channel for easy compensation and fast transient response. The system stability and transient response are controlled through the COMP pin. COMP pin is the output of the internal transconductance error amplifier. A series capacitor-resistor combination sets a pole-zero combination to control the characteristics of the control system. The DC gain of the voltage feedback loop is given by: A VDC = R LOAD × G CS × A VEA × VFB VOUT Output Capacitor The output capacitor is required to maintain the DC output voltage. Ceramic, tantalum, or low ESR electrolytic capacitors are recommended. Low ESR capacitors are preferred to keep the output voltage ripple low. The output voltage ripple can be estimated by: ∆VOUT = VOUT ⎛ V × ⎜1 − OUT f S × L1 ⎜ VIN ⎝ ⎞ ⎞⎛ 1 ⎟ ⎟ × ⎜ R ESR + ⎟⎜ 8 × f S × C2 ⎟ ⎠⎝ ⎠ Where AVEA is the error amplifier voltage gain, GCS is the current sense transconductance and RLOAD is the load resistor value. The system has two poles of importance. One is due to the compensation capacitor (C3) and the output resistor of error amplifier, and the other is due to the output capacitor and the load resistor. These poles are located at: fP1 = fP2 = G EA 2π × C3 × A VEA 1 2π × C2 × R LOAD Where L1 is the inductor value, C2 is the output capacitance value, and RESR is the equivalent series resistance (ESR) value of the output capacitor. In the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. The output voltage ripple is mainly caused by the capacitance. For simplification, the output voltage ripple can be estimated by: ∆VOUT = VOUT 8 × fS 2 is Where GEA transconductance. the error amplifier ⎞ ⎛ V × ⎜1 − OUT ⎟ ⎜ VIN ⎟ × L1 × C2 ⎝ ⎠ The system has one zero of importance, due to the compensation capacitor (C3) and the compensation resistor (R3). This zero is located at: f Z1 = 1 2π × C3 × R3 In the case of tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated to: ∆VOUT = VOUT ⎛ V ⎞ × ⎜1 − OUT ⎟ × RESR fS × L1 ⎝ VIN ⎠ The system may have another zero of importance, if the output capacitor has a large capacitance and/or a high ESR value. The zero, due to the ESR and capacitance of the output capacitor, is located at: The characteristics of the output capacitor also affect the stability of the regulation system. The MP2364 Rev. 1.4 3/22/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 8 TM MP2364 — DUAL 1.5A, 23V, 1.4MHz STEP-DOWN CONVERTER 1 2π × C2 × R ESR fESR = In this case (as shown in Figure 2), a third pole set by the compensation capacitor (C6) and the compensation resistor (R3) is used to compensate the effect of the ESR zero on the loop gain. This pole is located at: fP3 = 1 2π × C6 × R3 3. Determine if the second compensation capacitor (C6) is required. It is required if the ESR zero of the output capacitor is located at less than half of the switching frequency, or the following relationship is valid: f 1 4 2π × R3 × f C BSA/B MP2364 SWA/B 10nF MP2364_F02 Figure 2—External Bootstrap Diode This diode is also recommended for high duty cycle operation (when VOUT >65%) and high VIN output voltage (VOUT>12V) applications. Where R3 is the compensation resistor value. MP2364 Rev. 1.4 3/22/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 9 TM MP2364 — DUAL 1.5A, 23V, 1.4MHz STEP-DOWN CONVERTER TYPICAL APPLICATION CIRCUITS 12V 3.3V @ 1.5A 1 2 3 4 SSA NC1 BSA ENA COMPA FBA SGB 20 19 18 17 16 15 14 13 12 11 OFF ON C6A 82pF D1B B230A C5B 10nF C3A 2.2nF C5A INA 10nF 5 D1A B230A 6 7 8 9 SWA PGA SGA FBB COMPB ENB MP2364 PGB SWB INB NC2 BSB SSB 2.5V @ 1.5A OFF ON 10 C3B 3.3nF MP2364_F03 Figure 3—2.5V @ 1.5A and 3.3V @ 1.5A Application Circuit MP2364 Rev. 1.4 3/22/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 10 TM MP2364 — DUAL 1.5A, 23V, 1.4MHz STEP-DOWN CONVERTER PACKAGE INFORMATION TSSOP20F 0.0256(0.650)TYP 0.004(0.090) 0.010(0.250) GATE PLANE 0.169 0.177 (4.300) (4.500) 0.004(0.090) 0o-8o 0.018(0.450) 0.030(0.750) 0.039(1.000)REF 0.105 (2.67) 0.118 (3.00) pad width 0.030(0.750) 0.244 0.260 (6.200) (6.600) DETAIL "A" PIN 1 IDENT. 0.030(0.750) 0.150 (3.80) 0.165 (4.19) pad length SEE DETAIL "B" SEE DETAIL "A" 0.075(0.190) 0.012(0.300) 0.004(0.090) 0.008(0.200) 0.252 (6.400) 0.260 (6.600) 0.047(1.200) max 0.007(0.190) 0.012(0.300) 0.032(0.800) 0.041(1.050) 0.002(0.050) 0.006(0.150) 0.004(0.090) 0.006(0.160) SEATING PLANE 0.007(0.190) 0.010(0.250) DETAIL "B" NOTE: 1) Control dimension is in inches. Dimension in bracket is millimeters. MP2364 Rev. 1.4 3/22/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 11 TM MP2364 — DUAL 1.5A, 23V, 1.4MHz STEP-DOWN CONVERTER SOIC16 0.745(18.92) 0.765(19.43) 16 9 PIN 1 ID 0.240(6.10) 0.260(6.60) 1 8 TOP VIEW 0.320( 8.13) 0.400(10.16) 0.300(7.62) 0.325(8.26) 0.125(3.18) 0.145(3.68) 0.015(0.38) 0.035(0.89) 0.120(3.05) 0.140(3.56) 0.008(0.20) 0.014(0.36) 0.050(1.27) 0.065(1.65) 0.015(0.38) 0.021(0.53) 0.100(2.54) BSC FRONT VIEW SIDE VIEW NOTE: 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH AND WIDTH DO NOT INCLUDE MOLD FLASH, OR PROTRUSIONS. 3) DRAWING CONFORMS TO JEDEC MS-001, VARIATION BB. 4) DRAWING IS NOT TO SCALE. NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP2364 Rev. 1.4 3/22/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 12