MP4433
36V, 3A, Low Quiescent Current,
Synchronous, Step-Down Converter
DESCRIPTION
FEATURES
The MP4433 is a synchronous, step-down,
switching
regulator
with
programmable
frequency (350kHz to 2.5MHz) and integrated,
internal, high-side and low-side power
MOSFETs. The MP4433 provides up to 3A of
highly efficient output current with current mode
control for fast loop response.
The wide 3.3V to 36V input range
accommodates a variety of step-down
applications in automotive input environments.
The MP4433 is ideal for battery-powered
applications due to its extremely low quiescent
current.
The MP4433 employs advanced asynchronous
mode (AAM) to achieve high efficiency in lightload condition by scaling down the switching
frequency to reduce switching and gate driving
losses.
Standard features include soft start, external
clock synchronization, enable control, and
power good indication. High-duty cycle and low
dropout mode are provided for automotive coldcrank.
Over-current protection (OCP) with valleycurrent detection is employed to prevent the
inductor current from running away. Hiccup
mode reduces the average current greatly in
short-circuit condition. Thermal shutdown
provides reliable and fault-tolerant operation.
The MP4433 is available in a QFN-16
(3mmx4mm) package.
Wide 3.3V to 36V Operating Input Range
3A Continuous Output Current
1μA Low Shutdown Mode Current
10μA Sleep Mode Quiescent Current
Internal 90mΩ High-Side and 40mΩ LowSide MOSFETs
350kHz to 2.5MHz Programmable Switching
Frequency
Fixed Output Options: 3.3V, 3.8V, 5V
Synchronize to External Clock, Selectable
In-Phase or 180°Out-of-Phase
Power Good Indicator
Programmable Soft-Start Time
80ns Minimum On Time
Selectable Forced CCM or AAM
Low Dropout Mode
Over-Current Protection with Valley-Current
Detection and Hiccup
Available in a QFN-16 (3mmx4mm)
Package
APPLICATIONS
Automotive Systems
Industrial Power Systems
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS” and “The Future of Analog IC Technology” are
registered trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
VIN
3.3 to 36V
VIN
BST
VOUT
EN
SYNC
SW
MP4433
PHASE
GND
FREQ
FB
MP4433 Rev. 1.01
1/12/2018
VCC
PG
BIAS
SS
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MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number*
MP4433GL
Package
QFN-16 (3mmx4mm)
Top Marking
See Below
* For Tape & Reel, add suffix –Z (e.g. MP4433GL–Z)
TOP MARKING
MP: MPS prefix
Y: Year code
W: Week code
4433 : First four digits of the part number
LLL: Lot number
PACKAGE REFERENCE
TOP VIEW
FREQ
16
FB
SS
AGND
15
14
13
PHASE
1
12
VCC
VIN
2
11
BST
SW
3
10
SW
PGND
4
9
5
EN
6
SYNC
7
PG
PGND
8
BIAS
QFN-16 (3mmx4mm)
MP4433 Rev. 1.01
1/12/2018
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MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
(3)
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance
Supply voltage (VIN) ...................... -0.3V to 40V
Switch voltage (VSW) ........... -0.3V to VIN + 0.3V
BST voltage (VBST) ............................VSW + 6.5V
EN voltage (VEN) ............................ -0.3V to 40V
BIAS voltage (VBIAS) ....................... -0.3V to 20V
All other pins .................................... -0.3V to 6V
(2)
Continuous power dissipation (TA = +25°C)
QFN-16 (3mmx4mm) .................................2.6W
Junction temperature ............................... 150°C
Lead temperature .................................... 260°C
Storage temperature .................. -65°C to 150°C
NOTES:
1) Absolute maximum ratings are rated under room temperature
unless otherwise noted. Exceeding these ratings may
damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/ θJA. Exceeding the maximum allowable power dissipation
produces an excessive die temperature, causing the regulator
to go into thermal shutdown. Internal thermal shutdown
circuitry protects the device from permanent damage.
3) Measured on JESD51-7, 4-layer PCB.
QFN-16 (3mmx4mm) ............ 48 ....... 11 ... °C/W
Recommended Operating Conditions
Supply voltage (VIN) ....................... 3.3V to 36V
Operating junction temp (TJ) for 1000h lifetime ..
.......................................... -40°C to +125°C
Operating junction temp (TJ) for 408h lifetime ....
.......................................... -40°C to +150°C
MP4433 Rev. 1.01
1/12/2018
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MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 12V, VEN = 2V, TJ = -40°C to +125°C
+25°C.
Parameter
Symbol
VIN quiescent current
IQ
VIN shutdown current
ISHDN
VIN under-voltage lockout
threshold rising
VIN under-voltage lockout
threshold hysteresis
, unless otherwise noted. Typical values are at TJ =
Condition
Typ
Max
VFB = 0.85V, no load, no switching,
TJ = +25°C
10
18
VFB = 0.85V, no load, no switching
10
25
VEN = 0V
1
5
µA
2.8
3.2
V
INUVRISING
Min
2.4
INUVHYS
Feedback reference voltage
VREF
Switching frequency
Minimum on time
(4)
FSW
(5)
150
VSYNC_LOW
Sync input high voltage
VSYNC_HIGH
µA
mV
784
800
816
mV
TJ = 25°C
792
800
808
mV
RFREQ = 180kΩ or from sync clock
400
475
550
kHz
RFREQ = 82kΩ or from sync clock
850
1000
1150
kHz
RFREQ = 27kΩ or from sync clock
2250
2500
2750
kHz
TON_MIN
Sync input low voltage
Units
80
ns
0.4
1.8
V
V
Current limit
ILIMIT_HS
Duty cycle = 40%
4.7
5.8
7.3
A
Low-side valley current limit
ILIMIT_LS
VOUT = 3.3V, L = 4.7µH
3.1
4.4
5.7
A
ZCD current
IZCD
Reverse current limit
0.1
A
ILIMIT_REVERSE
3
Switch leakage current
ISW_LKG
0.01
1
µA
HS switch on resistance
RON_HS
90
155
mΩ
LS switch on resistance
RON_LS
40
75
mΩ
5
10
15
µA
0.9
1.05
1.2
V
Soft-start current
ISS
EN rising threshold
VSS = 0.8V
VEN_RISING
EN threshold hysteresis
VEN_HYS
PG rising threshold (VFB/VREF)
PGRISING
PG falling threshold (VFB/VREF)
PGFALLING
PG deglitch timer
TPG_DEGLITCH
PG output voltage low
VPG_LOW
VCC regulator
120
mV
VFB rising
85
90
95
VFB falling
105
110
115
VFB falling
79
84
89
VFB rising
Thermal shutdown hysteresis
(5)
%
%
PG from low to high
30
µs
PG from high to low
50
µs
ISINK = 2mA
0.2
0.4
5
ICC = 5mA
(5)
%
113.5 118.5 123.5
VCC
VCC load regulation
Thermal shutdown
VBST - VSW = 5V
A
V
V
3
%
TSD
170
C
TSD_HYS
20
°C
NOTE:
4) Not tested in production and guaranteed by over-temperature correlation.
5) Not tested in production and guaranteed by design and characterization.
MP4433 Rev. 1.01
1/12/2018
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MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL CHARACTERISTICS
VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted.
MP4433 Rev. 1.01
1/12/2018
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MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL CHARACTERISTICS (continued)
VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted.
MP4433 Rev. 1.01
1/12/2018
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MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MP4433 Rev. 1.01
1/12/2018
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MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MP4433 Rev. 1.01
1/12/2018
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MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MP4433 Rev. 1.01
1/12/2018
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MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MP4433 Rev. 1.01
1/12/2018
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MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MP4433 Rev. 1.01
1/12/2018
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MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MP4433 Rev. 1.01
1/12/2018
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MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MP4433 Rev. 1.01
1/12/2018
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MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MP4433 Rev. 1.01
1/12/2018
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MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
PIN FUNCTIONS
Pin #
Name
1
PHASE
2
VIN
3, 10
SW
4, 9
PGND
5
EN
6
SYNC
7
PG
8
BIAS
11
BST
12
VCC
13
AGND
Switch node. SW is the output of the internal power switch.
14
SS
15
FB
16
FREQ
MP4433 Rev. 1.01
1/12/2018
Description
Selectable in-phase or 180°out-of-phase of SYNC input. Drive PHASE high to be
in-phase; drive PHASE low to be 180°out-of-phase.
Input supply. VIN supplies power to all the internal control circuitries and the power
switch connected to SW. Place a decoupling capacitor to ground close to VIN to
minimize switching spikes.
Power ground. PGND is the reference ground of the power device. PGND requires
careful consideration during PCB layout. For best results, connect PGND with copper
pours and vias.
Enable. Pull EN below the specified threshold to shut down the chip. Pull EN above
the specified threshold to enable the chip.
Synchronize. Apply a 350kHz to 2.5MHz clock signal to SYNC to synchronize the
internal oscillator frequency to the external clock. The external clock should be at
least 250kHz larger than the RFREQ set frequency. SYNC can also be used to select
forced CCM or AAM. Drive SYNC high before the chip starts up to choose forced
CCM; drive SYNC low or leave SYNC floating to choose AAM.
Power good Indicator. The output of PG is an open drain. PG goes high if the
output voltage is within ±10% of the nominal voltage.
External power supply for internal regulator. Connecting BIAS to an external
power supply (5V ≤ VBIAS ≤ 18V) reduces power dissipation and increases efficiency.
Float BIAS or connect BIAS to ground if it is not being used.
Bootstrap. BST is the positive power supply for the high-side MOSFET driver
connected to SW. Connect a bypass capacitor between BST and SW.
Internal bias supply. VCC supplies power to the internal control circuit and gate
drivers. A ≥1µF decoupling capacitor to ground is required close to VCC.
Analog ground. AGND is the reference ground of the logic circuit.
Soft-start input. Place an external capacitor from SS to AGND to set the soft-start
period. The MP4433 sources 10µA from SS to the soft-start capacitor at start-up. As
the SS voltage rises, the feedback threshold voltage increases to limit inrush current
during start-up.
Feedback input. Connect FB to the tap of an external resistor divider from the output
to AGND to set the output voltage. The feedback threshold voltage is 0.8V. Place the
resistor divider as close to FB as possible. Avoid placing vias on the FB traces.
Switching frequency program. Connect a resistor from FREQ to ground to set the
switching frequency.
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MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
BLOCK DIAGRAM
BIAS
VCC
VCC
VCC
Regulator
VIN
VCC
EN
Vref
Reference
FREQ
BST
Oscillator
PLL
SYNC
ISW
PHASE
PG
Logic
+
-
VFB
110%xVref
+
-
90%xVref
VFB
Error Amplifier
Vref
SS
FB
VFB
+
+
-
Control Logic,
OCP,
OTP,
BST Refresh
SW
VCC
VC
R1
460kΩ
C1
52pF
C2
0.2pF
Ireverse
PGND
AGND
Figure 1: Functional Block Diagram
MP4433 Rev. 1.01
1/12/2018
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MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
TIMING SEQUENCE
VIN
0
SW
0
EN
EN
T h r e s h ol d
0
VCC
V
CC
T h r e sh ol d
0
118.5% Vref
90% Vref
50% REF 84% Vref
Vo
110% Vref
SS
0
I L =I L i mi t
IL
0
PG
30µ s
50µ s
30µ s
50µs
30µ s
0
Start-Up
N o r m al
OCP
N o r m al
OC
Release
OV
N o r m al
EN Shutdown
Figure 2: Timing Sequence
MP4433 Rev. 1.01
1/12/2018
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MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
OPERATION
The MP4433 is a high-frequency, synchronous,
rectified, step-down, switch-mode converter
with integrated, internal, high-side and low-side
power MOSFETs. The MP4433 offers a very
compact solution that achieves 3A of
continuous output current with excellent load
and line regulation over a wide 3.3V to 36V
input supply range. The MP4433 features
switching frequency programmable from
350kHz to 2.5MHz, external soft start, power
good indication, and precision current limit. Its
very low operational quiescent current makes it
suitable for battery-powered applications.
Pulse Width Modulation (PWM) Control
At moderate-to-high output current, the MP4433
operates in a fixed-frequency, peak-currentcontrol mode to regulate the output voltage. An
internal clock initiates a PWM cycle. At the
rising edge of the clock, the high-side power
MOSFET (HS-FET) is turned on, and the
inductor current rises linearly to provide energy
to the load. The HS-FET remains on until its
current reaches the value set by the COMP
voltage (VCOMP), which is the output of the
internal error amplifier. If the current in the HSFET does not reach VCOMP in one PWM period,
the HS-FET remains on, saving a turn-off
operation. When the HS-FET is off, it remains
off until the next clock cycle begins. The lowside MOSFET (LS-FET) turns on immediately
while the inductor current flows through it. To
avoid a shoot-through, dead time is inserted to
prevent the HS-FET and LS-FET from turning
on at the same time. For each turn on and off in
a switching cycle, the HS-FET remains on and
off with a minimum on and off time limit.
Forced CCM Mode and AAM Mode
The MP4433 has selectable forced continuous
conduction mode (CCM) and advanced
asynchronous mode (AAM) (see Figure 3).
Drive SYNC above its specified threshold
before the chip starts up to force the device into
CCM with a fixed frequency, regardless of the
output load current. Once the device is in CCM,
SYNC can be pulled low again or driven with an
external clock if needed. The advantage of
CCM is a controllable frequency and smaller
output ripple, but it also has low efficiency at
light load.
MP4433 Rev. 1.01
1/12/2018
Drive SYNC below its specified threshold or
leave SYNC floating before the chip starts up to
enable AAM power-save mode. The MP4433
first enters non-synchronous operation for as
long as the inductor current approaches zero at
light load. If the load is further decreased or is
at no load, making VCOMP below the internally
set AAM value (VAAM), the MP4433 enters sleep
mode, consuming very low quiescent current to
further improve light-load efficiency.
In sleep mode, the internal clock is blocked first,
and the MP4433 skips some pulses. Since the
FB voltage (VFB) is lower than the internal 0.8V
reference (VREF), VCOMP ramps up until it
crosses over VAAM. Then the internal clock is
reset, and the crossover time is taken as the
benchmark of the next clock. This control
scheme helps achieve high efficiency by scaling
down the frequency to reduce switching and
gate driver losses during light-load or no-load
conditions.
When the output current increases from light
load condition, VCOMP becomes larger, and the
switching frequency increases. If the DC value
of VCOMP exceeds VAAM, the operation mode
resumes discontinuous conduction mode (DCM)
or CCM, which have a constant switching
frequency.
Inductor
Current
Inductor
Current
Forced CCM
AAM
t
t
Load
Load
Decreased
t Decreased
t
t
t
Figure 3: Forced CCM and AAM
Error Amplifier (EA)
The error amplifier compares VFB with VREF and
outputs a current proportional to the difference
between the two. This output current then
charges
or
discharges
the
internal
compensation network to form VCOMP, which
controls the power MOSFET current. The
optimized internal compensation network
minimizes the external component counts and
simplifies the control loop design.
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MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
Internal Regulator and BIAS
Most of the internal circuitry is powered by the
5V internal regulator. This regulator takes VIN
and operates in the full VIN range. When VIN
exceeds 5V, the output of the regulator is in full
regulation. When VIN falls below 5V, the output
decreases following VIN. A decoupling ceramic
capacitor is needed close to VCC.
For better thermal performance, connect BIAS
to an external power supply between 5V to 18V.
The BIAS supply overrides VIN to power the
internal regulator. Using the BIAS supply allows
VCC to be derived from a high-efficiency
external source, such as VOUT. Float BIAS or
connect BIAS to ground if it is not being used.
Under-Voltage Lockout (UVLO)
Under-voltage lockout (UVLO) protects the chip
from operating at an insufficient supply voltage.
The UVLO comparator monitors the output
voltage of the internal regulator (VCC). The
UVLO rising threshold is about 2.8V with a
150mV hysteresis.
Enable Control (EN)
EN is a digital control pin that turns the
regulator on and off. When EN is pulled below
its threshold voltage, the chip is put into the
lowest shutdown current mode. Pulling EN
above its threshold voltage turns on the part.
Do not float EN.
Power Good Indicator (PG)
The MP4433 has a power good (PG) indication.
PG is the open drain of a MOSFET and should
be connected to VCC or another voltage source
through a resistor (e.g.: 100kΩ). In the
presence of an input voltage, the MOSFET
turns on so that PG is pulled low before SS is
ready. When the regulator output is within
±10% of its nominal output, the PG output is
pulled high after a delay (typically 30μs). When
the output voltage moves outside this range
with a hysteresis, the PG output is pulled low
with a 50μs delay to indicate a failure output
status.
Programmable Frequency
The oscillating frequency of the MP4433 can be
programmed either by an external frequency
resistor (RFREQ) or by a logic level
synchronization clock.
MP4433 Rev. 1.01
1/12/2018
The frequency resistor should be located
between FREQ and ground as close to the device
as possible. The value of RFREQ can be estimated
with Equation (1):
R FREQ (kΩ)
170000
f sw
1.11
(1)
(kHz)
The calculated resistance may need fine tuning
with a bench test. Do not float FREQ even if an
external SYNC clock is added.
SYNC and PHASE
The internal oscillator frequency can also be
synchronized to an external clock ranging from
350kHz to 2.5MHz through SYNC. The external
clock should be at least 250kHz larger than the
RFREQ set frequency. Ensure that the high
amplitude of the SYNC clock is higher than
1.8V and the low amplitude is lower than 0.4V.
There is no pulse width requirement, but there
is always a parasitic capacitance of the pad, so
if the pulse width is too short, a clear rising and
falling edge may not be seen due to the
parasitic capacitance. A pulse longer than
100ns is recommended in application.
PHASE is used when two or more MP4433
devices are in parallel with the same SYNC
clock. Pulling PHASE high forces the device to
operate in-phase of the SYNC clock. Pulling
PHASE low forces the device to be 180°out-ofphase of the SYNC clock. By setting different
voltages of PHASE, two devices can operate in
180° out-of-phase to reduce the total input
current ripple, so a smaller input bypass
capacitor can be used (see Figure 4). The
PHASE rising threshold is about 2.5V with a
400mV hysteresis.
SW1: Phase high
SW2: Phase low
SW1, 2 has a 180o phase shift
SYNC
CLK
SW1
SW2
t
Figure 4: In-Phase and 180°Out-of-Phase
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MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
Soft Start (SS)
Soft start is implemented to prevent the
converter output voltage from overshooting
during start-up.
When the chip starts up, an internal current
source begins charging the external soft-start
capacitor. When the soft-start voltage (VSS) is
lower than the internal reference (VREF), VSS
overrides VREF, so the error amplifier uses VSS
as the reference. When VSS is higher than VREF,
the error amplifier uses VREF as the reference.
The soft-start time (tSS) set by the external SS
capacitor can be calculated with Equation (2):
t SS (ms)
CSS (nF) VREF (V)
ISS (A)
(2)
Where CSS is the external SS capacitor, VREF =
0.8V, and ISS is the internal 10μA SS charge
current.
SS can be used for tracking and sequencing.
Pre-Bias Start-Up
At start-up, if VFB is higher than VSS (the output
has a pre-bias voltage), neither the HS-FET or
LS-FET turn on until VSS is higher than VFB.
Over-Current Protection (OCP) and Hiccup
The MP4433 has cycle-by-cycle peak current
limit protection with valley-current detection and
hiccup mode.
The power MOSFET current is sensed
accurately via a current sense MOSFET. The
current is then fed to the high-speed current
comparator for current-mode control purposes.
During the HS-FET on-state, if the sensed
current exceeds the peak current limit value set
by the COMP high-clamp voltage, the HS-FET
turns off immediately. Then the LS-FET turns
on to discharge the energy, and the inductor
current decreases. The HS-FET remains off
unless the inductor valley current is lower than
a certain current threshold (the valley current
limit), even though the internal clock pulses
high.
MP4433 Rev. 1.01
1/12/2018
If the inductor current does not drop below the
valley current limit when the internal clock
pulses high, the HS-FET misses the clock, and
the switching frequency decreases to half the
nominal value. Both the peak and valley current
limits keep the inductor current from running
away during an overload or short-circuit
condition.
When the output is shorted to ground, causing
the output voltage to drop below 55% of its
nominal output, meanwhile the peak current
limit is kicked, the device will consider this an
output dead short and trigger hiccup mode
immediately to periodically restart the part.
In hiccup mode, the MP4433 disables its output
power stage and slowly discharges the softstart capacitor. The MP4433 restarts with a full
soft start when the soft-start capacitor is fully
discharged. If the short-circuit condition still
remains after the soft-start ends, the device
repeats this operation until the fault is removed
and the output returns to the regulation level.
This protection mode reduces the average
short-circuit current greatly to alleviate thermal
issues and protect the regulator.
Floating Driver and Bootstrap Charging
A 0.1μF to 1μF external bootstrap capacitor
powers the floating power MOSFET driver. The
floating driver has its own UVLO protection with
a rising threshold of 2.5V and a hysteresis of
200mV.
The bootstrap capacitor voltage is charged to
~5V from VCC through a PMOS pass transistor
when the LS-FET is on.
At high duty cycle operation or sleep-mode
condition, the time period available to the
bootstrap charging is less, so the bootstrap
capacitor may not be charged sufficiently. In
case the external circuit does not have
sufficient voltage or time to charge the
bootstrap capacitor, extra external circuitry can
be used to ensure that the bootstrap voltage in
the normal operation region.
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© 2018 MPS. All Rights Reserved.
20
MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
BST Refresh
To improve drop out, the MP4433 is designed
to operate at close to 100% duty cycle for as
long as the BST to SW voltage is greater than
2.5V. When the voltage from BST to SW drops
below 2.5V, the HS-FET is turned off using a
UVLO circuit, which forces the LS-FET on to
refresh the charge on the BST capacitor.
Since the supply current sourced from the BST
capacitor is low, the HS-FET can remain on for
more switching cycles than are required to
refresh the capacitor, thus making the effective
duty cycle of the switching regulator high.
The effective duty cycle during dropout of the
regulator is mainly influenced by the voltage
drops across the HS-FET, LS-FET, inductor
resistance, and printed circuit board resistance.
Thermal Shutdown
Thermal shutdown is implemented to prevent
the chip from running away thermally. When the
silicon die temperature exceeds its upper
threshold, the power MOSFETs shut down.
When the temperature drops below its lower
threshold, the chip is enabled again.
MP4433 Rev. 1.01
1/12/2018
Start-Up and Shutdown
If both VIN and EN exceed their appropriate
thresholds, the chip starts up. The reference
block starts first, generating a stable reference
voltage and current, and then the internal
regulator is enabled. The regulator provides a
stable supply for the rest of the circuitries.
While the internal supply rail is up, an internal
timer holds the power MOSFET off for about
50µs to blank the start-up glitches. When the
soft-start block is enabled, it first holds its SS
output low to ensure that the rest of the
circuitries are ready, and then slowly ramps up.
Three events can shut down the chip: VIN low,
EN low, and thermal shutdown. During the
shutdown procedure, the signaling path is
blocked first to avoid any fault triggering. VCOMP
and the internal supply rail are then pulled down.
The floating driver is not subject to this
shutdown command, but its charging path is
disabled.
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21
MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
APPLICATION INFORMATION
Setting the Output Voltage
The external resistor divider connected to FB
sets the output voltage (see Figure 5).
ICIN ILOAD
VOUT
V
(1 OUT )
VIN
VIN
The worst-case condition occurs at VIN = 2VOUT,
shown in Equation (5):
ICIN
MP4433
RFB1
FB
Figure 5: Feedback Network
Choose RFB1 to be around 40kΩ. RFB2 can then
be calculated with Equation (3):
R FB1
VOUT
1
0.8V
(3)
Table 1 lists the recommended feedback
resistor values for common output voltages.
Table 1: Resistor Selection for Common Output
Voltages
VOUT (V)
RFB1 (kΩ)
RFB2 (kΩ)
3.3
41.2 (1%)
13 (1%)
5
68.1 (1%)
13 (1%)
ILOAD
2
(5)
For simplification, choose an input capacitor
with an RMS current rating greater than half of
the maximum load current.
Vout
RFB2
R FB2
(4)
Selecting the Input Capacitor
The input current to the step-down converter is
discontinuous and therefore requires a
capacitor to supply AC current to the converter
while maintaining the DC input voltage. For the
best performance, use low ESR capacitors.
Ceramic capacitors with X5R or X7R dielectrics
are highly recommended because of their low
ESR and small temperature coefficients.
For most applications, use a 4.7µF to 10µF
capacitor. It is strongly recommended to use
another lower-value capacitor (e.g.: 0.1µF) with
a small package size (0603) to absorb highfrequency switching noise. Place the smaller
capacitor as close to VIN and GND as possible.
The input capacitor can be electrolytic, tantalum,
or ceramic. When using electrolytic or tantalum
capacitors, add a small, high-quality ceramic
capacitor (e.g.: 0.1μF) as close to the IC as
possible. When using ceramic capacitors,
ensure that they have enough capacitance to
provide a sufficient charge to prevent excessive
voltage ripple at input. The input voltage ripple
caused by capacitance can be estimated with
Equation (6):
VIN
ILOAD
V
V
OUT (1 OUT )
fSW CIN VIN
VIN
(6)
Selecting the Output Capacitor
The output capacitor maintains the DC output
voltage. Use ceramic, tantalum, or low-ESR
electrolytic capacitors. For best results, use low
ESR capacitors to keep the output voltage
ripple low. The output voltage ripple can be
estimated with Equation (7):
V
V
1
VOUT OUT (1 OUT ) (RESR
) (7)
fSW L
VIN
8fSW COUT
Where L is the inductor value, and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
For ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency, and the capacitance causes the
majority of the output voltage ripple.
Since CIN absorbs the input switching current, it
requires an adequate ripple current rating. The
RMS current in the input capacitor can be
estimated with Equation (4):
MP4433 Rev. 1.01
1/12/2018
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22
MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
For simplification, the output voltage ripple can
be estimated with Equation (8):
VOUT
VOUT
V
(1 OUT ) (8)
8 fSW L COUT
VIN
2
For tantalum or electrolytic capacitors, the ESR
dominates the impedance at the switching
frequency. For simplification, the output ripple
can be approximated with Equation (9):
VOUT
VOUT
V
(1 OUT ) RESR
fSW L
VIN
VIN UVLO Setting
The MP4433 has an internal, fixed, undervoltage lockout (UVLO) threshold. The rising
threshold is 2.8V, while the falling threshold is
about 2.65V. For applications requiring a higher
UVLO point, an external resistor divider
between VIN and EN can be used to achieve a
higher equivalent UVLO threshold (see Figure
6).
VIN
VIN
(9)
R UP
EN
The characteristics of the output capacitor also
affect the stability of the regulation system. The
MP4433 can be optimized for a wide range of
capacitance and ESR values.
Selecting the Inductor
A 1µH to 10µH inductor with a DC current rating
at least 25% higher than the maximum load
current is recommended for most applications.
For higher efficiency, choose an inductor with a
lower DC resistance. A larger value inductor
results in less ripple current and a lower output
ripple voltage, but also has a larger physical
size, higher series resistance, and lower
saturation current. A good rule for determining
the inductor value is to allow the inductor ripple
current to be approximately 30% of the
maximum load current. The inductance value
can then be calculated with Equation (10):
L
VOUT
V
(1 OUT )
fSW IL
VIN
(10)
Where ∆IL is the peak-to-peak inductor ripple
current.
Choose the inductor ripple current to be
approximately 30% of the maximum load
current. The maximum inductor peak current
can be calculated with Equation (11):
ILP ILOAD
VOUT
V
(1 OUT )
2fSW L
VIN
RDOWN
Figure 6: Adjustable UVLO Using EN Divider
The UVLO threshold can be calculated with
Equation (12) and Equation (13):
INUVRISING (1
RUP
) VEN_RISING
RDOWN
(12)
INUVFALLING (1
RUP
) VEN_FALLING
RDOWN
(13)
Where VEN_RISING = 1.05V, and VEN_FALLING =
0.93V.
External BST Diode
An external BST diode can enhance the
efficiency of the regulator when the duty cycle is
high. A power supply between 2.5V and 5V can
be used to power the external bootstrap diode.
VCC or VOUT is recommended for this power
supply in the circuit (see Figure 7).
VCC
RBST
External BST diode
IN4148
BST
VCC / VOUT
CBST
(11)
L
VOUT
SW
COUT
Figure 7: Optional External Bootstrap Diode to
Enhance Efficiency
The recommended external BST diode is
IN4148, and the recommended BST capacitor
value is 0.1µF to 1μF.
MP4433 Rev. 1.01
1/12/2018
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© 2018 MPS. All Rights Reserved.
23
MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
A resistor in series with the BST capacitor (RBST)
can reduce the SW rising rate and voltage
spikes. This helps enhance EMI performance
and reduce voltage stress at a high VIN. A
higher resistance is better for SW spike
reduction but compromises efficiency. For a
tradeoff between EMI and efficiency, a ≤20Ω
RBST is recommended.
PCB Layout Guidelines(6)
Efficient PCB layout, especially of the input
capacitor placement, is critical for stable
operation. For best results, refer to Figure 8 and
follow the guidelines below. A four-layer layout
is strongly recommended to achieve better
thermal performance.
1.
Place symmetric input capacitors as close
to VIN and GND as possible.
2.
Use a large ground plane to connect
directly to PGND. If the bottom layer is a
ground plane, add vias near PGND.
3.
Ensure that the high-current paths at GND
and VIN have short, direct, and wide traces.
4.
Place the ceramic input capacitor,
especially the small package size (0603)
input bypass capacitor, as close to VIN and
PGND as possible to minimize high
frequency noise.
5.
Keep the connection of the input capacitor
and IN as short and wide as possible.
6.
Place the VCC capacitor as close to VCC
and GND as possible.
7.
Route SW and BST away from sensitive
analog areas, such as FB.
8.
Place the feedback resistors close to the
chip to ensure that the trace connecting to
FB is as short as possible.
9.
Use multiple vias to connect the power
planes to the internal layers.
Top Layer
Inner Layer 1
Inner Layer 2
NOTE:
6) The recommended PCB layout is based on Figure 9.
Bottom Layer
Figure 8: Recommended PCB Layout
MP4433 Rev. 1.01
1/12/2018
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24
MP4433 - 36V, 3A, LOW IQ, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS
U1
VIN
3.3V-36V
2
C1A
10μF
R1
100kΩ
GND
C1B
10μF
VIN
C5
0.1μF
L1
MP4433
5
EN
11
BST
C1C C1D
0.1μF 0.1μF
EN
3, 10
SW
3.3V/3A
10μH
R3
1MΩ
12
R5
100kΩ
VCC
R4
316kΩ
7
PG
14
SS
C3
4.7nF
6
SYNC
GND
15
FB
C4
1μF
PG
C6
5pF
VOUT
C2A C2B
22μF 22μF
SYNC
R6
NS
16
FREQ
R2
169kΩ
1
PHASE
PHASE
8
BIAS
C7
NS
AGND
4, 9
13
PGND
Figure 9: VOUT = 3.3V, FSW = 500kHz
U1
VIN
3.3V-36V
GND
2
C1A
10μF
R1
100kΩ
C1B
10μF
VIN
BST
C1C C1D
0.1μF 0.1μF
5
EN
11
C5
0.1μF
L1
MP4433
EN
SW
3, 10
R3
41.2kΩ
12
R5
100kΩ
PG
VCC
FB
C6
10pF
VOUT
C2A C2B
22μF 22μF
GND
15
C4
1μF
R4
13kΩ
7
PG
SS
14
C3
4.7nF
SYNC
3.3V/3A
10μH
6
SYNC
FREQ
R6
NS
16
R2
169kΩ
1
PHASE
4, 9
PGND
BIAS
AGND
8
C7
NS
13
PHASE
Figure 10: VOUT = 3.3V, FSW = 500kHz for
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