MP2660
2
5V USB, 500mA, I C-Controlled Linear
Charger with Power Path Management
for Single-Cell Li-Ion Battery
DESCRIPTION
FEATURES
The MP2660 is a highly integrated, single-cell,
Li-ion/Li-polymer battery charger with system
power path management for space-limited
portable applications. This device takes input
power from either an AC adapter or a USB port
to supply the system load and charge the
battery independently. The charger section
features constant current pre-charge, constant
current fast charge (CC) and constant voltage
(CV) regulation, charge termination, and autorecharge.
The power path management function ensures
continuous power to the system even with a
dead battery by automatically selecting the
input, the battery, or both to power the system.
This power stage features a low dropout
regulator from the input to the system and a
100mΩ switch from the battery to the system.
Power path management separates the
charging current from the system load, which
allows for proper charge termination and keeps
the battery in full-charge mode.
The MP2660 provides system short-circuit
protection (SCP) by limiting the current from the
input to the system and the battery to the
system. This feature is especially critical for
preventing the Li-ion battery from being
damaged due to excessively high currents. An
on-chip battery under-voltage lockout (UVLO)
cuts off the path between the battery and the
system if the battery voltage drops below the
programmable battery UVLO threshold, which
prevents the Li-ion battery from being overdischarged. An integrated I2C control interface
allows the MP2660 to program the charging
parameters including the input current limit,
input minimum voltage regulation, charging
current, battery regulation voltage, safety timer,
and battery UVLO.
Compatible with 5V USB Power Sources
Fully Autonomous Charger for Single-Cell
Li-Ion/Li-Polymer Batteries
Complete Power Path Management for
Simultaneously Powering the System and
Charging the Battery
Programmable Input Current Limit and Input
Minimum Voltage Regulation Thresholds
±0.5% Charging Voltage Accuracy
13V Maximum Voltage for the Input Source
I2C Interface for Programming Charging
Parameters and Status Reporting
Fully Integrated Power Switches and No
External Blocking Diode Required
Built-In Robust Charging Protection
Including Battery Temperature Monitoring
and Programmable Timer
Built-In Battery Disconnection Function for
Shipping Mode
Thermal Limiting Regulation on the Chip
Available in an Ultra-Compact WLCSP-9
(1.55mmx1.55mm) Package
APPLICATIONS
Wearable Devices
Smart Handheld Devices
Fitness Accessories
Smart Watches
Bluetooth Headphones
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are
trademarks of Monolithic Power Systems, Inc. or its subsidiaries.
The MP2660 is available in a 9-pin WLCSP
(1.55mmx1.55mm) package.
MP2660 Rev. 1.12
10/15/2021
MonolithicPower.com
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1
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
TYPICAL APPLICATION
System Load
IN
SYS
Q1
USB
Port
VDD
Q2
MP2660
INT
BATT
Host
Li-ion
Battery
Pack
SDA
SCL
NTC
GND
IN
Table 1: Operation Mode Table
FET On/Off
Change By
Control
LDO FET
Battery FET
(charging)
Battery FET
(discharging)
I2C Control
EN_HIZ = 1
Enter Hi-Z
Mode
CEB = 1
Charge
Control
FET_DIS = 1
Enter Shipping
Mode
OFF
x
x
x
OFF
OFF
x
x
OFF
x = Don’t Care
MP2660 Rev. 1.12
10/15/2021
MonolithicPower.com
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2
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
ORDERING INFORMATION
Part Number*
MP2660GC-xxxx**
EVKT-MP2660
Package
WLCSP-9 (1.55mmx1.55mm)
Evaluation kit
Top Marking
See Below
* For Tape & Reel, add suffix -Z (e.g. MP2660GC-xxxx-Z)
**“xxxx” is the register setting option. The factory default is “0000”. This content can be viewed in the I2C register
map. Please contact an MPS FAE to obtain an “xxxx” value.
TOP MARKING
DP: Product code of MP2660GC
Y: Year code
LLL: Lot number
EVALUATION KIT EVKT-MP2660
EVKT-MP2660 kit contents (items below can be ordered separately):
#
Part Number
Item
Quantity
1
EV2660-C-01A
MP2660 evaluation board
1
2
EVKT-USBI2C-02-bag
Includes one USB to I2C communication interface,
one USB cable, and one ribbon cable
1
3
Online resources
Include datasheet, user guide, product brief, and GUI
1
Order direct from MonolithicPower.com or our distributors.
Input Power
Supply
Input
GUI
USB Cable
USB to I2C
Communication
Interface
Ribbon Cable
EV2660-C-01A
Battery
Output
Load
EVKT-MP2660 Evaluation Kit Set-Up
MP2660 Rev. 1.12
10/15/2021
MonolithicPower.com
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© 2021 MPS. All Rights Reserved.
3
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
PACKAGE REFERENCE
TOP VIEW
1
2
3
A
IN
SYS
BATT
B
NTC
INT
VDD
C
SDA
SCL
GND
WLCSP-9 (1.55mmx1.55mm)
PIN FUNCTIONS
Pin #
Name
I/O
A1
IN
Power
A2
SYS
Power
A3
BATT
Power
B1
NTC
I
B2
INT
I/O
B3
VDD
Power
C1
C2
C3
SDA
SCL
GND
I/O
I
Power
MP2660 Rev. 1.12
10/15/2021
Description
Input power. Place a ceramic capacitor from IN to GND as close to the IC as
possible.
System power supply. Place a ceramic capacitor from SYS to GND as close to
the IC as possible.
Battery. Place a ceramic capacitor from BATT to GND as close to the IC as
possible.
Temperature sense input. Connect a negative temperature coefficient
thermistor to NTC. Program the hot and cold temperature window with a resistor
divider from IN to NTC to GND. The charge is suspended when NTC is out of the
range.
Interrupt signal. INT sends the charging status and fault interruption to the host.
INT can also disconnect the system from the battery. Pull INT low for >8s to
disconnect the battery from the system. Use a ≥100kΩ external pull-up resistor
for INT.
Internal control power supply. Connect a ceramic capacitor (0.1µF) from VDD
to GND. No external load is allowed.
I2C Interface data. Connect SDA to the logic rail through a 10kΩ resistor.
I2C Interface clock. Connect SCL to the logic rail through a 10kΩ resistor.
Ground.
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4
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
θJA θJC
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance (4)
VIN ................................................ -0.3V to +13V
All other pins to GND .................. -0.3V to +6.0V
Continuous power dissipation (TA = 25°C) (2)
................................................................ 0.88W
Junction temperature ............................... 150°C
Lead temperature (solder) ....................... 260°C
Storage temperature ................ -65°C to +150°C
WLCSP-9 (1.5mmx1.55mm) ... 114 ... 12 ... °C/W
Recommended Operating Conditions (3)
Supply voltage (VIN) ..................... 4.35V to 5.5V
(USB input)
IIN ................................................... up to 455mA
ISYS ..................................................... up to 1.6A
ICHG ................................................ up to 455mA
VBATT .............................................. up to 4.545V
Operating junction temp. (TJ) ... -40°C to +125°C
MP2660 Rev. 1.12
10/15/2021
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX) - TA) / θJA. Exceeding the maximum allowable power
dissipation can produce an excessive die temperature, which
may cause the device to go into thermal shutdown. Internal
thermal shutdown circuitry protects the device from
permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
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5
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
ELECTRICAL CHARACTERISTICS
VIN = 5.0V, VBATT = 3.5V, TA = 25°C, unless otherwise noted.
Parameter
Symbol
Condition
Min
Typ
Max
Units
5.0
13
5.5
V
V
4.5
V
6.15
V
Input Source and Battery Protection
Input voltage range
Input operation voltage
VIN
VIN
BATT input voltage (5)
VBATT
Input over-voltage
protection threshold
Input OVP hysteresis
Input under-voltage lockout
threshold
Input under-voltage lockout
threshold hysteresis
Input vs. battery headroom
threshold
Input vs. battery headroom
threshold hysteresis
Battery under-voltage
lockout threshold
VIN_OVP
4.35
Input rising threshold
5.85
6.00
335
VIN_UVLO
Input rising threshold
3.8
3.9
4.0
180
VHDRM
Input rising vs. battery
90
110
2.6
Battery UVLO range
Programmable using I2C
2.4
Battery under-voltage
lockout threshold hysteresis
VBATT_UVLO = 2.8V
235
Rising, higher than VBATT_REG
120
Falling, higher than VBATT_REG
65
VBATT_UVLO
VBATT_OVP
2.8
V
mV
130
66
BATT voltage falling,
programmable, VBATT_UVLO = 2.8V
Battery over-voltage
protection
mV
mV
mV
3.0
V
3.1
V
mV
mV
Power Path Management
Regulated system output
voltage
Input current limit range
VSYS_REG
Input current limit
IIN_LIM
Input minimum voltage
regulation
VIN_MIN
SYS output voltage
IN to SYS switch on
resistance
MP2660 Rev. 1.12
10/15/2021
VSYS
RON_SYS
VIN = 5.5V, ISYS = 10mA, ICHG = 0A
4.85
I2C programmable
REG00h, bits[2:0] = 000 - 85mA
REG00h, bits[2:0] = 001 - 130mA
REG00h, bits[2:0] = 100 - 265mA
REG00h, bits[2:0] = 111 - 455mA
85
63
102
230
400
I2C programmable range
I2C setting VIN_MIN = 4.20V
Charging mode, VIN = 5.5V,
VBATT = 3.7V
Supplement mode, VBATT = 3.7V,
IBATT = 100mA
VIN < VIN_UVLO and VBATT <
VBATT_UVLO
VIN = 5V, ISYS = 100mA
5.00
5.15
V
mA
70
116
247
428
455
85
130
265
455
3.88
4.10
4.20
5.08
4.30
4.85
5.00
5.15
3.6
mA
V
V
0
300
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400
mΩ
6
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
ELECTRICAL CHARACTERISTICS (continued)
VIN = 5.0V, VBATT = 3.5V, TA = 25°C, unless otherwise noted.
Parameter
Symbol
Input quiescent current
Battery quiescent current
BATT input to SYS switch
on resistance
Battery current regulation in
discharge mode
BATT to SYS switch
leakage
SYS reverse to BATT
switch leakage
Battery discharge function
controlled by INT (5)
IIN_Q
IBATT_Q
RON_BATT
IDSCHG
tINT
Condition
Min
VIN = 5.5V, CEB = 0, charge
enable, ICHG = 0A, ISYS = 0A
Max
Units
610
µA
VIN = 5.5V, CEB = 1, charge
disable
VIN = 5V, CEB = 0, ISYS = 0A,
VBATT = 4.3V
VIN = 0V, CEB = 1, ISYS = 0A,
VBATT = 4.35V
VBATT = 4.5V, VIN = VSYS = GND,
FET_DIS = 1, disconnect mode
VIN < 2V, VBATT = 3.5V,
ISYS = 100mA
Program range
Typ
470
33
11
14
4.512
5.017
100
150
mΩ
1600 (5)
mA
1
µA
1.2
µA
200
VBATT = 4.5V, VIN = VSYS = GND,
disconnect mode
VSYS = 6V, VIN = 4.5V,
VBATT = GND, CEB = 1
INT pull low lasting time to turn off
the battery discharge function
Battery FET lasts for the off time
before auto-on
µA
8
s
500
ms
Battery Charger
Battery voltage regulation
range
Battery voltage regulation
(VBATT_REG = 4.2V)
Battery charge voltage
regulation
Fast charge current
Junction temperature
regulation(5)
Pre-charge current
MP2660 Rev. 1.12
10/15/2021
VBATT_REG
VBATT
VBATT_REG
ICC
TJ_REG
IPRE
Programmable using I2C
3.600
T = 25°C, IBATT = 15mA
4.179
VBATT_REG = 4.2V,
REG04h, bits[7:2] = 101000
VBATT_REG = 4.35V,
REG04h, bits[7:2] = 110010
VIN = 5V, VBATT = 3.8V,
programmable range
VIN = 5V, VBATT = 3.8V,
ICC_SETTING = 76mA
VIN = 5V, VBATT = 3.8V,
ICC_SETTING = 246mA
Junction temperature regulation
REG06h, bits[1:0] = 11 Thermal_limit = 120°C
Program range
IPRE_SETTING = 20mA,
REG03h, bits[1:0] = 10
4.545
V
4.200
4.221
V
4.179
4.200
4.221
4.328
4.350
4.372
V
535 (5)
8
65
76
87
220
245
270
120
6
13.0
16.5
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mA
°C
27
mA
20.0
mA
7
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
ELECTRICAL CHARACTERISTICS (continued)
VIN = 5.0V, VBATT = 3.5V, TA = 25°C, unless otherwise noted.
Parameter
Symbol
Charge termination current
threshold
Pre-charge threshold
voltage
Pre-charge voltage
hysteresis
Recharge threshold below
VBATT_REG
ITERM
VBATT_PRE
Condition
Min
Typ
Max
ICC_SETTING ≤ 263mA, (REG02h,
bit[4] = 0), IPRE_SETTING = 6mA
4.0
6.5
8.5
10.0
13.0
16.5
16
20
24
22
27
31
10.0
13.0
16.5
22
27
32
34
41
48
48.0
56.5
65.0
2.8
3.0
3.1
ICC_SETTING ≤ 263mA, (REG02h,
bit[4] = 0), IPRE_SETTING = 13mA
ICC_SETTING ≤ 263mA, (REG02h,
bit[4] = 0), IPRE_SETTING = 20mA
ICC_SETTING ≤ 263mA, (REG02h,
bit[4] = 0), IPRE_SETTING = 27mA
ICC_SETTING ≥ 280mA, (REG02h,
bit[4] = 1), IPRE_SETTING = 6mA
ICC_SETTING ≥ 280mA, (REG02h,
bit[4] = 1), IPRE_SETTING = 13mA
ICC_SETTING ≥ 280mA, (REG02h,
bit[4] = 1), IPRE_SETTING = 20mA
ICC_SETTING ≥ 280mA, (REG02h,
bit[4] = 1), IPRE_SETTING = 27mA
VBATT rising, set VBATT_PRE = 3.0V
mA
88
VRECH
Units
V
mV
REG04h, bit[0] = 0
130
170
210
REG04h, bit[0] = 1
270
320
370
mV
Thermal Protection
Thermal shutdown rising
TJ_SHDN
threshold (5)
Thermal shutdown
hysteresis (5)
NTC output current
INTC
NTC cold temp rising
VCOLD
threshold
NTC cold temp rising
threshold hysteresis
NTC hot temp falling
VHOT
threshold
NTC hot temp falling
threshold hysteresis
Logic I/O Pin Characteristics (5)
Low logic voltage threshold
VL
High logic voltage
threshold
VH
MP2660 Rev. 1.12
10/15/2021
CEB = 0, VNTC = 3V
As a percentage of VIN
150
°C
20
°C
-100
0
100
nA
64
66
68
%
28
As a percentage of VIN
33
35
mV
37
65
mV
0.4
1.3
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%
V
V
8
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
ELECTRICAL CHARACTERISTICS (continued)
VIN = 5V, TA = 25°C, unless otherwise noted.
Parameter
I2C Interface (SDA, SCL)
Symbol Condition
Min
Typ
Max
1.3
Units
Input high threshold level
VIH
VPULL_UP = 1.8V, SDA and SCL
V
Input low threshold level
VIL
VPULL_UP = 1.8V, SDA and SCL
0.4
V
Output low threshold level
VOL
ISINK = 5mA
0.4
V
I2C clock frequency
FSCL
400
kHz
Digital Clock and Watchdog Timer
Digital clock 2
FDIG2
Watchdog timer
tWDT
Safety timer
tST
32
Programmable (REG05h, bits[5:4]
= 11)
Programmable (REG05h, bits[2:1]
= 00), tST = 3hrs
Programmable (REG05h, bits[2:1]
= 01), tST = 5hrs
Programmable (REG05h, bits[2:1]
= 10), tST = 8hrs
Programmable (REG05h, bits[2:1]
= 11), tST = 12hrs
kHz
140
160
180
2.7
3.0
3.3
4.5
5.0
5.5
7.2
8.0
8.8
10.8
12.0
13.2
s
hrs
Note:
5) Guaranteed by design.
MP2660 Rev. 1.12
10/15/2021
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9
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 5V, TA = 25°C, IIN_LIM = 455mA, ICC = 246mA, VIN_MIN = 4.76V, unless otherwise noted.
Battery Regulation Voltage
vs. Temperature
System Reguation Voltage
vs. Temperature
VBATT_REG=4.2V
4.2
4.15
4.1
5
10
4.98
8
I_BATT_SHIP (μA)
4.25
V_SYS_REG (V)
VBATT_REG (V)
4.3
Battery Current under
Shipping Mode vs.
Temperature
4.96
4.94
4.92
-50
4.9
0
50
100
TEMPERATURE (°C)
Pre-Charge Current
vs. Temperature
6
4
2
-50
0
0
50
100
TEMPERATURE (°C)
Fast Charge Current
vs. Temperature
IPRE=20mA
0
50
100
TEMPERATURE (°C)
Battery Termination
Current vs. Temperature
ICC=246mA
20.0
-50
270.0
30.0
260.0
27.0
ITERM=20mA
IPRE (mA)
18.0
17.0
16.0
15.0
14.0
ITERM (mA)
ICC_DEFAULT (mA)
19.0
250.0
240.0
24.0
21.0
18.0
230.0
13.0
220.0
-50
0
50
100
TEMPERATURE (°C)
120
450.0
118
440.0
116
114
112
110
-50
0
50
100
TEMPERATURE (°C)
MP2660 Rev. 1.12
10/15/2021
-50
IIN_LIM=455mA
5
VIN_MIN=4.76V
4.9
430.0
420.0
4.8
4.7
4.6
410.0
400.0
-50
0
50
100
TEMPERATURE (°C)
Input Regulation Voltage
vs. Temperature
I_Limit_455mA
vs. Temperature
I_LIMIT_455mA (mA)
V_BATT_OVP_R(mV)
Battery OVP Voltage
vs. Temperature
15.0
0
50
100
TEMPERATURE (°C)
VIN_MIN (V)
12.0
-50
4.5
0
50
100
TEMPERATURE (°C)
-50
0
50
100
TEMPERATURE (°C)
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10
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, TA = 25°C, IIN_LIM = 455mA, ICC = 246mA, VIN_MIN = 4.76V, unless otherwise noted.
Battery Charge Curve
Auto-Recharge
Battery Charge Curve
ISYS=0A
ISYS=0A
ISYS=200mA
VIN
1V/div.
VSYS
1V/div.
VIN
1V/div.
VSYS
1V/div.
VBATT
1V/div.
VIN
1V/div.
VSYS
1V/div.
IBATT
100mA /div.
VBATT
1V/div.
IBATT
100mA /div.
2s/div.
1s/div.
CC Charge Steady State
VBATT=3.7V, ISYS=200mA
VIN
1V/div.
VSYS
1V/div.
IBATT
50mA /div.
VBATT
1V/div.
IBATT
100mA /div.
2s/div.
Supplement Mode
Steady State
Input Voltage Regulation
based PPM
VBATT=3.7V, ISYS=600mA
VIN=5V/300mA, VBATT=4.2V,
VIN_MIN=4.84V
VIN
1V/div.
VSYS
1V/div.
VIN
1V/div.
VSYS
1V/div.
IBATT
50mA/div.
VBATT
1V/div.
VBATT
1V/div.
ISYS
100mA/div.
IBATT
50mA /div.
1ms/div.
4s/div.
1ms/div.
Input Voltage Regulation
based PPM
Input Current Limit
based PPM
Input Current Limit
based PPM
VIN=5V/300mA, VBATT=3.7V
VBATT=3.7V
IIN_LIM=175mA
VSYS
1V/div.
VIN
1V/div.
IBATT
100mA/div.
ISYS
100mA/div.
4s/div.
MP2660 Rev. 1.12
10/15/2021
VSYS
1V/div.
VSYS
1V/div.
IIN
100mA/div.
IBATT
200mA/div.
IBATT
100mA/div.
IIN
50mA/div.
ISYS
200mA/div.
ISYS
100mA/div.
4s/div.
4s/div.
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11
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, TA = 25°C, IIN_LIM = 455mA, ICC = 246mA, VIN_MIN = 4.76V, unless otherwise noted.
Power On
Power Off
VBATT=3.7V, ISYS=0A
VBATT=3.7V, ISYS=0A
Power On
@ Supplement Mode
VBATT=3.7V, ISYS=600mA
VIN
1V/div.
VSYS
1V/div.
VIN
1V/div.
VSYS
1V/div.
VBATT
1V/div.
VIN
1V/div.
VSYS
1V/div.
VBATT
1V/div.
VBATT
1V/div.
IBATT
100mA /div.
IBATT
100mA /div.
IBATT
100mA /div.
2ms/div.
100ms/div.
Power Off
@ Supplement Mode
2ms/div.
EN On
@ Input Current Limit
Based PPM
VBATT=3.7V, ISYS=600mA
EN Off
@ Input Current Limit
Based PPM
VBATT=3.7V, ISYS=400mA
VIN
1V/div.
VSYS
1V/div.
IBATT
100mA /div.
VIN
1V/div.
VSYS
1V/div.
IBATT
100mA/div.
VBATT
1V/div.
ISYS
100mA/div.
VBATT
1V/div.
IBATT
100mA /div.
2ms/div.
EN Off
@ Supplement Mode
VBATT=3.7V, ISYS=600mA
VBATT=3.7V, ISYS=600mA
VIN
1V/div.
VSYS
1V/div.
ISYS
200mA/div.
VSYS
1V/div.
MP2660 Rev. 1.12
10/15/2021
VBATT=3.7V, ISYS=0A
VSYS
1V/div.
VBATT
1V/div.
IBATT
100mA/div.
40μs/div.
Charge On
VIN
1V/div.
ISYS
200mA/div.
IBATT
100mA/div.
40μs/div.
400μs/div.
EN On
@ Supplement Mode
VIN
1V/div.
VBATT=3.7V, ISYS=400mA
VIN
1V/div.
VSYS
1V/div.
IBATT
100mA/div.
40μs/div.
400μs/div.
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12
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, TA = 25°C, IIN_LIM = 455mA, ICC = 246mA, VIN_MIN = 4.76V, unless otherwise noted.
Charge Off
Adding Load @
Discharge Mode
VBATT=3.7V, ISYS=0A
Load Transient @
Discharge Mode
VBATT=3.7V
VIN
1V/div.
VSYS
1V/div.
VBATT
1V/div.
VBATT=3.7V, ISYS=0-1A
VSYS
1V/div.
VBATT
1V/div.
IBATT
500mA /div.
VSYS
1V/div.
VBATT
1V/div.
IBATT
500mA /div.
ISYS
500mA/div.
ISYS
500mA/div.
IBATT
100mA /div.
40μs/div.
4s/div.
2ms/div.
BATT Float Operation
BATT Insertion
BATT Removal
ISYS=0A
VBATT=3.7V, ISYS=0A
VBATT=3.7V, ISYS=0A
VIN
1V/div.
VSYS
1V/div.
VBATT
1V/div.
VIN
1V/div.
VSYS
1V/div.
VBATT
1V/div.
IBATT
50mA/div.
VIN
1V/div.
VSYS
1V/div.
VBATT
1V/div.
IBATT
100mA/div.
IBATT
100mA/div.
20ms/div.
40ms/div.
40ms/div.
NTC On/Off
NTC On/Off
VIN OVP Operation
VBATT=3.7V, ISYS=0A
VBATT=3.7V, ISYS=0A
VBATT=3.7V, ISYS=0A
VSYS
1V/div.
VSYS
1V/div.
VBATT
1V/div.
VBATT
1V/div.
VNTC
1V/div.
IBATT
100mA/div.
VNTC
1V/div.
IBATT
100mA/div.
40ms/div.
MP2660 Rev. 1.12
10/15/2021
VIN
1V/div.
VBATT
1V/div.
VSYS
2V/div.
IBATT
100mA/div.
40ms/div.
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2s/div.
13
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
FUNCTIONAL BLOCK DIAGRAM
VIN
Body
Switch
Control
VIN_REF
gm2
VSYS_REF
gm1
IIN_REF
gm3
IN
SYS
Q1
Driver
Loop Compensation
Body
Switch
Control
Driver
LDO
Battery FET
Control
VDD
gm5
VBATT
Q2
ICHG_REF
BATT
gm4
VBATT_REF
6V
VIN
IN
Charge Control
Block
NTC
3.9V
NTC Protection
VBATT+110mV
SCL
DAC
SDA
I2C
Interface
VBATT_REF, IIN_REF,
ICHG_REF
Register and OTP
Bank
INT
Timer
GND
Figure 1: Functional Block Diagram
MP2660 Rev. 1.12
10/15/2021
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14
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
OPERATION
System
2
The MP2660 is an I C-controlled, single-cell, Liion or Li-polymer battery charger with complete
power path management. The full charge
function features constant current pre-charge
(PRE.C), constant current fast-charge (CC) and
constant voltage (CV) regulation, charge
termination, auto-recharge, and a built-in timer.
The power path function allows the input source
to power the system and charge the battery
simultaneously. If the power source cannot
supply enough current to the system load and
to charge the battery, then the charge current
will be reduced until it is necessary for the
battery to supplement system power.
The IC integrates a 300mΩ LDO FET between
IN and SYS and a 100mΩ battery FET between
SYS and BATT.
During charging mode, the on-chip 100mΩ
battery FET works as a full-featured linear
charger with pre-charging, CC and CV charging,
charge termination, auto-recharging, NTC
monitoring, built-in timer control, and thermal
protection. The charge current can be
programmed via the I2C interface. The IC limits
the charge current when the die temperature
exceeds the programmable thermal regulation
threshold (120°C default).
When the input power is not sufficient for
powering the system load, the MP2660 enters
supplement mode by fully turning on the
100mΩ battery FET. When the input is removed,
the 100mΩ battery FET is also fully turned on,
allowing the battery to power up the system.
When the system load is satisfied, the
remaining current is used to charge the battery.
The IC reduces the charging current or uses
power from the battery to satisfy the system
load when its demand is over the input power
capacity or if either the input current or voltage
loops are active.
Figure 2 shows the power path management
structure for the MP2660.
MP2660
or
LDO FET
LDO Rails
Battery
FET
Input
Backlighting
MCU
Battery
Figure 2: Power Path Management Structure
Power Supply
The internal bias circuit of the IC is powered
from the higher voltage of IN or BATT. When IN
or BATT rises above the respective undervoltage lockout (UVLO) threshold, the sleep
comparator, battery depletion comparator, and
the battery FET driver are active. The I2C
interface is ready for communication and all
registers are reset to the default value. The host
can access all registers.
Input OVP and UVLO
The MP2660 has an input over-voltage
protection (OVP) threshold and an input UVLO
threshold. Once the input voltage transitions out
of the normal input voltage range, the Q1 FET
is turned off immediately.
When the input voltage is identified as a good
source, a 200μs immunity timer is active. If the
input power is still sufficient when the 200μs
timer expires, the system starts up. Otherwise,
Q1 remains off (see Figure 3).
VIN OVP
VIN GOOD
VIN
200µs
200µs
VSYS
Figure 3: Input Power Detection Operation
MP2660 Rev. 1.12
10/15/2021
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15
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
CV Charge
Threshold
AutoRecharge
Threshold
Fast Charge
Current
ICHG
VBATT
Fast Charge
Threshold
ITERM
Pre-Charge
Current
PreCharge
CV
Charge
CC Fast
Charge
Charge
Termination
AutoRecharge
Fast Charge
Figure 4: Battery Charge Profile
Power Path Management (PPM)
The IC employs a direct power path structure
with the battery FET decoupling the system from
the battery, which allows for separate control
between the system and the battery. The system
is given the priority to start up even with a deeply
discharged or missed battery. When the input
power is available, even with a depleted battery,
the system voltage is always regulated to
VSYS_REG by the integrated LDO FET.
As shown in Figure 2, the direct power structure
is composed of a frond-end LDO FET between
IN and SYS pin and a battery FET between SYS
and BATT pin.
The input LDO (using an LDO FET) provides
power to the system, which drives the system
load directly and charges the battery through the
battery FET.
For the system voltage control, when the input
voltage is higher than VSYS_REG, the system
voltage is regulated to VSYS_REG. When the input
voltage is lower than VSYS_REG, the LDO FET is
fully on in drop-out with an input current limit.
Battery Charge Profile
The IC provides three main charging phases:
pre-charge,
constant-current
charge,
and
constant-voltage charge (see Figure 4).
MP2660 Rev. 1.12
10/15/2021
1. Phase 1 (constant-current pre-charge): The
IC is able to safely pre-charge the deeply
depleted battery until the battery voltage
reaches the pre-charge to the fast charge
threshold (VBATT_PRE). The pre-charge current
is programmable via REG03h, bits[1:0]. If
VBATT_PRE is not reached before the precharge timer (1hr) expires, the charge cycle is
stopped, and a corresponding timeout fault
signal is asserted.
2. Phase 2 (constant-current fast charge): When
the battery voltage exceeds VBATT_PRE, the IC
enters a constant-current charge (fast charge)
phase. The fast charge current is
programmable via REG02h, bits[4:0].
3. Phase 3 (constant-voltage charge): When the
battery voltage rises to the pre-programmable
charge full voltage (VBATT_REG) set via
REG04h, bits[7:2], the charge mode changes
from CC mode to CV mode, and the charge
current begins to taper off.
The end of charge (EOC) current threshold (ITERM)
value setting is shown in Table 2.
Table 2: ITERM Value Table
REG02h, bit[4]
ITERM Value
0 (ICC_SETTING ≤ 263mA)
100% x IPRE
1 (ICC_SETTING ≥ 280mA)
200% x IPRE
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16
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
Once the charge current reaches the EOC
current threshold (ITERM) and the CV loop is still
dominated, the IC has three possible actions
after a 500µs delay depending on the settings
of EN_TERM (REG05h, bit[6]) and TERM_TMR
(REG05h, bit[0]):
VIN is still in the operating range, the IC begins
another new charging cycle automatically
without the requirement of restarting a charging
cycle manually. The auto-recharge function is
valid only when EN_TERM = 1 and
TERM_TMR = 0.
1. EN_TERM = 1, TERM_TMR = 0, (default
spec): The IC terminates the charge and
changes the charge status to “charge done.”
2. EN_TERM = 1, TERM_TMR = 1: The IC
changes the charge status to “charge done,”
but the charge current continues tapering off
until it reaches 0.
3. EN_TERM = 0, TERM_TMR = x: The
charge status stays at “charge,” but the
charge current continues tapering off until it
reaches 0.
Battery Over-Voltage Protection (OVP)
The IC is designed with a built-in battery overvoltage limit about 120mV higher than VBATT_REG.
When the battery over-voltage event occurs,
the IC suspends the charging immediately and
asserts a fault.
During the charging process, the actual charge
current may be less than the register setting
due to other loop regulations, such as dynamic
power management (DPM) regulation or
thermal regulation. Refer to the Input Currentand Input Voltage-Based Power Management
section for details.
If ITERM is not reached before the safety charge
timer expires (see Safety Timer section), the
charge cycle is ceased and corresponding
timeout fault signal is asserted.
The following conditions can start a new charge
cycle:
The input power is recycled
Battery charging is enabled by the I2C
Auto-recharge kicks in
However, these conditions can stop a charge
cycle:
Thermistor fault at NTC
Safety timer fault
Battery over voltage
Battery FET is forced to turn off
Automatic Recharge
When the battery is fully charged and charging
is terminated, the battery may be discharged
due to the system consumption or a selfdischarge. When the battery voltage is
discharged below the recharge threshold, and
MP2660 Rev. 1.12
10/15/2021
Input Current- and Input Voltage-Based
Power Management
To meet the input source (usually USB)
maximum current limit specification, the IC uses
an input current-based power management by
monitoring the input current continuously. The
total input current limit can be programmable
via the I2C to prevent the input source from
overloading.
If the pre-set input current limit is higher than
the rating of the input source, back-up input
voltage-based power management also works
to prevent the input source from being
overloaded. If either the input current limit or the
input voltage regulation is reached, the Q1 FET
between IN and SYS is regulated so that the
total input power is limited. As a result, the
system voltage drops. Once the system
declines to the minimum value of 4.8V or VIN 160mV, the charge current is reduced to
prevent the system voltage from dropping
further.
The
voltage-based
dynamic
power
management (DPM) regulates the input voltage
to VIN_MIN when the load is over the input power
capacity. VIN_MIN set via the I2C should be at
least 400mV higher than VBATT_REG to ensure the
stable operation of the regulator.
Battery Supplement Mode
The charge current is reduced to keep the input
current or input voltage in regulation when DPM
occurs. If the charge current is at zero and the
input source is still overloaded due to a heavy
system load, the system voltage starts to fall off.
Once the system voltage falls below the battery
voltage, the IC enters battery supplement mode.
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17
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
When the system voltage is 30mV below the
battery voltage, the ideal diode mode is enabled.
The battery FET is regulated to maintain VBATT VSYS at 22.5mV. If the voltage drop of the
battery FET (IDSCHG x RON_BATT) is higher than
22.5mV, the battery FET is fully turned on to
keep the ideal forward voltage. When the
system load decreases and VSYS is higher than
VBATT + 20mV, ideal diode mode is disabled.
reduces the charge current to prevent higher
power dissipation. The multiple thermal
regulation thresholds from 60°C to 120°C help
the system design meet the thermal
requirement in different applications. The
junction temperature regulation threshold can
be set via REG06h, bits[1:0]. When the junction
temperature reaches 150°C, both Q1 and Q2
are turned off.
Figure 5 shows the dynamic power
management and battery supplement mode
operation profile.
Negative Temperature Coefficient (NTC)
Temperature Sensor
NTC allows the IC to sense the battery
temperature using the thermistor usually
available in the battery pack to ensure a safe
operating environment of the chip. A resistor
with an appropriate value should be connected
from IN to NTC, and the thermistor should be
connected from NTC to ground. The voltage on
NTC is determined by the resistor divider,
whose divide ratio depends on the battery
temperature. The IC sets a pre-determined
upper and lower bound of the divide ratio
internally for NTC cold and NTC hot.
When VIN is not available, the IC operates in
discharge mode, and the battery FET is always
fully on to reduce loss.
ISYS
IIN
VSYS
Min (4.8V, VIN -160mV)
VBATT
22.5mV
30mV
ICHG
0
IDSCHG* RON_BATT
IDSCHG
Figure 5: Dynamic Power Management and
Battery Supplement Operation Profile
Battery Charge Full Voltage
The battery voltage for the constant voltage
regulation phase is VBATT_REG. When VBATT_REG is
4.2V, it has a ±0.5% accuracy over the ambient
temperature range of 0°C to +50°C. When the
battery is removed, the BATT voltage is
between VBATT_REG - VRECH and VBATT_REG.
Thermal Regulation and Thermal Shutdown
The IC monitors the internal junction
temperature continuously to maximize power
delivery and prevent the chip from overheating.
When the internal junction temperature reaches
the pre-set limit of TJ_REG (default 120°C), the IC
MP2660 Rev. 1.12
10/15/2021
The NTC function works in charge mode only.
Once the NTC voltage falls out of the divide
ratio (the temperature is outside the safe
operating range), the IC stops the charging and
reports it on the status bits. Charging resumes
automatically after the temperature falls back
into the safe range.
Safety Timer
The IC provides both a pre-charge and a fastcharge safety timer to prevent extended
charging cycles due to abnormal battery
conditions. If the battery voltage drops below
VBATT_PRE, then the safety timer is one hour. The
fast-charge safety timer begins once the battery
enters fast-charge mode. Figure 4 on page 16
shows the fast-charge timer’s battery profile.
The fast-charge safety timer can be
programmed via the I2C. The safety timer
feature can also be disabled via the I2C.
The following actions can restart the safety
timer:
A new charge cycle is initiated
Charge enable toggling
Hi-Z disable toggling
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18
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
During power path management (PPM), the
charge current is reduced due to an insufficient
input power (input current limit, input voltage
limit). The timer period can be extended 2 times
by setting TMR2X_EN (REG06h, bit[6]) to 1.
TMR2X_EN = 1: 2x extended safety timer
enabled during PPM
TMR2X_EN = 0 (default): 2x extended
safety timer disabled during PPM
This feature avoids a false trigger indication for
a bad battery that delivers a small charge
current to the battery as a result of the
insufficient input power.
Host Mode and Default Mode
The IC is a host-controlled device. After the
power-on reset, the IC starts up in the
watchdog timer expiration state or default mode.
All registers are in the default settings.
Any write to the IC switches it into host mode.
All charge parameters are programmable. If the
watchdog timer (REG05h, bits[5:4]) is not
disabled, the host must reset the watchdog
timer regularly by writing 1 to REG01h, bit[6]
before the watchdog timer expires to keep the
device in host mode. Once the watchdog timer
expires, the IC returns to default mode. The
watchdog timer limit can also be programmed
or disabled by the host control. When there is
no VIN, the watchdog timer is suspended.
The operation can also be changed to default
mode when one of the following conditions
occur:
Refresh input without battery
Re-insert battery with no VIN
Register reset REG01h, bit[7] is reset
Battery Discharge Function
If the battery is connected and the input source
is missing, the battery FET is fully on when
VBATT is above the VBATT_UVLO threshold. The
100mΩ battery FET minimizes conduction loss
during discharge. The quiescent current of the
IC is as low as 11μA in this mode. The low on
resistance and low quiescent current help
extend the running time of the battery.
MP2660 Rev. 1.12
10/15/2021
Over-Discharge Current Protection
The IC has an over-discharge current protection
in discharge mode and supplement mode.
Once IBATT exceeds the programmable
discharge current limit (default 1.0A), the
battery FET is regulated to limit the discharge
current.
Similarly, when the battery voltage falls below
the programmable VBATT_UVLO threshold (default
2.8V), the battery FET is turned off to prevent
over-discharge.
System Short-Circuit Protection (SCP)
The MP2660 features SYS node short-circuit
protection (SCP) for both the IN to SYS path
and the BATT to SYS path.
The system voltage is monitored continuously.
Once VSYS is lower than 1.5V, the over-current
protection threshold for the BATT to SYS path
is limited to 2A (fast off). For details, please
refer to the flow chart in Figure 19.
If the system short-circuit occurs when both the
input and the battery are present, the protection
mechanism of both paths work, with the faster
one (the IN_to_SYS path protection mechanism)
dominating the hiccup operation.
Interrupt to Host (INT)
The IC also has an alert mechanism, which can
output an interrupt signal via INT pin to
notifyces the system ofn the operation by
outputting a 256μs low-state INT pulse. Any of
the below events can will trigger the INT output:
Good input source detected(PG_STAT)
Charge completed
Charging status change
Any fault in REG08h (watchdog timer fault,
input fault, thermal fault, safety timer fault,
battery OVP fault)
When any fault occurs, the IC sends out an INT
pulse and latches the fault state in REG08h.
After the IC exits the fault state, the fault bit can
be released to 0 after the host reads REG08h.
Note that the INT needs the external pull up
resistor for its open-drain connection. Suggest
the resistance not lower than 100kΩ.
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19
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
Battery Disconnection Function
In applications where the battery is not
removable, it is essential to disconnect the
battery from the system to shipping mode, in
stock mode, or to system reset mode for
different applications (shown in Table3).
1. Shipping Mode:
Entering shipping mode: The register bit
FET_DIS (REG06h, bit[5]), makes the IC
enter shipping mode. During normal
operation, the battery FET is turned on (the
bit is 0). If this bit is set to 1 through the I2C,
the battery FET is turned off, and the
MP2660 enters shipping mode.
The FET_DIS bit is reset to 0 automatically
after the battery FET is turned on.
Exiting shipping mode: The IC can exit
shipping mode by pulling INT down for a
very short time (>500ms).
2. Reset Mode:
The IC can use INT to cut off the path from
the battery to the system under the
condition needed to reset the system
manually.
If the battery FET is on, once the logic at
INT is set to low for more than 8s, the
battery is disconnected from the system by
turning off the battery FET. The battery can
be connected in and out of the system by
controlling INT (see Figure 6).
0.5s
INT
8s
Table 3: Battery Disconnection Control
FET On/Off
Change By
Control
LDO FET
Battery FET
(charging)
Battery FET
(discharging)
INT Pin
H to L for 8s H to L for 500ms
Exit Shipping
Reset Mode
Mode
x
x
OFF
ON
OFF
ON
I2C Interface
The MP2660’s I2C interface allows a user to
flexibly configure the charging parameters. It
also provides instant device status reporting.
The I2C is a 2-wire serial interface with two bus
lines: a serial data line (SDA) and a serial clock
line (SCL). Both the SDA and SCL lines are
open drains. Do not connect the SDA and SCL
lines to the positive supply voltage via a pull-up
resistor.
The IC operates as a slave device, receiving
control inputs from the master device (e.g. a
microcontroller). The SCL line is driven by the
master device. The I2C interface supports both
standard mode (up to 100kbit/s) and fast mode
(up to 400kbit/s).
All transactions begin with a start (S) condition
and are terminated by a stop (P) condition.
Start and stop conditions are generated by the
master. A start condition is defined as a high to
low transition on the SDA line while the SCL
line is high. A stop condition is defined as a low
to high transition on the SDA line while the SCL
line is high.
SDA
Battery FET Gate
Shipping
Mode
Figure 6: Disconnection Function Operation
Profile
SCL
Start (S)
Stop (P)
Figure 7: Start (S) and Stop (P) Conditions
MP2660 Rev. 1.12
10/15/2021
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20
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
releasing the SDA line during the ACK clock
pulse, so that the SDA line can be pulled low by
the receiver and remain low during the high
period of the 9th clock.
SDA
SCL
The not acknowledge (NACK) signal is defined
as the SDA line remaining high during the 9th
clock. Then the master generates either a stop
(P) to abort the transfer or a repeated start (S)
to start a new transfer.
Data
Change
Allowed
Data Line
Stable,
Data Valid
After the start signal, a slave address is sent.
This address is 7-bits long, and is followed by
an 8th bit as a data direction bit (R/W). A 0
indicates a write (W) signal transmission, while
a 1 indicates a read (R) signal data request.
Figure 9 shows the address bit arrangement.
Figure 8: I2C Bus Bit Transfer
For data validity, the SDA line data should
remain stable during the high period of the
clock. The SDA line’s high/low state can
change while the SCL line’s clock signal is low.
Each byte on the SDA line should be 8 bits long.
The number of bytes transmitted per transfer is
unrestricted. Data is transferred with the most
significant bit (MSB).
LSB
MSB
R/W
Each byte is followed by an acknowledge (ACK)
bit generated by the receiver to signal to the
transmitter that the byte was successfully
received.
Slave Address
Figure 9: 7-Bit Addressing
See Figures 10–14 for more details on the R/W
signal sequences.
The ACK signal is defined as the transmitter
Acknowledgement
Signal from Receiver
Acknowledgement
Signal from Slave
SDA
MSB
SCL
1
Start
or
Repeated
Start
7
2
9
8
1
2
8
9
ACK
Stop
or
Repeated
Start
ACK
Figure 10: I2C Bus Data Transfer
1
7
1
1
8
1
8
1
1
S
Slave Address
0
ACK
Reg Address
ACK
Data Address
ACK
P
Figure 11: Single Write
1
7
1
1
8
1
1
7
1
1
8
S
Slave Address
0
ACK
Reg Address
ACK
S
Slave Address
1
ACK
Data
1
1
NACK P
Figure 12: Single Read
MP2660 Rev. 1.12
10/15/2021
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MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
1
S
7
Slave Address
1
1
8
1
0
ACK
Reg Address
ACK
8
Data to Addr
1
8
1
ACK
Data to Addr+1
ACK
8
Data to Addr+n
1
1
ACK
P
Figure 13: Multi-Write
1
S
7
Slave Address
1
1
8
1
1
7
1
1
0
ACK
Reg Address
ACK
S
Slave Address
1
ACK
8
1
8
1
8
1
1
Data @ Address
ACK
Data @ Addr+1
ACK
Data @ Addr+n
NACK
P
Figure 14: Multi-Read
MP2660 Rev. 1.12
10/15/2021
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22
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
I2C REGISTER MAP
IC Address: 09h
Input Source Control Register/Address: 00h (Default: 0100 1111)
Bit
Symbol
Description
Read/Write
Default
Bit 7
EN_HIZ (6)
0: Disable
1: Enable
Read/Write
Disable (0)
Read/Write
Offset: 3.88V
Range: 3.88V 5.08V
Default: 4.60V
(1001)
Read/Write
455mA (111)
Input Voltage Regulation
Bit 6
VIN_MIN [3]
640mV
Bit 5
VIN_MIN [2]
320mV
Bit 4
VIN_MIN [1]
160mV
Bit 3
VIN_MIN [0]
80mV
Input Current Limit
Bit 2
IIN_LIM [2]
Bit 1
IIN_LIM [1]
Bit 0
IIN_LIM [0]
000: 85mA
001: 130mA
010: 175mA
011: 220mA
100: 265mA
101: 310mA
110: 355mA
111: 455mA
Note:
6) This bit only controls the on and off of the LDO FET.
Power-On Configuration Register / Address: 01h (Default: 0000 0100)
Bit
Symbol
Description
Read/Write
Default
Bit 7
Register reset
0: Keep current setting
1: Reset
Read/Write
Keep current
register setting (0)
Bit 6
I2C watchdog timer
reset
0: Normal
1: Reset
Read/Write
Normal (0)
Reserved
Reserved
NA
NA
Bit 5
Reserved
Bit 4
Reserved
Charger Configuration
Bit 3
CEB
0: Charge enable
1: Charge disable
Battery UVLO Threshold
Bit 2
VBATT_UVLO [2]
0.4V
Bit 1
VBATT_UVLO [1]
0.2V
Bit 0
VBATT_UVLO [0]
0.1V
MP2660 Rev. 1.12
10/15/2021
Read/Write
Charge enable(0)
Read/Write
Offset: 2.4V
Range: 2.4V - 3.1V
Default: 2.8V (100)
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MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
I2C REGISTER MAP (continued)
Charge Current Control Register/ Address: 02h (Default: 0000 1110)
Bit
Symbol
Description
Read/Write
Bit 7
Reserved
Reserved
NA
Bit 6
Reserved
Reserved
NA
Bit 5
Reserved
Reserved
NA
Default
Charge Current Setting
Bit 4
ICC [4]
272mA
Bit 3
ICC [3]
136mA
Bit 2
ICC [2]
68mA
Bit 1
ICC [1]
34mA
Bit 0
ICC [0]
17mA
Read/Write
Offset: 8mA
Range: 8mA 535mA
Default: 246mA
(01110)
Pre-Charge/ Termination Current/ Address: 03h (Default: 0100 1010)
Bit
Symbol
Description
Bit 7
Reserved
Reserved
Read/Write
Default
NA
BATT to SYS Discharge Current Limit
Bit 6
IDSCHG[3]
800mA
Bit 5
IDSCHG [2]
400mA
Bit 4
IDSCHG [1]
200mA
Bit 3
IDSCHG [0]
100mA
Bit 2
Reserved
Reserved
Read/Write
Offset: 200mA
Range: 200mA 1.6A
Default: 1.0A
(1001)
NA
Pre-Charge / Terminal Current
Bit 1
IPRE [1]
14mA
Read/Write
Bit 0
IPRE [0]
MP2660 Rev. 1.12
10/15/2021
7mA
Offset: 6mA
Range: 6mA 27mA
Default: 20mA (10)
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24
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
I2C REGISTER MAP (continued)
Charge Voltage Control Register/ Address: 04h (Default: 1010 0011)
Bit
Symbol
Description
Read/Write
Default
Read/Write
Offset: 3.60V
Range: 3.60V 4.545V
Default: 4.2V
(101000)
Read/Write
3.0V (1)
Read/Write
300mV (1)
Battery Regulation Voltage
Bit 7
VBATT_REG [5]
480mV
Bit 6
VBATT_REG [4]
240mV
Bit 5
VBATT_REG [3]
120mV
Bit 4
VBATT_REG [2]
60mV
Bit 3
VBATT_REG [1]
30mV
Bit 2
VBATT_REG [0]
15mV
Pre-Charge Threshold
Bit 1
VBATT_PRE
0: 2.8V
1: 3.0V
Battery Recharge Threshold (below VBATT_REG)
Bit 0
VRECH
0: 150mV
1: 300mV
Charge Termination/Timer Control Register / Address: 05h (Default: 0100 1010)
Bit
Symbol
Description
Bit 7
Reserved
Reserved
Read/Write
Default
NA
Termination Setting (control of the termination is allowed or not)
Bit 6
EN_TERM
0: Disable
1: Enable
Read/Write
Enable (1)
00: Disable timer
01: 40s
10: 80s
11: 160s
Read/Write
Disable timer (00)
0: Disable
1: Enable
Read/Write
Enable timer (1)
Read/Write
5hrs (01)
I2C Watchdog Timer Limit
Bit 5
WATCHDOG [1]
Bit 4
WATCHDOG [0]
Safety Timer Setting
Bit 3
EN_TIMER
Safety Timer for Fast Charging Cycle
Bit 2
CHG_TMR [1]
Bit 1
CHG_TMR [0]
00: 3hrs
01: 5hrs
10: 8hrs
11: 12hrs
Termination Timer Control (when TERM_TMR is enabled, the IC will not suspend the charge current
after charge termination)
Bit 0
TERM_TMR
MP2660 Rev. 1.12
10/15/2021
0: Disable
1: Enable
Read/Write
Disable (0)
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MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
I2C REGISTER MAP (continued)
Miscellaneous Operation Control Register/ Address: 06h (Default: 0000 1011)
Bit
Symbol
Description
Read/Write
Default
Bit 7
Reserved
Reserved
Bit 6
TMR2X_EN
0: Disable 2X extended safety timer
during PPM
1: Enable 2X extended safety timer
during PPM
Read/Write
Disable (0)
Bit 5
FET_DIS (7)
0: Enable
1: Turn off
Read/Write
Enable (0)
Bit 4
Reserved
Reserved
NA
Bit 3
EN_NTC
0: Disable
1: Enable
Read/Write
Bit 2
Reserved
Reserved
NA
00: 60°C
01: 80°C
10: 100°C
11: 120°C
Read/Write
NA
Enable (1)
Thermal Regulation Threshold
Bit 1
Bit 0
TJ_REG [1]
TJ_REG [0]
120°C (11)
Note:
7)
This bit only controls the turn off function of the battery FET, including charge and discharge.
System Status Register/ Address: 07h (Default: 0000 0000)
Bit
Symbol
Description
Bit 7
Reserved
Reserved
Read/Write
Default
NA
Revision
Bit 6
Rev [1]
Bit 5
Rev [0]
Bit 4
CHG_STAT [1]
Bit 3
CHG_STAT [0]
Revision number
Read only
(00)
00: Not charging
01: Pre-charge
10: Charge
11: Charge done
Read only
Not charging (00)
Read only
No PPM (0)
(no power-path
management
happens)
Bit 2
PPM_STAT
0: No PPM
1: In PPM
Bit 1
PG_STAT
0: Power fail
1: Power good
Read only
Power fail (0)
Bit 0
THERM_STAT
0: No thermal regulation
1: In thermal regulation
Read only
No thermal
regulation (0)
MP2660 Rev. 1.12
10/15/2021
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26
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
I2C REGISTER MAP (continued)
Fault Register/ Address: 08h (Default: 0000 0000)
Bit
Symbol
Description
Bit 7
Reserved
Reserved
Bit 6
WATCHDOG_
FAULT
0: Normal
1: Watchdog timer expiration
Read only
Normal (0)
Bit 5
VIN_FAULT
0: Normal
1: Input fault (OVP or bad source)
Read only
Normal (0)
Bit 4
THEM_SD
0: Normal
1: Thermal shutdown
Read only
Normal (0)
Bit 3
BAT_FAULT
0: Normal
1: Battery OVP
Read only
Normal (0)
Bit 2
STMR_FAULT
0: Normal
1: Safety timer expiration
Read only
Normal (0)
Bit 1
Reserved
Reserved
NA
Bit 0
Reserved
Reserved
NA
MP2660 Rev. 1.12
10/15/2021
Read/Write
Default
NA
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MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
ONE TIME PROGRAMMING MAP
#
0x02
Bit7
0x03
0x04
0x05
Bit6
N/A
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ICC: 8mA-535mA / 17mA step
IPRE: 6mA-27mA / 7mA
N/A
step
VBATT_REG: 3.60V-4.545V / 15mV step
N/A
N/A
WATCHDOG
N/A
ONE TIME PROGRAMMING DEFAULT
One Time Programmable Items
ICC
IPRE
VBATT_REG
WATCHDOG
MP2660 Rev. 1.12
10/15/2021
Default
246mA
20mA
4.2V
Disable Timer
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28
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
STATE CONVERSION CHART
Battery Discharge
Mode
Only Power System
Mode
Battery FET Off
Battery FET On
IN Plug-in
and HIZ Quit IN Plug-out
or HIZ Entry
Shipping Mode
IN Plug-out
or HIZ Entry
Battery FET Off
or Disable Charge
Battery FET On
and Enable Charge
IN Plug-in
and HIZ Quit
PSYS < PIN
Battery Supplement
Mode
Battery Charge Mode
PSYS > PIN
Figure 15: State Machine Conversion
MP2660 Rev. 1.12
10/15/2021
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29
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
CONTROL FLOW CHART
POR
No
VIN>VIN_UVLO or
VBATT>VBATT_UVLO?
Yes
Sleep Comparator Active,
Battery FET Driver Starts Up
I2C Write?
Yes
No
Default Mode:
Host Mode:
Registers Set as Default
Host Programs Registers
Yes
I2C Watchdog
Timer Disabled
Yes
No
I2C Watchdog Timer
Reset (8)
I2C Watchdog
Timer Reset
No
No
Watchdog Timer
Expired?
Yes
Figure 16: Default Mode and Host Mode Selection (9)
Notes:
8) Once the watchdog timer expires, the I2C watchdog timer reset is required, or the watchdog timer is not valid in the next cycle.
9) The watchdog timer is held when VIN is not present.
MP2660 Rev. 1.12
10/15/2021
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30
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
CONTROL FLOW CHART (continued)
POR
No
VDD is Powered by Max (VIN, VBATT)
VDD > 2V?
Yes
I2C is Ready
Hi-Z Mode?
Yes
Hi-Z Mode, SYS is
Supplied by VBATT
No
EN BG
Not good VIN,
Q1 is Off
No
All Happen?
VIN_OVP > VIN > VIN_UVLO
VIN > VBATT + VHDRM
Yes
Good VIN, Q1 is
On and
Regulated
No
ENCHG?
Yes
Charge Fault
Yes
Any Fault?
No
ENCHG
Regulates Q2
Figure 17: Input Power Start-Up Flow Chart
MP2660 Rev. 1.12
10/15/2021
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31
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
CONTROL FLOW CHART (continued)
ENCHG
Charge
Mode?
VBATT > VBATT_REG
VBATT < VBATT_PRE
VBATT_PRE < VBATT < VBATT_REG
C.V.C
C.C.C
PRE.C
No
No
No
ICHG < ITERM
Battery Full
VBATT >
VBATT_REG
VBATT >
VBATT_PRE
Yes
Yes
Yes
Charge
Complete
Yes
No
VBATT < VRECH ?
Normal Charge
Timer
Out?
No
No
No
NTC
Fault?
TJ TJ_REG?
Yes
Yes
Yes
Charge Suspended
Charge Suspended
Decrease ICHG to
Maintain TJ at TJ_REG
No
No
Reset
Timer?
NTC OK?
Yes
Yes
Others
TJ = ?
< TJ_REG
Charger Recovery,
Return to Normal
Operation
150 oC
Others
Thermal Shutdown
130oC
< TJ_REG
TJ = ?
Fault Protection
Figure 18: Charging Process
MP2660 Rev. 1.12
10/15/2021
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32
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
CONTROL FLOW CHART (continued)
Battery
Supplement
SYS Reguation
No
No
VSYS < 1.5V?
VSYS < 1.5V?
Yes
Yes
No
No
IIN > 750mA (Fast Off)
Fixed Current Limit
IBATT > 2A (Fast Off)
Fixed Current Limit
No
No
IIN > IIN_LIM?
IBATT > IDSCHG?
Yes
Yes
Yes
Regulate IIN at IIN_LIM
Start 60μs Timer
Yes
Regulate IBATT at IDSCHG
Start 60μs Timer
No
No
60μs Expires?
60μs Expires?
Yes
Yes
Turn Off Q1 and Q2
Start 800μs Timer
Turn Off Q1 and Q2
Start 800μs Timer
No
No
800μs Expired?
800μs Expires?
Yes
Yes
Turn On Q1 and Q2
Turn On Q1 and Q2
Figure 19: System Short-Circuit Protection
MP2660 Rev. 1.12
10/15/2021
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33
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
APPLICATION INFORMATION
Selecting a Resistor for the NTC Sensor
Figure 20 shows an internal resistor divider
reference circuit to limit the low temperature
threshold and high temperature threshold at
VHOT and VCOLD, respectively.
IN
Low-Temp Threshold
VCOLD
RT1
NTC
RNTC
RT2
Hot-Temp Threshold
VHOT
Figure 20: NTC Function Block
For a given NTC thermistor, set the NTC
window by selecting appropriate RT1 and RT2
values with Equation (1) and Equation (2):
R T2 // RNTC_Cold
R T1 R T2 // RNTC_Cold
R T2 // RNTC_Hot
R T1 R T2 // RNTC_Hot
VCOLD
(1)
VHOT
(2)
Where RNTC_Hot is the value of the NTC resistor
at the high end of the required temperature
operation range, and RNTC_Cold is NTC resistor
value at a low temperature. The two resistors
(RT1 and RT2) allow the high temperature limit
and low temperature limit to be programmed
independently. With this feature, the MP2660
can fit most NTC resistor types and different
temperature operation range requirements.
The RT1 and RT2 values depend on the type of
NTC resistor used. For example, for the
thermistor NCP18XH103, RNTC_Cold is 27.219kΩ
at 0°C, and RNTC_Hot is 4.161kΩ at 50°C.
Equation (1) and Equation (2) can be used to
calculate RT1 = 6.59kΩ and RT2 = 24.15kΩ,
assuming that the NTC window is between 0°C
and 50°C and using the VCOLD and VHOT values
from the EC table.
MP2660 Rev. 1.12
10/15/2021
Selecting the External Capacitor
Like most low-dropout regulators, the MP2660
requires external capacitors for regulator
stability and voltage spike immunity. The device
is designed specifically for portable applications
requiring minimum board space and small
components. These capacitors must be
selected correctly for optimal performance.
An input capacitor is required for stability. A
capacitor of at least 1µF must be connected
between IN to GND for stable operation over
the entire load current range. There can be
more output capacitance than input as long as
the input is at least 1µF.
The IC is designed specifically to work with a
very small ceramic output capacitor (typically
2.2µF). A ceramic capacitor with X5R or X7R
type dielectrics at least 2.2µF is suitable in the
MP2660 application circuit. For the MP2660,
the output capacitor should be connected
between SYS and GND with thick traces and
small loop area.
A capacitor from BATT to GND is also
necessary for the MP2660, and the typical
capacitance value is 10µF. A ceramic capacitor
with X5R or X7R type dielectrics at least 10µF
is suitable for the application circuit.
A capacitor between VDD and GND is used to
stabilize the VDD voltage to power the internal
control and logic circuit. The typical value of this
capacitor is 100nF.
PCB Layout Guidelines
Efficient PCB layout is critical for stable
operation. For best results, follow the guidelines
below.
1. Place the external capacitors as close to the
IC as possible to ensure the smallest input
inductance and the ground impedance.
2. Place the PCB trace connecting the
capacitor between VDD and GND very
close to the IC.
3. Keep the signal GND for the I2C wire clean
and away from power GND.
4. Route the I2C wires (SDA, SCL) parallel
with each other.
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34
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
TYPICAL APPLICATION CIRCUIT
5V
A1
C1
1µF
RT1
10kΩ
RT2
10kΩ
B1
SYS
IN
NTC
B3
VDD
C4
100nF
MP2660
INT
Host
C2
2.2µF
B2
GND
VDD
A3
SDA
C2
SYS
INT
R3
100kΩ
BATT
C1
A2
C3
BATT
C3
10µF
SCL
Figure 21: MP2660 Typical Application Circuit with 5V Input
Table 4: The Key BOM of Figure 21
MP2660 Rev. 1.12
10/15/2021
Qty
Ref
Value
1
C1
1µF
1
C2
2.2µF
1
C3
10µF
1
C4
100nF
2
RT1, RT2
10kΩ
Description
Ceramic Capacitor; 16V;
X5R or X7R
Ceramic Capacitor; 16V;
X5R or X7R
Ceramic Capacitor; 16V;
X5R or X7R
Ceramic Capacitor; 16V;
X5R or X7R
Film Resistor;1%
Package
Manufacture
0603
Any
0603
Any
0603
Any
0603
Any
0603
Any
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35
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
PACKAGE OUTLINE DRAWING FOR 9L WLCSP (1.55X1.55MM)
PACKAGE INFORMATIONMF-PO-D-0066 revision 2.0
WLCSP-9 (1.55mmx1.55mm)
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
BOTTOM VIEW
TOP VIEW
SIDE VIEW
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) BALL COPLANARITY SHALL BE 0.05
MILLIMETER MAX.
3) JEDEC REFERENCE IS MO-211, VARIATION BC.
4) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
MP2660 Rev. 1.12
10/15/2021
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36
MP2660 – 0.5A, 1-CELL CHARGER W/ I2C CONTROL, POWER PATH
REVISION HISTORY
Revision #
1.1
1.12
Revision Date
4/29/2021
10/15/2021
Description
Updated the footnote below the Applications section
Updated the INT pin description
Updated “CE = L” to “CEB = 0”; updated “CE = H” to “CEB = 1”
Updated the conditions for the Typical Performance
Characteristics section
Updated the Safety Timer section
Added the I2C Interface section
Updated the conditions and symbols in Figure 17, Figure 18,
and Figure 19 in the Control Flow Chart section
Updated “ITC” to “IPRE”; updated “IBF” to “ITERM”; updated “VIN_REG”
to “VIN_MIN”; grammar and formatting updates
grammar corrections
Pages
Updated
4
6–8
10–13
18–19
20–22
31–33
All
All
Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP2660 Rev. 1.12
10/15/2021
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