MP28167-A
2.8V to 22V VIN, 3A IOUT, 4-Switch,
Integrated Buck-Boost Converter
with FB Pin
DESCRIPTION
FEATURES
The MP28167-A is a synchronous, four-switch,
integrated buck-boost converter capable of
regulating the output voltage across a wide 2.8V
to 22V input voltage range with high efficiency.
The integrated output voltage scaling and
adjustable output current limit functions meet
USB power delivery (PD) requirements.
The MP28167-A uses constant-on-time (COT)
control in buck mode and constant-off-time
control in boost mode, providing fast load
transient response and smooth buck-boost
mode transient. The MP28167-A provides autoPFM/PWM or forced PWM switching modes. It
also provides configurable output constant
current (CC) current limit, which supports flexible
design for different applications.
Full protection features include over-current
protection (OCP), over-voltage protection
(OVP),
under-voltage
protection
(UVP),
configurable soft start, and thermal shutdown.
The MP28167-A is available in a QFN-16
(3mmx3mm) package.
Configurable Output Voltage via FB Pin
Wide 2.8V to 22V Operating Input Voltage
Range
0.08V to 1.637V Reference Voltage Range
with 0.8mV Resolution through I2C (1)
(Default 1V Reference Voltage)
3A Output Current or 4A Input Current
Four Low RDS(ON) Internal Buck Power
MOSFETs
Adjustable Accurate CC Output Current
Limit with Internal Sensing MOSFET via I2C
500kHz/750kHz Selectable Switching
Frequency
Output Over-Voltage Protection (OVP) with
Hiccup
Output Short-Circuit Protection (SCP) with
Hiccup
Over-Temperature Warning and Shutdown
I2C Interface with ALT Pin
One-Time Programmable (OTP) NonVolatile Memory
I2C-Configurable Line Drop Compensation,
PFM/PWM Mode, Soft Start, OCP, and
OVP
Configurable EN Shutdown Discharge
Available in a QFN-16 (3mmx3mm)
Package
The MPL-AL Inductor Series Matches the
Best Performance
APPLICATIONS
USB PD Sourcing Ports
Buck-Boost Bus Supplies
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality Assurance. “MPS”,
the MPS logo, and “Simple, Easy Solutions” are registered trademarks of
Monolithic Power Systems, Inc. or its subsidiaries.
Note:
1) For applications where VOUT is below 3V, the switching
frequency decreases.
MP28167-A Rev. 1.0
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1
MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
TYPICAL APPLICATION
Efficiency vs. Output Current
C4
100nF
L1
IN
C1
100µF
C1A
22µF
BST2
C5
VOUT
5V
OUT
EN
MP28167-A
Rt
806kΩ
ALT
SCL I2C slave
SDA
AGND
R1
430kΩ
FB
R2
107kΩ
VCC
C3
1µF
95
100nF
SW2
R3
499kΩ
C7
22nF
100
4.7µH
SW1
BST1
GND
R5
21.5kΩ
OC
Cout
22µFx5
EFFICIENCY (%)
VIN
12V
+
VIN = 12V, VOUT = 5V to 20V, L = 4.7µH,
fSW = 500kHz, RDC = 16.5mΩ,
forced PWM mode
90
85
80
75
70
65
C6
22nF
60
0.01
Vout=12V
Vout=5V
Vout=9V
Vout=15V
Vout=20V
0.1
1
OUTPUT CURRENT (A)
MP28167-A Rev. 1.0
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2
MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
ORDERING INFORMATION
Part Number*
MP28167GQ-A
EVKT-MP28167-A
Package
QFN-16 (3mmx3mm)
Evaluation kit
Top Marking
MSL Rating
See below
1
* For Tape & Reel, add suffix –Z (e.g. MP28167GQ-A–Z).
TOP MARKING
BKN: Product code of MP28167GQ-A
Y: Year code
LLL: Lot number
EVALUATION KIT EVKT-MP28167-A
EVKT-MP28167-A kit contents (items below can be ordered separately, and the GUI installation file and
supplemental documents can be downloaded from the MPS website):
#
Part Number
Item
Quantity
1
EV28167-A-Q-00A
2
EVKT-USBI2C-02
MP28167-A evaluation board
Includes one USB to I2C communication interface, one
USB cable, and one ribbon cable
1
1
Order directly from MonolithicPower.com or our distributors.
Input Power
Supply
Input
USB
Cable
GUI
Ribbon
Cable
Evaluation Board
USB to I2C Communication
Interface (EVKT-USBI2C-02)
Output
Load
Load
Figure 1: EVKT-MP28167-A Evaluation Kit Set-Up
MP28167-A Rev. 1.0
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3
MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
PACKAGE REFERENCE
TOP VIEW
QFN-16 (3mmx3mm)
MP28167-A Rev. 1.0
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
PIN FUNCTIONS
Pin #
Name
Description
Supply voltage. IN is the drain of the internal power device, and provides power to the entire
chip. The MP28167-A operates from a 2.8V to 22V input voltage. A capacitor (CIN) is required
to prevent large voltage spikes from appearing at the input. Place CIN as close to the IC as
possible.
Power ground. GND is the reference ground of the regulated output voltage. GND requires
extra consideration during PCB layout. Connect GND with copper traces and vias.
1
IN
2, 11
GND
3
EN
4
ALT
5
SCL
6
SDA
Data pin of the I2C interface. If not used, SDA should be pulled up to VCC.
7
OC
Output constant current limit set pin.
8
FB
Feedback. Sets the output voltage when connected to the tap of an external resistor divider
that is connected between output and GND.
9
VCC
10
AGND
12
OUT
Output power pin. Place the output capacitor close to OUT and GND.
13
BST2
Bootstrap. Connect a 0.1µF capacitor between SW2 and BST2 to form a floating supply
across the high-side switch driver.
14
SW2
Switching node of the second half bridge. Connect one end of the inductor to SW2 for the
current to run through the bridge.
15
SW1
Switching node of the first half bridge. Connect one end of the inductor to SW1 for the
current to run through the bridge.
16
BST1
Bootstrap. Connect a 0.1µF capacitor between SW1 and BST1 to form a floating supply
across the high-side switch driver.
On/off control for entire chip. Drive EN high to turn the device on. Drive EN low or float EN
to turn it off. EN has an internal 2MΩ pull-down resistor to ground.
Alert output. If ALT pulls to logic low, a fault or warning has occurred.
Clock pin of the I2C interface. SCL can support an I2C clock up to 3.4MHz. If not used, SCL
should be pulled up to VCC.
Internal 3.65V LDO regulator output. Decouple VCC with a 1µF capacitor.
Analog ground. Connect AGND to GND.
MP28167-A Rev. 1.0
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (2)
Thermal Resistance
Supply voltage (VIN) ..................................... 26V
VOUT .............................................................. 24V
VSW1, SW2 (DC) ................................-0.3V to +24.3V
VSW1, SW2 (10ns) ....................................-7V to +26V
VBST1, BST2 ............................................. VSWx + 4V
VEN ................................................-0.3V to +26V
VALT ..............................................-0.3V to +5.5V
All other pins ...................................-0.3V to +4V
Continuous power dissipation (TA = 25°C) (3) (6)
................................................................... 4.8W
Junction temperature ................................150°C
Lead temperature .....................................260°C
Storage temperature ................ -65°C to +150°C
QFN-16 (3mmx3mm)
EV28167-A-Q-00A (6) ............. 26 ........ 3.... °C/W
JESD51-7 (7) .......................... 50 ....... 12 ... °C/W
Notes:
2)
3)
4)
ESD Rating (4)
All pins (HBM) ........................................... ±2kV
All pins (CDM).............................................±2kV
Recommended Operating Conditions (5)
5)
Operation input voltage range ......... 2.8V to 22V
Output voltage range ..................... 1V to 20.47V
Output current .................. 3A continuous current
or 4A input current
Operating junction temp (TJ) .... -40°C to +125°C
6)
7)
Exceeding these ratings may damage the device.
The maximum allowable power dissipation is a function of the
maximum junction temperature, TJ (MAX), the junction-toambient thermal resistance, θJA, and the ambient
temperature, TA. The maximum allowable continuous power
dissipation at any ambient temperature is calculated by PD
(MAX) = (TJ (MAX) - TA) / θJA. Exceeding the maximum
allowable power dissipation produces an excessive die
temperature, and the regulator goes into thermal shutdown.
Internal thermal shutdown circuitry protects the device from
permanent damage.
HBM, per JEDEC specification JESD22-A114; CDM, per
JEDEC specification JESD22-C101. JEDEC document
JEP155 states that 500V HBM allows safe manufacturing with
a standard ESD control process. JEDEC document JEP157
states that 250V CDM allows safe manufacturing with a
standard ESD control process.
The device is not guaranteed to function outside of its
operating conditions.
Measured on EV28167-A-Q-00A, 4-layer PCB, 64mmx64mm.
Measured on JESD51-7, 4-layer PCB. The value of θJA given
in this table is only valid for comparison with other packages
and cannot be used for design purposes. These values were
calculated in accordance with JESD51-7 and simulated on a
specified JEDEC board. They do not represent the
performance obtained in an actual application.
MP28167-A Rev. 1.0
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
ELECTRICAL CHARACTERISTICS
VIN = 12V, VEN = 5V, TJ = -40°C to +125°C
noted.
Parameter
Symbol
(8),
typical value is tested at TJ = 25°C, unless otherwise
Condition
Min
Typ
Max
Units
3
μA
Shutdown supply current
IIN
VEN = 0V
0
Quiescent supply current
IQ
Non-switching, I2C sets PFM mode
1
EN rising threshold
EN hysteresis
EN to ground resistance
EN on to VOUT > 90% delay
VCC regulator
VCC load regulation
VIN under-voltage lockout
rising threshold
VIN under-voltage lockout
threshold hysteresis
VEN_RISING
1.00
VEN_HYS
REN
tDELAY
VEN = 2V
See Figure 7 on page 19
VCC
VCC_LOG
3.3
ICC = 10mA
1.10
mA
1.20
110
mV
2
MΩ
3.6
ms
3.65
4
1
VIN_UVLO
2.50
VUVLO_HYS
V
2.65
V
%
2.8
160
V
mV
Power Converter
HS switch on resistance
RDSON_HS
Switch A, D
25
40
mΩ
LS switch on resistance
RDSON_LSB Switch B, C
21
35
mΩ
-1%
1000
+1%
mV
-1.5%
1000
+1.5%
mV
Feedback voltage
VFB
Feedback current
IFB
Output discharge
resistance
RDIS
Switch leakage
Oscillator frequency
SWLKG
fS1
fS2
TJ = 25°C
TJ = -40°C to +125°C
VFB = 1.05V
10
60
nA
100
VEN = 0V, VSW1, SW2 = 22V, TJ = 25°C
1
VEN = 0V, VSW1, SW2 = 22V,
TJ = -40°C to +125°C
5
Set FREQ = 500kHz by I2C, TJ = 25°C -20%
2
520
+20%
Ω
μA
kHz
Set FREQ = 750kHz by I C, TJ = 25°C
750
kHz
Switch A, B, C, D
160
ns
Minimum on time (9)
tON_MIN1
Maximum duty cycle
DMAX
Buck mode, FREQ = 500kHz
85
%
Minimum duty cycle (9)
DMIN
Boost mode, FREQ = 500kHz
15
%
Can be changed by I2C, VREF from 0V
to 1V, default SS time
3.5
ms
Soft-start time
tSS
Protection
Output over-voltage
protection
VOVP_R
150%
160%
170%
VREF
Output OVP recovery
VOVP_F
130%
140%
150%
VREF
Low-side B valley limit
ILIMIT2
Switch B
6
8
10
A
Low-side C peak current
limit
ILIMIT3
Switch C
10
MP28167-A Rev. 1.0
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7
MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, VEN = 5V, TJ = -40°C to +125°C
noted.
Parameter
Output average current
typical value is tested at TJ = 25°C, unless otherwise
Symbol
Condition
Min
Typ
Max
Units
IOUT_LIM1
VOUT = 5V,
across 0°C to 125°C temp range
0.85
1
1.15
A
IOUT_LIM2
VOUT = 5V,
across 0°C to 125°C temp range
-5%
3.5
+5%
A
20µs deglitch, UV falling
45%
50%
55%
VREF
0.2
0.4
V
1
μA
(9)
Output UV threshold
(8),
VUVP
ALT sink current capability
ALT_LOW
Sink 4mA
ALT leakage
ALT_LKG
VPULL = 5V
Thermal shutdown rising
threshold (9)
Thermal hysteresis (9)
TSTD
150
°C
TSTD_HYS
20
°C
I2C Specification (9)
I2C pull-up VDD can be 1.8V to 5V
Input logic high
VIH
Input logic low
VIL
0.4
V
VOUT_L
0.4
V
3400
kHz
Output voltage logic low
1.4
V
SCL clock frequency
fSCL
SCL high time
tHIGH
60
ns
SCL low time
tLOW
160
ns
Data set-up time
tSU_DAT
10
ns
Data hold time
tHD_DAT
0
tSU_STA
160
ns
tHD_STA
160
ns
tBUF
160
ns
tSU_STO
160
ns
SCL and SDA rising time
tR
10
300
ns
SCL and SDA falling time
tF
10
300
ns
tSP
0
50
ns
400
pF
Set-up time for (repeated)
start condition
Hold time for (repeated)
start condition
Bus free time between a
start and a stop condition
Set-up time for stop
condition
Pulse width of suppressed
spike
Capacitance for each bus
line
400
60
CB
ns
Notes:
8)
9)
All min/max parameters are tested at TJ = 25°C. Over-temperature limits are guaranteed by design, characterization, and correlation.
Guaranteed by engineering sample characterization.
MP28167-A Rev. 1.0
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
TYPICAL CHARACTERISTICS
VIN = 12V, VOUT = 5V, L = 4.7µH, fSW = 500kHz, TA = 25°C, unless otherwise noted.
Load Regulation
Line Regulation vs. Input Voltage
VOUT = 5V
0.3
0.3
0.2
0.2
LINE REGULATION (%)
LOAD REGULATION (%)
VIN = 12V, VOUT = 5V/9V/12V/20V,
IOUT = 0A to 3A, no line drop compensation
0.1
0
-0.1
Vo=5V
Vo=9V
Vo=12V
Vo=20V
-0.2
-0.3
0
1
2
0.1
0
-0.1
Io=0A
Io=1.5A
Io=3A
-0.2
-0.3
3
2
4
6
INPUT VOLTAGE (V)
Line Regulation vs. Input Voltage
Line Regulation vs. Input Voltage
VOUT = 9V
VOUT = 12V
0.3
0.3
0.2
0.2
0.1
0
-0.1
Io=0A
Io=1.5A
Io=3A
-0.2
LINE REGULATION (%)
LINE REGULATION (%)
OUTPUT CURRENT (A)
-0.3
0.1
0
-0.1
Io=0A
Io=1.5A
Io=3A
-0.2
-0.3
2
4
6
8 10 12 14 16 18 20 22 24
2
INPUT VOLTAGE (V)
4
6
8 10 12 14 16 18 20 22 24
INPUT VOLTAGE (V)
Line Regulation vs. Input Voltage
Thermal Rise vs. Output Current
VOUT = 20V
VIN = 12V, VOUT = 5V to 20V, IOUT = 0A to 3A
0.3
40
0.2
35
0.1
0
-0.1
-0.2
Io=0A
Io=1A
Io=2A
-0.3
-0.4
2
4
6
8 10 12 14 16 18 20 22 24
INPUT VOLTAGE (V)
THERMAL RISE (℃）
LINE REGULATION (%)
8 10 12 14 16 18 20 22 24
30
25
20
15
Vo=5V
Vo=9V
Vo=12V
Vo=20V
10
5
0
0
1
2
OUTPUT CURRENT (A)
MP28167-A Rev. 1.0
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9
MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
TYPICAL CHARACTERISTICS (continued)
VIN = 12V, VOUT = 5V, L = 4.7µH, fSW = 500kHz, TA = 25°C, unless otherwise noted.
Efficiency vs. Output Current
Efficiency vs. Output Current
VOUT = 5V to 20V, RDC = 16.5mΩ,
forced PWM mode
VOUT = 5V to 20V, RDC = 16.5mΩ, PFM mode
95
95
90
90
85
EFFICIENCY (%)
100
EFFICIENCY (%)
100
Vout=12V
80
Vout=5V
75
Vout=9V
70
Vout=15V
65
0.1
1
OUTPUT CURRENT (A)
Vout=9V
75
Vout=12V
70
Vout=20V
60
0.01
10
Recommended VIN, VOUT, IOUT
Operation Range
0.1
1
OUTPUT CURRENT (A)
3.5
6
5.8
OUTPUT VOLTAGE (V)
3
2.5
Vo=5V
2
Vo=9V
1.5
Vo=12V
1
Vo=15V
0.5
Vo=20V
0
2
4
6
5.6
5.4
5.2
5
4.8
4.6
4.4
4.2
0
4
8 10 12 14 16 18 20 22 24
-60
-40
INPUT VOLTAGE (V)
-20
0
20
40
60
80
100
TEMPERATURE (°C)
VIN UVLO Rising and Falling
Threshold vs. Temperature
EN Rising and Falling Threshold vs.
Temperature
2
EN RISING AND FALLING
THRESHOLD (V)
3
VIN UVLO RISING AND
FALLING THRESHOLD (V)
10
Output Voltage vs. Temperature
22μF x 5 ceramic COUT capacitor
IO_MAX(A)
Vout=5V
80
65
Vout=20V
60
0.01
85
2.5
2
1.5
1
0.5
Rising
Falling
0
1.5
1
0.5
Rising
Falling
0
-60
-40
-20
0
20
40
60
TEMPERATURE (°C)
80
100
-60
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
TYPICAL CHARACTERISTICS (continued)
VIN = 12V, VOUT = 5V, L = 4.7µH, fSW = 500kHz, TA = 25°C, unless otherwise noted.
Output Voltage UVP Threshold vs.
Temperature
Buck Current Limit vs. Temperature
100
90
OUTPUT VOLTAGE UVP
THRESHOLD (%)
BUCK CURRENT LIMIT (A)
10
8
6
4
2
0
-60
-40
-20
0
20
40
60
TEMPERATURE (°C)
80
100
80
70
60
50
40
30
20
Falling
Rising
10
0
-60
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 5V, L = 4.7µH, fSW = 500kHz, TA = 25°C, test waveform is based on Figure 17,
unless otherwise noted.
EN Bit Enabled through I2C
Command
EN Bit Enabled through I2C
Command
Load = 0A
Load = 3A
CH1: VOUT
5V/div.
CH1: VOUT
5V/div.
CH2: VSW1
10V/div.
CH3: VSW2
5V/div.
CH2: VSW1
10V/div.
CH3: VSW2
5V/div.
CH4: IL
2A/div.
CH4: IL
2A/div.
2ms/div.
2ms/div.
EN Bit Shutdown through I2C
Command
EN Bit Shutdown through I2C
Command
Load = 0A
Load = 3A
CH1: VOUT
5V/div.
CH1: VOUT
5V/div.
CH2: VSW1
10V/div.
CH3: VSW2
10V/div.
CH2: VSW1
10V/div.
CH3: VSW2
5V/div.
CH4: IL
2A/div.
CH4: IL
2A/div.
2ms/div.
100μs/div.
EN Pin Enabled
EN Pin Enabled
Load = 0A
Load = 3A
CH1: VOUT
5V/div.
CH1: VOUT
5V/div.
CH2: VSW1
10V/div.
CH3: VSW2
5V/div.
CH2: VSW1
10V/div.
CH3: VSW2
5V/div.
CH4: IL
2A/div.
CH4: IL
2A/div.
2ms/div.
1ms/div.
MP28167-A Rev. 1.0
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 5V, L = 4.7µH, fSW = 500kHz, TA = 25°C, test waveform is based on Figure 17,
unless otherwise noted.
EN Pin Disabled
EN Pin Disabled
Load = 0A
Load = 3A
CH1: VOUT
5V/div.
CH1: VOUT
5V/div.
CH2: VSW1
10V/div.
CH3: VSW2
5V/div.
CH2: VSW1
10V/div.
CH3: VSW2
10V/div.
CH4: IL
2A/div.
CH4: IL
2A/div.
10ms/div.
50μs/div.
VIN Start-Up
VIN Start-Up
Load = 0A
Load = 3A
CH1: VOUT
5V/div.
CH1: VOUT
5V/div.
CH2: VSW1
10V/div.
CH3: VSW2
5V/div.
CH2: VSW1
10V/div.
CH3: VSW2
10V/div.
CH4: IL
2A/div.
CH4: IL
2A/div.
2ms/div.
2ms/div.
VIN Shutdown
VIN Shutdown
Load = 0A
Load = 3A
CH1: VOUT
5V/div.
CH1: VOUT
5V/div.
CH2: VSW1
10V/div.
CH3: VSW2
5V/div.
CH2: VSW1
10V/div.
CH3: VSW2
5V/div.
CH4: IL
2A/div.
CH4: IL
5A/div.
10ms/div.
500μs/div.
MP28167-A Rev. 1.0
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 5V, L = 4.7µH, fSW = 500kHz, TA = 25°C, test waveform is based on Figure 17,
unless otherwise noted.
Steady State
Steady State
VOUT = 5V, load = 0A, fSW = 500kHz
VOUT = 5V, load = 3A, fSW = 500kHz
CH1: VOUT
20mV/div.
CH1: VOUT
20mV/div.
CH2: VSW1
10V/div.
CH3: VSW2
5V/div.
CH2: VSW1
10V/div.
CH3: VSW2
5V/div.
CH4: IL
2A/div.
CH4: IL
5A/div.
2μs/div.
2μs/div.
Steady State
Steady State
VOUT = 5V, load = 0A, fSW = 750kHz
VOUT = 5V, load = 3A, fSW = 750kHz
CH1:
VOUT/AC
10mV/div.
CH1:
VOUT/AC
10mV/div.
CH2: VSW1
5V/div.
CH3: VSW2
5V/div.
CH2: VSW1
5V/div.
CH3: VSW2
5V/div.
CH4: IL
2A/div.
CH4: IL
2A/div.
1μs/div.
1μs/div.
I2C VID
I2C VID
VOUT = 5V to 12V, IOUT = 0A, R1 = 430kΩ,
R2 = 53.6kΩ
VOUT = 12V to 5V, IOUT = 0A, R1 = 430kΩ,
R2 = 53.6kΩ
CH1: VOUT
5V/div.
CH1: VOUT
5V/div.
CH2: VSW1
10V/div.
CH3: VSW2
10V/div.
CH2: VSW1
10V/div.
CH3: VSW2
10V/div.
CH4: IL
2A/div.
CH4: IL
2A/div.
2ms/div.
2ms/div.
MP28167-A Rev. 1.0
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 5V, L = 4.7µH, fSW = 500kHz, TA = 25°C, test waveform is based on Figure 17,
unless otherwise noted.
I2C VID
I2C VID
VOUT = 5V to 12V, IOUT = 3A, R1 = 430kΩ,
R2 = 53.6kΩ
VOUT = 12V to 5V, IOUT = 3A, R1 = 430kΩ,
R2 = 53.6kΩ
CH1: VOUT
5V/div.
CH1: VOUT
5V/div.
CH2: VSW1
10V/div.
CH3: VSW2
10V/div.
CH2: VSW1
10V/div.
CH3: VSW2
10V/div.
CH4: IL
5A/div.
CH4: IL
5A/div.
2ms/div.
2ms/div.
Load Transient
Load Transient
VIN = 12V, VOUT = 5V, no line drop compensation,
0A to 1.5A, 150mA/μs
VIN = 12V, VOUT = 5V, no line drop compensation,
1.5A to 3A, 150mA/μs
CH2:
CH2:
VOUT/AC
500mV/div.
VOUT/AC
500mV/div.
CH4: IOUT
1A/div.
CH4: IOUT
1A/div.
500μs/div.
500μs/div.
Short-Circuit Protection Entry with
Latch-Off Mode
Short-Circuit Protection Entry with
Hiccup Mode
CH1: VOUT
5V/div.
CH1: VOUT
5V/div.
CH2: VSW1
10V/div.
CH3: VSW2
10V/div.
CH2: VSW1
10V/div.
CH3: VSW2
10V/div.
CH4: IL
10A/div.
CH4: IL
10A/div.
5ms/div.
20ms/div.
MP28167-A Rev. 1.0
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 5V, L = 4.7µH, fSW = 500kHz, TA = 25°C, test waveform is based on Figure 17,
unless otherwise noted.
Short-Circuit Protection Recovery
with Hiccup Mode
CC Current Limit Entry
(Test with CV mode of electronic load)
CH1: VOUT
5V/div.
CH1: VOUT
2V/div.
CH2: VSW1
10V/div.
CH3: VSW2
10V/div.
CH2: VSW1
10V/div.
CH3: VSW2
5V/div.
CH4: IL
10A/div.
CH4: IL
5A/div.
20ms/div.
100ms/div.
CC Current Limit Steady State
VOUT OVP with Hiccup Mode
CH1: VOUT
5V/div.
CH1: VOUT
5V/div.
CH2: VSW1
10V/div.
CH3: VSW2
5V/div.
CH2: VSW1
10V/div.
CH3: VSW2
5V/div.
CH4: IL
5A/div.
CH4: IL
2A/div.
1μs/div.
500ms/div.
VOUT OVP with Latch-Off Mode
CH1: VOUT
5V/div.
CH2: VSW1
10V/div.
CH3: VSW2
5V/div.
CH4: IL
5A/div.
500ms/div.
MP28167-A Rev. 1.0
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
FUNCTIONAL BLOCK DIAGRAM
IN
OUT
VCC
Regulator
VCC
Bootstrap
Regulator
HS
Driver
On Timer
SCL
SDA
BST1
A
DAC
I2C/OTP
IF and
Register
SW1
VCC
A, B, C, D
FET Sensing
ALT
LS
Driver
B
GND
EN
Current Limit
Comparator
Reference
Buck-Boost
Control Logic
2MΩ
Bootstrap
Regulator
IN
OUT
BST2
COMP
FB
Error
Amplifier
HS
Driver
VCC
SW2
VCC
SS
PG and
OVP
D
LS
Driver
OV
C
GND
OC
AGND
Figure 1: Functional Block Diagram
MP28167-A Rev. 1.0
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
OPERATION
The MP28167-A is a four-switch, integrated
buck-boost converter that can work in constanton-time (COT) control mode with a fixed
frequency. This provides fast transient response
for the buck, boost, and buck-boost modes. A
special buck-boost control strategy provides
high efficiency over the full input range, and
smooth transient between different modes.
Buck-Boost Operation
The MP28167-A can regulate the output voltage
(VOUT) to be above, equal to, or below the input
voltage (VIN). Figure 2 shows a power structure
with one inductor and the four switches.
SWA works with COT control logic, and SWB
turns on as a complement of SWA. In each cycle,
SWB turns on to conduct the inductor current.
When the inductor current drops to the COMP
voltage (VCOMP), SWB turns off and SWA turns
on. SWA turns on for a fixed on time before
turning off. Then SWB turns on again, and the
operation repeats. The COMP signal is the error
amplifier (EA) output from the VOUT feedback and
internal FB reference voltage (see Figure 4).
SW1
SW2
IL
tON
COMP
Control by COMP
Figure 4: Buck Waveform
Boost Mode
When VIN is significantly lower than VOUT, the
MP28167-A works in boost mode. In boost
mode, SWC and SWD switch for the boost
regulation. SWB is off, and SWA remains on to
conduct the inductor current.
Figure 2: Buck-Boost Topology
The MP28167-A can operate in buck mode,
boost mode, or buck-boost mode with different
VIN inputs (see Figure 3).
Boost
Buck-Boost
SWA On, SWB Off,
SWC and SWD
Switching
All FETs
Switching
Buck
D On, C Off,
A and B Switching
VO-SET
VIN Voltage
Boost
DMAX
Boost
DMIN
During each period, SWC remains off with COT
control, while SWD turns on as a complement of
SWC to boost the inductor current to the output.
In each cycle, SWC turns on to conduct the
inductor current. When the inductor current rises
and reaches VCOMP, SWC turns off and SWD
turns on. SWC turns off with a fixed off time
before turning on again. During this period, SWD
turns on for the current freewheel (see Figure 5).
Buck
DMAX
Buck
DMIN
Figure 3: Buck-Boost Operation Range
Buck Mode
When VIN is significantly higher than VOUT, the
MP28167-A works in buck mode. In buck mode,
SWA and SWB switch for buck regulation. SWC
is off, and SWD remains on to conduct the
inductor current.
SW1
SW2
COMP
IL
Control by COMP
tOFF
Figure 5: Boost Waveform
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
Buck-Boost Mode
When VIN is almost equal to VOUT, the MP28167A cannot provide enough energy to operate in
buck mode due to SWA’s minimum off time, or it
supplies too much power to VOUT in boost mode
due to SWC’s minimum on time. The IC uses
buck-boost control to regulate VOUT in these
conditions.
If VIN drops and the SWA off period is close to
the minimum buck off time in buck mode, buckboost mode is engaged. When the next cycle
starts after the SWA and SWD on time (the buck
high-side MOSFET [HS-FET] on period), the
boost starts with SWA and SWC on (boost lowside MOSFET [LS-FET] on).
SWA and SWD turn on again for the resting
period of boost mode (boost HS-FET on). After
the boost period elapses, the buck period starts,
and SWB and SWD remain on until the inductor
current drops to VCOMP. Then SWA and SWD turn
on until the next boost period begins. Buck and
boost switching work with a one-interval period.
This is called buck-boost mode.
If VIN rises, and the SWC on period is close to
the boost minimum on time in boost mode, buckboost mode is enabled. After the boost constantoff-time period (SWA and SWD on), SWB and
SWD remain on until the inductor current signal
drops to VCOMP, just like a buck off-time period
control.
After the inductor current signal triggers VCOMP,
SWA and SWD turn on for the buck on time,
which is followed by boost switching (SWA and
SWC on). Buck and boost switching work with a
one-interval period. Figure 6 shows the buckboost waveform when VIN exceeds VOUT.
SW1
tBOOST-MIN
SW2
Buck Min Off Time
IL
COMP
Buck Buck-Boost
tBUCK-BOOST
Figure 6: Buck to Buck-Boost Transient
Figure 7 shows the buck-boost waveform when
VOUT exceeds VIN.
If VIN exceeds 130% of VOUT in buck-boost mode,
the MP28167-A switches from buck-boost mode
to buck mode. If VIN drops below 20% of VOUT,
the MP28167-A switches from buck-boost mode
to boost mode.
SW1
tBUCK-MIN
SW2
Boost Min On Time
COMP
IL
Boost Buck-Boost
tBUCK-BOOST
Figure 7: Buck-Boost Waveform
Working Mode Selection
The MP28167-A works with a fixed frequency
under heavy-load conditions. When the load
current decreases, the MP28167-A can work in
forced continuous conduction mode (FCCM) or
pulse-skip mode (PSM) based on the MODE
register setting.
FCCM (or Forced PWM)
In forced continuous conduction mode (FCCM),
the buck on time and boost off time are
determined by the internal circuit. This achieves
a fixed frequency based on the VIN / VOUT ratio.
When the load decreases, the average input
current drops, and the inductor current may go
negative from VOUT to VIN during the off time
(SWD on). This forces the inductor current to
work in continuous mode with a fixed frequency,
producing a lower VOUT ripple than in PSM mode.
PSM (Auto-PFM/PWM Mode)
If the inductor current drops to 0A in PSM, SWD
turns off to prevent the current from flowing from
VOUT to VIN, forcing the inductor current to work
in discontinuous conduction mode (DCM).
Meanwhile, the internal off time clock stretches
once the MP28167-A enters DCM mode. The
frequency drops when the inductor current
conduction period decreases, which helps save
power loss and reduce the VOUT ripple.
If VCOMP drops to the PSM threshold (even if the
IC stretches the frequency), the MP28167-A
stops switching to further decrease the switching
power loss.
MP28167-A Rev. 1.0
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
The MP28167-A recovers switching once VCOMP
exceeds the PSM threshold. The switching pulse
skips based on VCOMP in very light-load
conditions. PSM has a much higher efficiency
than FCCM mode in light load, but the VOUT ripple
may be higher due to the group switching pulse.
Internal VCC Regulator
The 3.65V internal regulator powers most of the
internal circuitries. This regulator takes VIN and
operates in the full VIN range. When VIN exceeds
3.65V, the output of the regulator is in full
regulation. If VIN drops below 3.65V, the output
decreases with VIN. VCC requires an external
1µF ceramic capacitor for decoupling.
Enable (EN) Control
The MP28167-A has an enable (EN) control pin.
Pull EN high to enable the IC. Pull EN low or float
EN to disable the IC.
If EN is pulled down when the output discharge
function is enabled, the MP28167-A shuts down
after 55ms. The MP28167-A’s I2C register value
is reset to default only after the MP28167-A
experiences this type of shutdown. If EN is pulled
high within 55ms, the I2C register is not reset,
and the MP28167-A enables the output with the
previous register setting.
If the output discharge function is disabled, the
MP28167-A shuts down once EN is pulled down
for more than 100µs, and the MP28167-A I2C
register is reset after a 100µs delay.
VOUT = 12V (I2C Setting)
VOUT = 12V (I2C Setting)
VOUT = 5V (I2C Reset)
EN
EN Off
< 55ms
EN Off > 55ms
Figure 8: EN On/Off Logic for I2C Register Reset
Under-Voltage Lockout (UVLO)
Under-voltage lockout (UVLO) protects the chip
from operating at an insufficient supply voltage.
The UVLO comparator monitors the input
voltage and enables or disables the entire IC.
Internal Soft Start (SS)
Soft start (SS) prevents the converter output
voltage from overshooting during start-up. When
the chip starts up, the internal circuitry generates
an SS voltage that ramps up from 0V to 3.65V. If
the SS voltage (VSS) is below VREF, the error
amplifier uses VSS as the reference. If VSS
exceeds VREF, the error amplifier uses VREF as
the reference.
If the output of the MP28167-A is pre-biased to a
certain voltage during start-up, the IC disables
the switching of both the HS-FET and LS-FET
until the voltage on the internal SS capacitor
exceeds the internal feedback voltage (see
Figure 8).
EN
VOUT
90%
tDELAY
Figure 9: EN On to VOUT > 90% Delay
Over-Current Protection (OCP)
The MP28167-A has a constant-current limit
control loop to limit the output average current.
The current information is sensed from switches
A, B, C, and D. Then an average algorithm
calculates the output current.
When the output current exceeds the currentlimit threshold, the output voltage starts to drop.
There are two conditions that activate this
condition:
1. The first is if VOUT exceeds 3V, VFB drops
below 50% of VREF, and VOUT drops below 3V.
The MP28167-A then enters hiccup mode or
latch off mode according to the I2C setting.
2. The second is if VOUT is set below or equal to
3V, and VOUT drops below the under-voltage
(UV) threshold (typically 50% below VREF).
The MP28167-A then enters hiccup mode or
latch-off mode according to the I2C setting.
In hiccup mode, the MP28167-A stops switching
and recovers automatically with 12.5% duty
cycles. In latch-off mode, the MP28167-A stops
switching until the IC restarts (power cycling on
VIN or EN, or EN bit toggling).
Over-Voltage Protection (OVP)
The MP28167-A monitors a resistor-divided
feedback voltage to detect output over-voltage
(OV) conditions. When the feedback voltage
exceeds 160% of the target voltage, the overvoltage protection (OVP) comparator output
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
goes high. The output-to-ground discharge
resistor turns on.
The OUT pin has an absolute OVP function.
Once VOUT exceeds the absolute OVP threshold
(23V), the MP28167-A stops switching and turns
on the OUT-to-ground discharge resistor.
Start-Up and Shutdown
If both VIN and EN exceed their respective
thresholds, the chip is enabled. The reference
block starts first, generating a stable reference
voltage and current, and then the internal
regulator is enabled. The regulator provides a
stable supply for the remaining circuitries.
Three events can shut down the chip: EN going
low, VIN going low, and thermal shutdown. During
shutdown, the signaling path is blocked to avoid
fault triggers. Then VCOMP and the internal supply
rail are pulled down. The floating driver is not
subject to this shutdown command.
Output Discharge
The MP28167-A has an output discharge
function that provides a resistive discharge path
for the external output capacitor. The function is
active when the part is disabled (input voltage is
under UVLO or enable off), the discharge path is
turned off when VOUT < 50mV or waits for the
50ms maximum timer to pass. This function can
also be disabled via the I2C.
Thermal Warning (TSW) and Shutdown (TSD)
Thermal warning and thermal shutdown prevent
the part from operating at exceedingly high
temperatures. When the silicon die temperature
exceeds 120°C, the MP28167-A sets the OTW
bit [D5] to 1. When the temperature falls below
its lower threshold (typically 100°C), the OTW bit
[D5] is set to 0.
When the silicon die temperature exceeds
150°C, the entire chip shuts down. When the
temperature falls below its lower threshold
(typically 130°C), the chip is enabled. This is a
non-latch protection.
2
I C INTERFACE
I2C Serial Interface Description
The I2C is a two-wire, bidirectional,
interface consisting of a data line (SDA)
clock line (SCL). The lines are pulled to
voltage externally when they are idle.
serial
and a
a bus
When
connecting to the line, a master device
generates the SCL signal and device address,
and arranges the communication sequence.
The MP28167-A interface is an I2C slave that
supports fast mode (400kHz) and high-speed
mode (3.4MHz). The I2C interface adds flexibility
to the power supply solution. The output voltage,
transition slew rate, and other parameters can be
controlled instantaneously via the I2C interface.
When the master sends the address as an 8-bit
value, the 7-bit address should be followed by a
0 to indicate a write operation, or 1 to indicate a
read operation.
Start and Stop Conditions
The start and stop conditions are signaled by the
master device, which signifies the beginning and
end of an I2C transfer. The start (S) condition is
defined as the SDA signal transitioning from high
to low while the SCL is high. The stop (P)
condition is defined as the SDA signal
transitioning from low to high while the SCL is
high (see Figure 9).
The master then generates the SCL clocks and
transmits the device address and the read/write
direction bit (R/W) on the SDA line.
Transfer Data
Data is transferred in 8-bit bytes by an SDA line.
Each byte of data should be followed by an
acknowledge (ACK) bit.
I2C Update Sequence
The MP28167-A requires a start condition, a
valid I2C address, a register address byte, and a
data byte for a single data update. The
MP28167-A acknowledges that it has received
each byte by pulling the SDA line low during the
high period of a single clock pulse. A valid I2C
address selects the MP28167-A. The MP28167A performs an update on the falling edge of the
LSB byte. See Figure 11, Figure 12, and Figure
13 for examples I2C write and read sequences.
I2C Start-Up Timing
I2C functionality is enabled once EN is active and
VIN exceeds the under-voltage lockout (UVLO)
threshold. The I2C works during over-current
protection (OCP), over-voltage protection (OVP),
and thermal shutdown.
MP28167-A Rev. 1.0
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
SDA
SCL
S
P
Stop Condition
Start Condition
Figure 10: Start and Stop Conditions
8 Bits
S
8 Bits
Slave Address
WR
A
8 Bits
Register Address K
A
Write Data
A
P
Master to Slave
A = Acknowledge (SDA = Low)
S = Start Condition
WR Write = 0
Slave to Master
NA = Not Acknowledge (SDA = High)
P = Stop Condition
RD Read = 1
Figure 11: I2C Write Example (Write Single Register)
S
Slave Address
8 Bits
8 Bits
8 Bits
WR
A
Register Address K
A
Write Data K
A
Write Data K + 1
A
Write Data K + N
A
P
Multi-byte write executed from current register location (the
read-only register is skipped)
Master to Slave
A = Acknowledge (SDA = Low)
S = Start Condition
WR Write = 0
Slave to Master
NA = Not Acknowledge (SDA = High)
P = Stop Condition
RD Read = 1
Figure 12: I2C Write Example (Write Multi-Register)
8 Bits
S
Slave Address
8 Bits
WR
A
Register Address K
8 Bits
8 Bits
A
Sr
Register address to read specified
Slave Address
RD
A
Read Data K
NA
P
Read register data from current register location
Master to Slave
A = Acknowledge (SDA = Low)
S = Start Condition
Slave to Master
NA = Not Acknowledge (SDA = High)
P = Stop Condition
Sr = Repeat
Start Condition
WR Write = 0
RD Read = 1
Figure 13: I2C Read Example (Read Single Register)
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
I2C REGISTER MAP
Add
(Hex)
Name
R/W
00
VREF_L
R/W
01
VREF_H
R/W
02
VREF_GO
R/W
03
IOUT_LIM
R/W
RESERVED
04
CTL1
R/W
EN (10)
05
06
07
08
09
CTL2
RESERVED
RESERVED
RESERVED
Status
R/W
R
R
R
R
0A
INTERRUPT
W1C
0B
MASK
R/W
0C
27
28
29
ID1
MFR_ID
DEV_ID
IC_REV
R
R
R
R
D7
D6
D5
D4
D3
D2
D1
D0
VREF DATA BIT LOW [2:0] (10)
RESERVED
VREF DATA BIT HIGH [10:3] (10)
PG_
DELAY_
EN (10)
RESERVED
Output current limit threshold (0A to 6.35A/50mA step for 21.5kΩ OC resistor) (10)
HICCUP
OCP_OVP (10)
LINE DROP COMP (10)
PG
OTEMPP_
ENTER
GO_
BIT
OTP
OT
WARNING_
ENTER
DISCHG
_EN (10)
MODE (10)
FREQ (10)
(10)
SS
RESERVED, ALL “0”
RESERVED
RESERVED
OTW
CC_CV
OC_
ENTER
OC_
RECOVER
RESERVED
RESERVED
RESERVED
RESERVED
UVP_
FALLING
OTEMPP
_EXIT
OC_
MSK (10)
OTP Configure Code. “0x00” means the standard MP28167-A
Manufacturer ID: b ‘0000 1001’
Device ID: b ‘0101 1000’
IC revision: b ‘0000 0001’
RESERVED
OTPMSK
OTWMSK
(10)
(10)
OT
WARNING
_EXIT
PG_
RISING
UVP_
MSK (10)
PG_
MSK (10)
Note:
10) These items have one-time programmable (OTP) non-volatile memory. The OTP is reloaded to the I2C register when VIN exceeds the
under-voltage lockout (UVLO) threshold, or during EN shutdown.
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
REGISTER DESCRIPTION
I2C Bus Slave Address
The MP28167-A I2C slave address is fixed as 60H.
Output Reference Voltage Setting
The registers VREF_L and VREF_H set the reference voltage and follow 11-bit direct format.
Name
VREF
Format
Register
Name
Bit
Direct, unsigned binary integer
N/A
15
14
13
Access
N/A
Function
Default
Value
(1000mV)
N/A
VREF_H D[7:0]
12
11
VREF_L D[2:0]
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data bit high
N/A
Data bit low
1250 integer
The reference voltage can be calculated with Equation (1):
VREF (mV) = V x 0.8
(1)
Where V is an 11-bit unsigned binary integer of VREF[10:0] that ranges from 0 to 2047. The VREF
resolution is 0.8mV/LSB. The reference voltage changing slew rate is fixed at 1mV/µs. See the GO_BIT
section below to change the reference voltage.
VREF_GO Register
GO_BIT D[0]
The MP28167-A can be controlled when VREF begins to change. Set GO_BIT to 1 to start the output
reference change based on the VREF register. When the VREF change is complete (internal VREF reaches
its target value), GO_BIT auto-resets to 0. This prevents a false operation of VREF scaling.
Write the reference voltage (0x00 and 0x01 registers) first, and then write GO_BIT = 1. VREF changes
based on the new register setting. GO_BIT resets to 0 when VREF reaches a new value. The host can
read GO_BIT to determine whether VREF scaling has completed.
The VOUT-to-ground discharge function is enabled when GO_BIT = 1. This can ramp VOUT from high to
low under light-load conditions.
When GO_BIT = 0, VREF does not change. When GO_BIT = 1, VREF changes based on the VREF register
setting. After VREF scaling finishes, GO_BIT is automatically reset to 0.
PG_DELAY_EN D[1]
When PG_DELAY_EN D[1] = 0, there is no delay on PG. When PG_DELAY_EN D[1] = 1, PG
experiences a 100µs rising delay. The default value is 0.
IOUT_LIM Register
Sets the output current limit threshold.
Name
IOUT_LIM
Format
Direct, unsigned binary integer
Bit
7
6
5
4
3
2
1
0
Access
N/A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
(3.5A)
N/A
70 integer
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
IOUT_OC can be calculated with Equation (2):
IOUT_OC (A) = IOUT_LIM x 0.05
(2)
Where IOUT_LIM is a 7-bit unsigned binary integer of IOUT_LIM D[6:0], and the IOUT_OC resolution is
50mA/LSB (maximum value is 6.35A).
The resistor connected from the OC pin to ground should be 21.5kΩ when using the IOUT_LIM register.
Add a 22nF (C6) filter capacitor on OC to keep the CC loop stable. The MP28167-A allows IOUT_LIM to
be directly changed using the I2C. If the CC threshold must be changed after the MP28167-A has already
entered the CC limit operation state, it is recommended to change the CC threshold step by step (e.g.
50mA per step) instead of changing the current value to the final value.
CTL1 Register
Bits
Bit Name
Default
D[7]
EN
1
D[6]
HICCUP
OCP_OVP
1
D[5]
DISCHG_EN
1
D[4]
MODE
1
Description
I2C-controlled bit to turn the part on and off. When the external EN pin is low, the
converter is off, and the I2C shuts down. When EN is high, the EN bit takes over.
1: Enable the part
0: Disable the part
Over-current (OC) and over-voltage protection (OVP) mode selection.
1: Hiccup mode
0: Latch-off mode
Output discharge enable bit.
1: Output discharge occurs during EN or VIN shutdown
0: No output discharge occurs during shutdown
Enable PFM/PWM mode bit. The default is PWM mode under light-load conditions.
0: Enables auto-PFM/PWM mode
1: Sets forced PWM mode
Sets the switching frequency.
D[3:2]
FREQ
00
00: 500kHz
01: 750kHz
10: Reserved
11: Reserved
CTL2 Register
Bits
D[7:6]
Bit Name
LINE DROP
COMP
Default
00
Description
Sets the output voltage compensation (VLINE vs. the load feature).
00: No compensation
01: VOUT compensates 60mV when IOUT = 3A
10: VOUT compensates 120mV when IOUT = 3A
11: VOUT compensates 200mV when IOUT = 3A
VOUT compensation is based on R1 and R2. VLINE = (1 + R1 / R2) x VREFLINE. Where
VREFLINE is 0mV/12mV/24mV/40mV when the D[7:6] bits are 00/01/10/11,
respectively. VLINE is the compensated voltage.
Sets the output start-up soft-start timer (from 0% to 100%). If the reference voltage
is 1V:
D[5:4]
SS
10
00: 1.1ms
01: 2.2ms
10: 3.5ms
11: 4.4ms
The SS slew rate is constant, but SS time changes with different VREF values. For
example, the SS time = 3.5ms for 1V VREF, and the SS time = 5.25ms for 1.5V VREF.
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
Status Register
Bit
Bit Name
Default
Description
Output power good indication.
D[7]
PG
N/A
D[6]
OTP
N/A
0: OTP has not occurred
1: OTP has occurred
Over-temperature warning (OTW) indication.
D[5]
OTW
N/A
D[4]
CC_CV
N/A
0: OTW has not occurred
1: OTW has occurred
Enable bit for constant-current (CC) output mode or constant-voltage
(CV) output mode.
Notes
0: Output power is not good
1: Output power is good
Over temperature protection (OTP) indication.
These status
bits indicate
instantaneous
values.
0: CV mode
1: CC mode
Interrupt Register
Bits
Bit Name
Description
D[7]
OTEMPP_
ENTER
Over-temperature protection entry indication. When this bit is high, the IC
enters thermal shutdown. This bit is not masked, even if OTPMSK = 1.
Setting OTPMSK to 1 only masks the interrupt pin’s output (ALT).
D[6]
OTWARNING_
ENTER
Die temperature early warning enter bit. When this bit is high, the die
temperature exceeds 120°C. This bit is not masked, even if OTWMSK = 1.
Setting OTWMSK to 1 only masks the interrupt pin’s output (ALT).
D[5]
OC_ENTER
Entry of over-current (OC) or constant-current (CC) current-limit mode. THE
OC_MSK bit can enable or disable the OC_ENTER and OC_RECOVER
ALERT outputs.
This bit is
latched once
triggered.
D[4]
OC_RECOVER
Recovery from constant-current (CC) current-limit mode. If the device
recovers from a hiccup, it does not trigger this interrupt signal.
D[3]
UVP_FALLING
Reference voltage is in under-voltage protection (UVP) threshold.
D[2]
OTEMPP_EXIT
Over-temperature protection (OTP) ends. OTPMSK can mask off the ALT
signals of this bit.
Write 0xFF to
this register to
reset the
interrupt and
ALT pin’s state.
D[1]
OTWARNING_
EXIT
Die temperature early warning exit bit. When the die temperature is below
100°C, this bit is set to 1. This bit is not masked, even if OTWMSK = 1.
Setting OTWMSK to 1 only masks the interrupt pin’s output (ALT).
D[0]
PG_RISING
Output power good rising edge.
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Notes
26
MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
MSK Register
Bit
Bit Name
Default
Description
D[4]
OTPMSK
0
Set OTPMSK to 1 to mask off the over-temperature protection (OTP) alert. Setting
OTPMSK to 1 only masks the interrupt pin’s output (ALT). This is not the interrupt
register, but it is similar for other mask bits.
D[3]
OTWMSK
0
Masks off the over-temperature warning.
D[2]
OC_MSK
0
Masks off both over-current (OC) and constant current (CC) entry and recovery.
D[1]
UVP_MSK
0
Masks off the output under-voltage protection (UVP) interrupt.
Masks off the PG indication function on ALT.
D[0]
PG_MSK
0
1: The ALT pin does not indicate a PG event
0: The ALT indicates a PG rising event
OTEMPP_ENTER,
OTWARNING_ENTER,
or OC_ENTER
Event
ALT Pin
Active
Low
Write 0xFF to 0A Reg to
OTEMPP_EXIT,
ALT pin
OTWARNING_EXIT,
or OC_RECOVER
Event
Figure 14: ALT Behavior of OTP, OT Warning, and OC Recovery
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
APPLICATION INFORMATION
Setting the Output Voltage
The external resistor divider sets the output
voltage. R1 can be calculated with Equation (1):
V VREF
R1 OUT
R2
VREF
MP28167-A
R1
FB
Figure 15: Feedback Network
Table 1 lists the recommended resistors and
inductor values for common output voltages. If
the I2C is not used to set the output voltage, it
can be set using the resistors below.
Table 1: Resistor Selection for Common Output
Voltages
R2 (kΩ)
107
53.6
39.2
28.7
20.5
RT (kΩ)
806
787
787
402
200
L (μH)
4.7
4.7
4.7
4.7
3.3
Selecting the Inductor
The inductor selection is based on which mode
the device operates in. The inductance for buck
mode (LBUCK) can be estimated with Equation (2):
L B UCK
VOUT
V
(1 OUT )
f SW IL
VIN
(3)
In addition to the inductance value, the inductor
must support the peak current to avoid saturation.
The peak current can be calculated with
Equation (4) and Equation (5) for buck and boost
mode, respectively:
R2
R1 (kΩ)
430
430
430
402
390
VIN ( VOUT VIN )
VOUT f SW IL
Choosing a larger-value inductor reduces the
ripple current but increases the physical size of
the inductor. A larger-value inductor also
reduces the converter’s bandwidth by moving
the right half-plane zero to lower frequencies.
This tradeoff should be determined based on the
application requirements.
VOUT
VOUT (V)
5
9
12
15
20
L BOOST
(1)
Figure 11 shows the feedback circuit.
RT
The target inductance for boost mode can be
estimated with Equation (3):
(2)
Where ∆IL is the peak-to-peak inductor ripple
current, and is 30% to 50% of the maximum load
current.
In boost mode, the inductor selection is based on
limiting the peak-to-peak current ripple (∆IL)
between 30% and 50% of the maximum input
current.
IPEAK BUCK IOUT
IPEAK BOOST
VOUT (VIN(MAX) VOUT )
2 VIN(MAX) fREQ L
(4)
VOUT IOUT VIN(MIN) (VOUT VIN(MIN) )
(5)
VIN(MIN)
2 VOUT fREQ L
Where η is the estimated efficiency of the
MP28167-A.
For most applications, a 4.7µH inductor is
recommended for 500kHz switching frequency
applications, and a 3.3µH inductor is
recommended for 750kHz switching frequency
applications.
MPS inductors are optimized and tested for use
with our complete line of integrated circuits.
Table 2 lists recommended power inductors.
Table 2: Power Inductor Selection
Part Number
Inductor
Value
Select family
series (MPL-AL)
MPL-AL6050-4R7
MPL-AL6050-3R3
MPL-AL5030-2R2
2.2µH to
4.7µH
4.7μH
3.3μH
2.2μH
Manufacturer
MPS
MPS
MPS
MPS
Visit MonolithicPower.com for more information.
MP28167-A Rev. 1.0
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
Input and Output Capacitor Selection
It is recommended to use ceramic capacitors
with an electrolytic capacitor at the input to filter
the input ripple current and achieve stable
operation.
Since the input capacitor absorbs the input
switching current, it requires sufficient
capacitance. For most applications, a 100µF
electrolytic capacitor and a 22µF ceramic
capacitor are sufficient.
The output capacitor stabilizes the DC output
voltage. A sufficient capacitor value is
recommended to limit the output voltage ripple.
The minimum ceramic COUT should be 22µF x 5.
The input and output ceramic capacitors must be
placed as close as possible to the device.
PCB Layout Guidelines (11)
Efficient PCB layout is critical for stable
operation and thermal dissipation. For the best
results, refer to Figure 16 and follow the
guidelines below:
Top Layer
1. Place the ceramic CIN and COUT capacitors
close to the IC’s VIN-to-GND and OUT-toGND pins, respectively.
2. Use a large copper plane for PGND.
3. Add multiple vias to improve thermal
dissipation.
4. Connect AGND to PGND.
5. Use short, direct, and wide traces to connect
OUT.
6. Add vias under the IC and route the OUT
trace on both PCB layers (highly
recommended).
7. Use a large copper plane for SW1 and SW2.
Close-Up of Layout
Figure 16: Recommended PCB Layout
8. Place the VCC decoupling capacitor as close
to VCC as possible.
9. The FB trace requires special consideration.
Use a GND copper to cover this trace, and
route other signal traces far from FB, such as
SWx/BSTx.
Note:
11) The recommended layout is based on the Typical Application
Circuit (see Figure 17).
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MP28167-A – 22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
TYPICAL APPLICATION CIRCUITS
R6, 0Ω C4, 100nF
16
VIN = 2.8V to 22V
BST1
1
+
C1
100µF
IN
BST2
C1A
0.1µF
C1B
22µF
R3
499kΩ
SW2
3
R4
10kΩ
4
R7, 0Ω C5 100nF
13
14
VOU T = 5V
12
C2B
C2A
0.1µF 22µF
MP28167-A
ALT
FB
8
RT
806kΩ
I C Slave
VCC AGND
10
C2C
22µF
C2D
22µF
C2E
22µF
C2F
22µF
R1
430kΩ
R2
107kΩ
SCL
SDA
9
4.7µH
EN
2
5
6
C3
1µF
L1
15
OUT
C7
22nF
VCC
SW1
GND
2, 11
R5
21.5kΩ
OC
7
C6
22nF
Figure 17: Typical Application Circuit for 5V VOUT
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MP28167-A-22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
PACKAGE INFORMATION
QFN-16 (3mmx3mm)
MP28167-A Rev. 1.0
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MP28167-A-22V VIN, 3A IOUT, INTEGRATED BUCK-BOOST WITH FB FUNCTION
CARRIER INFORMATION
Pin1
1
1
ABCD
1
1
ABCD
ABCD
ABCD
Feed Direction
Part Number
Package
Description
Quantity/
Reel
Quantity/
Tube
Quantity/
Tray
Reel
Diameter
Carrier
Tape Width
Carrier
Tape Pitch
MP28167GQ-A–Z
QFN-16
(3mmx3mm)
5000
N/A
N/A
13in
12mm
8mm
Notice: The information in this document is subject to change without notice. Users should warrant and guarantee that thirdparty Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume
any legal responsibility for any said applications.
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