MP5021
The Future of Analog IC Technology
12V, 7mΩ RDSon Hot-Swap Protection
Device with Current Monitoring
DESCRIPTION
FEATURES
The MP5021 is a hot-swap protection device
designed to protect circuitry on its output from
transients on its input. It also protects its input
from undesired shorts and transients coming
from its output.
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At start up, the slew rate at the output limits the
in-rush current. An external capacitor at the SS
pin controls the slew rate.
The maximum output load is current limited using
a sense FET topology whereby a low-power
resistor from the ISET pin to ground controls the
magnitude of the current limit.
An internal charge pump drives the gate of the
power device, allowing for a power FET with a
very low ON resistance of 7mΩ.
The MP5021 includes an IMON option to
produce a voltage proportional to the current
through the power device, as set by a resistor
from the IMON pin to ground.
The MP5021 includes an optional discharge
function that provides a discharge path for the
external output capacitor when the part is
disabled. Fault protections include current-limit
protection, thermal shutdown, and damagedMOSFET detection. Both the current limit and
thermal shutdown have user-settable auto-retry
and latch-off mode. The device also features
over-voltage protection and under-voltage
protection
Integrated 7mΩ Power FET
Adjustable Current Limit (5A to 15A)
Output Current Measurement
±5% Current Limit and Monitor Accuracy
Fast Response ( VIN-1V
The power-good signal is pulled high. The
system can now draw full power.
As per Figure 4 (EN floating), the input voltage
rises immediately, and a 30Ω resistor pulls the
internal VGS voltage low .
Power-Up Sequence
For hot-swappable applications, the input of the
MP5021 can experience a voltage spike or
transient during the hot-plug procedure. This
spike is caused by the parasitic inductance of the
input trace and the input capacitor. An insertion
delay determined by the external capacitor at the
TIMER pin stabilizes the input voltage.
VIN
UVLO
40uA
When the FB voltage drops below 0.535V, the
power FET’s VGS voltage is less than a 3V or the
output voltage is less than VIN-1V, PG is switched
low.
The PG output is pulled low when either the EN
pin is below its threshold or the input
UVLO/OVLO is triggered.
With no input, the power good stays at a logic
low level in the presence of a pull-up supply.
FLTB Pin
The fault bar (FLTB) pin is an open drain output
used to indicate that a fault has occurred. Pull up
the FLTB pin to external power supply through a
100kΩ resistor.
When the device reaches its current limit, the die
temperature exceeds the thermal shutdown
threshold, or the MOSFET is shorted before
power-up, the fault output is driven low with a
10µs propagation delay. If a short occurs and the
current reaches its 25A secondary current limit,
the FLTB will switch low with an ~8μs delay.
The FLTB goes high when the MP5021 resumes
normal operation, which means the output
voltage exceeds the setting voltage of the PGrising threshold and power FET is fully ON
(VGS>3V).
External Pull-Up Voltage for PG and FLTB
The PG and FLTB need an external power
supply. The open-drain output of PG can work
well from the external pull-up voltage even when
MP5021 Rev. 1.1
1/30/2013
1.23V
TIMER
4V clamp
SS
VGS
5V
4uA gate charge
30O Pull down
VOUT
ISWITCH
PG
t1
t
Insertion Delay Time
Figure 4: Start-Up Sequence
The TIMER pin charges through a 40µA
constant-current source when the input voltage
reaches the UVLO threshold. When the TIMER
pin voltage reaches 1.23V, a 4µA current source
pulls up the power FET’s gate-source voltage.
Meanwhile, the TIMER pin voltage drops. Once
the gate voltage reaches its threshold, VGSTH, the
output voltage rises. The soft-start capacitor
determines the rise time.
Soft-Start
A capacitor connected to the SS pin determines
the soft-start time: When the insertion delay time
ends, a constant-current source that is
proportional to the input voltage ramps up the
voltage on the SS pin. The output voltage rises at
a similar slew rate to the SS voltage.
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© 2013 MPS. All Rights Reserved.
14
MP5021 – 12V, 7mΩ RDSon HOT-SWAP PROTECTION DEVICE
At the end of the blanking time, EN behaves
normally.
The SS capacitor value is given by
CSS =
5 ⋅ τSS
RSS
Set the blanking time with a capacitor connected
to the ENTM pin. The following estimates a value
for the blanking timer capacitor:
Where:
τSS=soft start time
CENB =
RSS=1MΩ
τENB ⋅ 10−6
1.23
For example, a 100nF capacitor gives a soft-start
time of 20ms.
Where:
If the load capacitance is extremely large, the
current required to maintain the preset soft-start
time will exceed the current limit. Then the load
capacitor and the current limit control the rise
time.
CENB=EN blanking time capacitor
Float the SS pin to generate a fast ramp-up
voltage. A 4μA current source pulls up the gate of
the power FET. The gate charge current controls
the output voltage rise time. The approximate
soft-start time is about 1ms, which is the
minimum soft-start time.
Enable Pin and EN Blanking Time
The EN pin enables the part when HIGH and
disables the part when low. Floating the EN pin
sets the part to auto-startup thanks to an internal
1μA pull-up current source.
V IN
EN
1.23V
TIMER
t2
1.23V
Insertion delay
ENTM
1uA
VOUT
t1
EN blanking time
t
Figure 5: EN Blanking Time
As shown in Figure 5, EN has a programmable
blanking time of up to 1s that prevents EN from
de-asserting during the blanking time. All fault
functionality continues to operative during the
start-up so that the power switch shuts down if a
fault was detected; however, the switch will not
turn off if EN goes LOW during this blanking time.
MP5021 Rev. 1.1
1/30/2013
τENB=EN blanking time
For example, a 1μF capacitor gives a blanking
time of 1.23s.
Floating the ENTM pin generates a fast ramp-up
voltage on the ENTM pin. The blanking time
during this period is negligible.
When EN enables the part, the insertion delay
timer starts. When the insertion delay time ends,
the internal 4μA current source charges the
power FET’s gate. Charging takes about 1.5ms
for VGS to reach its threshold. Then the output
voltage rises following the SS-controlled slew
rate.
Damaged MOSFET Detection
The MP5021 can detect a shorted pass FET
during power-up by treating an output voltage
that exceeds VIN-1V during power-up as a short
on the MOSFET. The FLTB pin goes low to
indicate a fault condition and the power switch
remains off. Once the VOUT≤VIN-1, the part starts
up normally.
Internal VCC Sub-Regulator
The MP5021 has an internal 5V linear subregulator that steps down the input voltage to
generate a 5V power supply that powers lowvoltage circuitry. The regulator is enabled when
VIN exceeds its UVLO threshold and EN is high.
In EN shutdown mode, the internal VCC
regulator is disabled to reduce power dissipation.
PD Pin
When the PD pin connects to the output, the part
is in pull-down mode. In this mode, when the
enable pin is low, an integrated 500Ω pull-down
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© 2013 MPS. All Rights Reserved.
15
MP5021 – 12V, 7mΩ RDSon HOT-SWAP PROTECTION DEVICE
resistor attached to the output discharges the
output. Adding a resistor between the PD pin and
the output results in a slower output drop. If the
PD pin is floating, pull-down mode is disabled.
Under/Over-Voltage Lockout
If the input supply falls below the UVLO threshold
or above the OVLO threshold, the output is
disabled and the PG pin goes low.
AUTO Pin
When the AUTO pin is floating, the part is in
auto-retry mode. In auto-retry mode, the part
turns off when it exceeds its thermal limit or
current limit timeout, and turns back on when the
part cools by 20°C or the restart timer completes.
When the supply exceeds the UVLO threshold
without exceeding the OVLO threshold, the
output is enabled and the PG line is released.
When the AUTO pin is tied to ground, the part is
in latched-fault mode. In the latched-fault mode,
a thermal fault or current limit fault latches the
output off until the enable line is toggled from low
to high or the input voltage restarts.
MP5021 Rev. 1.1
1/30/2013
Monitoring the Output Current
The IMON pin provides a voltage proportional to
the output current (the current through the power
device). Place a 100nF capacitor from IMON to
GND to smooth the indicator voltage.
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© 2013 MPS. All Rights Reserved.
16
MP5021 – 12V, 7mΩ RDSon HOT-SWAP PROTECTION DEVICE
APPLICATION INFORMATION
Setting the Current Limit (RSET)
The MP5021 current limit value should exceed
the normal maximum load current, allowing the
tolerances in the current sense value. Estimate
the current limit from the following equation:
0.6(V)
Ilimit =
× 20 × 10 4 (A)
R SET
The table below gives the bench results from the
evaluation board.
Current Limit vs. Current Limit Resistor
Current Limit Resistor (kΩ)
Current Limit (A)
7.5
15.9
10
12.1
20
6.08
RSET VS. Current Limit
20
16
14
12
10
8
6
4
2
VIN
VOUT
VIN
EN
1
ENTM
3
CT
TIMER
4
RSET
ISET
5
C SS
SS
6
GND
7
IMON
8
Ipowerfet
FLTB
9
105
R4
RMON
18 OUT
17 OUT
VIN
16 OUT
15 OUT
VIN
C OUT
14 OUT
13 OUT
VIN
12 PD
PG
FB
R2
R3
19 OUT
VIN
C3
CENTM
20 OUT
R1
2
D1
AUTO
11
C2
C1
Current Monitor
MP5021 provides a power-MOSFET-current
monitoring function. Place a resistor (RMON) to
ground to set the gain of the output as per the
following equation:
IIMON =
VIN
21
VIN
6 16 26 36 46 56 66 76 86 96
22
0
10
CURRENT LIMIT(A)
18
PCB Layout Guide
Use the following layout guidelines for the
MP5021:
1. Place the high-current paths (GND, IN, and
OUT) very close to the device using short,
direct, and wide traces.
2. Place the input capacitors as close to the IN
and GND pins as possible.
3. Place the external feedback resistors next to
the FB pin. Avoid placing any vias on the FB
trace
4. Place the Schottky diode close to the OUT
and GND pins. This Schottky diode can limit
the Vout negative excursion at the OUT pin
when the load current shuts off.
5. Connect the IN and GND pads to large
copper to achieve better thermal performance.
6. Place a small capacitor, (for example 1nF)
directly adjacent the VIN and GND pins to
minimize transients on the input supply line.
7. Put vias in the thermal pad and provide a
large copper area near the IN pin to improve
thermal performance.
Where Ipowerfet is the power MOSFET current.
GND
For example:
RMON = 100kΩ→1V/A.
Top Layer
RMON = 10kΩ→100mV/A.
MP5021 Rev. 1.1
1/30/2013
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© 2013 MPS. All Rights Reserved.
17
MP5021 – 12V, 7mΩ RDSon HOT-SWAP PROTECTION DEVICE
Design Example
VIN
The detailed application schematic is shown in
Figure 7. The typical performance and circuit
waveforms have been shown in the Typical
Performance Characteristics section. For more
detailed device applications, please refer to the
related Evaluation Board Datasheets of MP5021.
Bottom Layer
Figure 6: PCB Layout
TYPICAL APPLICATION
U1
MP5021GQV
C1C
100nF
22
VIN
GND
EN
EN
1
EN
PD
12
R3
0
PD
M P5021
G QV
C5
NS
AUTO 2
AUTO
FB
C6
1uF
C7
220nFTIMER
R7
10K
ISET 5
C8
47nF
SS
ENTM
3
4
GND
R1
180k
CN1
C2A
C2B
C2C
C2D
4.7uF
NS
NS
NS
PG
C3A
C3B
220uF
NS
D1
B330A
R2
15.4k
GND
11
FB
10
PG
R4 510K
9
Fault
R5 100K
8
IMON
ENTM
GND
VCC
VCC
TIMER
ISET
Fault
PG
Fault
SS
IMON
IMON
7
6
GND
GND1
VOUT
VOUT
20
19
18
17
16
15
14
13
1
C1B
10uF
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
VIN
2
C1A
10uF
21
1
VIN
2
VIN
35
37
39
38
40
33
34
36
29
31
32
27
28
30
23
25
26
21
22
24
17
16
19
13
15
14
18
11
12
20
7
9
5
6
EN
10
1
3
VIN
4
GND
GND
CN4
2
GND
C4
100nF
8
R6
10K
AUTO
3
2
1
VCC
CN2
GND
GND
GND
Figure 7: Typical Application Circuit with Soft Start time 10ms, Current Limit 12A
MP5021 Rev. 1.1
1/30/2013
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© 2013 MPS. All Rights Reserved.
18
MP5021 – 12V, 7mΩ RDSon HOT-SWAP PROTECTION DEVICE
PACKAGE INFORMATION
QFN22 (3x5mm)
PIN 1 ID
0.10X45?TYP
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTE:
0.10X45?
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT
INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP5021 Rev. 1.1
1/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
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