MP2884A
Digital, Multi-Phase PWM Controller
with PMBus and PWM-VID
DESCRIPTION
FEATURES
The MP2884A is a digital, multi-phase, pulsewidth modulation (PWM) controller with digital
PWM-VID interface compatible with NVIDIA’s
Open VReg specification. The MP2884A can
work with MPS’s Intelli-Phase products to
complete the multi-phase voltage regulator (VR)
solution with minimal external components. The
MP2884A can be configured with up to 4-phase
operation.
The MP2884A provides an on-chip EEPROM to
store and restore device configurations. Device
configurations and fault parameters can be
easily programmed or monitored via the
PMBus/I2C interface. The MP2884A can
monitor and report the output current through
the CS output from the Intelli-Phase products.
The MP2884A is based on a unique, digital,
multi-phase, non-linear control and provides
fast transient response to the load transient with
minimal output capacitors. With only one
power-loop control method for both steady state
and
load
transient,
the
power
loop
compensation is very easy to configure.
The MP2884A is available in a QFN-40
(5mmx5mm) package.
Programmable Multi-Phase up to Four
Phases
PWM-VID Interface Compatible with NVIDIA
Open VReg Specification
PMBus/I2C Compliant (1MHz Bus Speed)
Pin Programmable for PMBus Address
Built-In EEPROM to Store Custom
Configurations
Switching Frequency Range 200kHz to
5MHz
Automatic Loop Compensation
Fewer External Components than
Conventional Analog Controller
Best Transient Performance with NonLinear Digital Control
Flexible Phase Assignment
Auto-Phase Shedding to Improve Overall
Efficiency
Phase-to-Phase Active Current Balancing
with Programmable Offsets for Thermal
Balance
Output Voltage/Current, Input Voltage/
Power Monitoring
Regulator Temperature Monitoring
VIN UVLO, Output OVP/UVP, OCP, OTP
with No Action, Latch, Retry, or Hiccup
Mode Options
Detecting for Intelli-Phase MOSFET Fault
Type and Auto-Record to EEPROM
Register Map Password Lock
Digital Load-Line Regulation
Available in an RoHS Compliant QFN-40
(5mmx5mm) Package
APPLICATIONS
Graphic Card Core Power
Server Core Power
Telecom and Networking Systems
Base Stations
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are
trademarks of Monolithic Power Systems, Inc. or its subsidiaries.
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
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© 2018 MPS. All Rights Reserved.
1
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
TYPICAL APPLICATION
Multi-Phase Application for PWM-VID
MP2884A Rev. 1.01
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12/25/2018
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© 2018 MPS. All Rights Reserved.
2
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
ORDERING INFORMATION
Part Number*
MP2884AGU–xxxx**
Package
QFN-40 (5mmx5mm)
Top Marking
See Below
* For Tape & Reel, add suffix –Z (e.g.: MP2884AGU-xxxx–Z).
** “xxxx” is the configuration code identifier for the register settings stored in the EEPROM. Each “x” can be a
hexadecimal value between 0 and F. Please work with an MPS FAE to create this unique number.
TOP MARKING
MPS: MPS prefix
YY: Year code
WW: Week code
MP2884A: Part number
LLLLLLL: Lot number
PACKAGE REFERENCE
TOP VIEW
QFN-40 (5mmx5mm)
MP2884A Rev. 1.01
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12/25/2018
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© 2018 MPS. All Rights Reserved.
3
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
PIN FUNCTIONS
Package
Pin #
Name
Type (1)
1
TALERT#
D [O]
2
3
T1
T2
D [O]
D [O]
Open-drain VR thermal indicator. TALERT# is pulled low if the
temperature exceeds the programmed threshold from either VTEMP or
TSNS.
Test pin 1. Leave T1 floating.
Test pin 2. Leave T2 floating.
4
T3
D [O]
Test pin 3. Leave T3 floating.
5-7
8
9
10
11
NC
PWM4
PWM3
PWM2
PWM1
D [O]
D [O]
D [O]
D [O]
D [O]
No connection. Leave NC floating.
12
VDD33
Power
13 - 16
17
18
19
20
NC
CS4
CS3
CS2
CS1
A [I]
A [I]
A [I]
A [I]
A [I]
21
CSSUM
A [I]
22
VINSEN
A [I]
23
VDD18
Power
24
ADDR
A [I]
25
IMON
A [I/O]
26
IREF
A [I/O]
27
28
T4
VDIFF
A [I]
A [O]
29
VFB
A [I/O]
30
T5
A [I]
31
VOSEN
A [I]
32
VORTN
A [I]
Description
Tri-state logic-level PWM outputs. Each output is connected to the
PWM input of the Intelli-Phase. The low logic level is 0V. The high logic
level is 3.3V. The mid-state logic level is 1.5V (or high impedance). Float
PWMx if it is not being used.
3.3V power supply input. Connect a 1µF bypass capacitor from VDD33
to AGND.
No connection. Leave NC floating.
Phase 1~4 current sense input. Short CSx to AGND or CSSUM if it is
not being used.
Total phase current sensing input. CSSUM is used for load-line and
over-current protections. Connect the active phases' CS signals together
to CSSUM through the current-sense resistors.
Input voltage sensing. Place a resistor divider from the power stage
(VIN) to VINSEN.
1.8V LDO output. VDD18 provides a power supply for the internal
digital circuit. Connect a 1µF bypass capacitor from VDD18 to AGND.
PMBus address setting.
Analog total average current sensing signal. IMON sources a current
proportional to the sensed total average current from CSSUM. IMON is
used for load-current reporting.
Internal bias current set. Connect a 61.9kΩ, 1% accuracy resistor from
IREF to AGND.
Test pin 4. Short T4 to AGND.
Output of the differential remote sense amplifier.
Feedback. VFB sources a current (Idroop) proportional to the sensed
output current. This current flows through the resistor (Rdroop) between
VFB and VDIFF to create a voltage drop proportional to the load current
to achieve the load-line function.
Test pin 5. Short T5 to AGND.
Remote voltage sensing positive input. VOSEN is connected to the
VR output voltage directly at the load. Route VOSEN with VORTN
differentially.
Remote voltage sensing return input. VORTN is connected to the
ground directly at the load. Route VORTN with VOSEN differentially.
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
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© 2018 MPS. All Rights Reserved.
4
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
PIN FUNCTIONS (continued)
Package
Pin #
Name
Type (1)
Description
Thermistor thermal sensing input or boot voltage setting.
TSNS/BOOT can be programmed for either thermistor thermal sensing
or boot voltage setting.
33
TSNS/BOOT
A [I/O]
34
35
36
SDA
SCL
EN
D [I/O]
D [I]
D [I]
37
PSI
A [I]
38
PGOOD
D [O]
39
PWMVID
A [I]
40
VTEMP
A [I]
PAD
AGND
Power
When used as TSNS, the controller compares the voltage of
TSNS/BOOT to an internal programmable threshold. Once triggered,
TALERT# is asserted, and the VR enters a pre-programmed protection
mode.
When used as BOOT, a voltage divider is required from VDD18 to
TSNS/BOOT to set the boot voltage.
PMBus data.
PMBus clock.
Enable control.
Power saving interface. 1.8V logic. When PSI is 1, all phases have
forced continuous conduction mode (CCM). When PSI is 0, there is an
adjustable low-phase count. When PSI is in Hi-Z, auto-phase-shedding
is enabled.
Power good indication. PGOOD is an open-drain output. PGOOD
asserts when the output voltage is in regulation.
PWM-VID signal input. PWMVID is a 1.8V logic. Connect the PWMVID signal to PWMVID. The VR calculates the target VID based on the
duty.
Analog signal from the VR to the controller. VTEMP indicates the
maximum temperature of the power stages. The MP2884A supports
temperature sensing from the Intelli-Phase power stages. Tie all
temperature reporting pins from the Intelli-Phase together to produce
the maximum value on the VTEMP bus.
Analog ground.
NOTE:
1) A = analog, D = digital, I = input, O = output, I/O = bidirectional.
ABSOLUTE MAXIMUM RATINGS (2)
Thermal Resistance (5)
VDD33 .......................................... -0.3V to +4.0V
VDD18 .......................................... -0.3V to +2.0V
CS1~4, PWM1~4, VFB, VDIFF, VOSEN,
VORTN,
PGOOD,
PSI,
SCL,
SDA,
TSNS/BOOT, TALERT#, PWMVID, EN,
VTEMP ......................................... -0.3V to +4.0V
CSSUM, IMON, IREF, VINSEN, ADDR ..............
...................................................... -0.3V to +2.0V
Junction temperature ................................ 150°C
Lead temperature...................................... 260°C
Continuous power dissipation (3) .............. 3.47W
QFN-40 (5mmx5mm) ............. 36 ....... 5 .... °C/W
θJA
θJC
NOTES:
2) Exceeding these ratings may damage the device.
3) The maximum allowable power dissipation is a function of
the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature.
4) The device is not guaranteed to function outside of its
operating conditions.
5) Measured on JESD51-7, 6-layer PCB.
Recommended Operating Conditions (4)
Supply voltage (VIN) ...................... +3.0V to 3.6V
Operating junction temp. (TJ) ....-40°C to +125°C
MP2884A Rev. 1.01
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12/25/2018
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© 2018 MPS. All Rights Reserved.
5
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
ELECTRICAL CHARACTERISTICS
VDD33 = 3.3V, EN = 1V, current going into the pin is positive. Typical values are at TA = 25°C.
Parameter
Remote Sense Amplifier
Bandwidth (6)
Symbol
Condition
Min
GBW(RSA)
VORTN current
IVORTN
VOSEN current
IVOSEN
EN = 1V, VOSEN = 3V,
VORTN = 0V
EN = 1V, VOSEN = 3V,
VORTN = 0V
Typ
Max
Units
20
MHz
-38
μA
38
μA
1.56
MHz
Oscillator
Frequency
fOSC
System Interface Control Inputs
Enable (EN)
Input low voltage
VIL(EN)
Input high voltage
VIH(EN)
Enable high leakage
IIH(EN)
IMON Output
Current gain
Current gain accuracy
PWM-VID
Input low voltage
Input mid-state
Input high voltage
PSI
Input low voltage
Input mid-state
Input high voltage
PWM Outputs
Output low voltage
Output middle voltage
Output high voltage
Rise and fall time (6)
PWM tri-state leakage
PWM fault detection source
current (6)
TSNS
Current source
IMON/ICS_SUM
VIREF = 1.23V, RIREF = 61.9kΩ
0.4
0.8
EN = 2V
2.3
Measured from ICSSUM to IMON,
ICS_SUM = -2mA
1:16
-1
PWMVIDL
PWMHIZ
PWMVIDH
%
0.4
V
V
V
0.4
V
V
V
200
mV
V
0.9
1.4
IPWM(SINK) = 400µA
IPWM(SOURCE) = -100µA
VOH (PWM)
IPWM(SOURCE) = -400µA
C = 10pF
PWM = 1.5V, EN = 0V
ITSNS
1
1.4
VOL (PWM)
VOM (PWM)
Isource(PWM)
µA/µA
0.9
PSIL
PSIM
PSIH
Enter PWM fault detect mode
3.15
10
1.36
VDD33
-0.02
10
-1
V
V
µA
V
1
ns
µA
150
µA
10
µA
MP2884A Rev. 1.01
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12/25/2018
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© 2018 MPS. All Rights Reserved.
6
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
ELECTRICAL CHARACTERISTICS (continued)
VDD33 = 3.3V, EN = 1V, current going into the pin is positive. Typical values are at TA = 25°C.
Parameter
Comparator (Protection)
Symbol
Over-voltage threshold
Supply current
VDD33
IVDD33
UVLO threshold voltage
Min
Relative to reference DAC
voltage (2Ch bit[2:0] = 3b'001)
Relative to reference DAC
voltage (2Ch bit[2:0] = 3b'010)
Relative to reference DAC
voltage (2Ch bit[2:0] = 3b'100)
Relative to reference DAC
voltage (2Ch bit[2:0] = 3b'001)
Relative to reference DAC
voltage (2Ch bit[2:0] = 3b'010)
Relative to reference DAC
voltage (2Ch bit[2:0] = 3b'100)
Under-voltage threshold
VDD33 Supply
Supply voltage range
Condition
VDD33UVLO
VDD33UVLO
3.0
EN = high or programmed as
non-low-power mode
EN = 0 and programmed as
low-power mode
VDD33 is rising
VDD33 is falling
2.68
Typ
Max
Units
−190
mV
−310
mV
−430
mV
190
mV
310
mV
430
mV
3.3
3.6
V
30
mA
150
µA
2.88
2.80
2.98
V
V
1.8V Regulator
1.8V regulator output voltage
VDD18
1.8v regulator load capability
IVDD18
IVDD18 = 0mA
1.8
V
VOL = VDD18 - 40mV
30
mA
ADC
ADC voltage reference
ADC resolution
1.592
1.6
1.608
10
(6)
DNL(6)
Sample rate
V
bits
1
LSB
700
kHz
FSADC
1.7
V
∆ADC
6.25
mV
50
mV/μs
(6)
DAC (Reference Voltage)
DAC voltage reference
Resolution/LSB
Max output voltage slew rate
(6)
OC_DAC (Protection)
Range (6)
Resolution/LSB (6)
FSDAC_PRT
∆DAC_PRT
Adjustable via the PMBus
0.17
2.72
10
MP2884A Rev. 1.01
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12/25/2018
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V
mV
7
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
ELECTRICAL CHARACTERISTICS (continued)
VDD33 = 3.3V, EN = 1V, current going into the pin is positive. Typical values are at TA = 25°C.
Parameter
Symbol Condition
PMBus DC Characteristics (SDA, SCL)
VIH
Input high voltage
Input low voltage
Pin capacitance
Holding time
Repeated start condition setup time
Stop condition set-up time
Data hold time
Data set-up time
Clock low time-out
Clock low period
Clock high period
Clock/data fall time
Clock/data rise time
Max
1.35
-10
CPIN
PMBus Timing Characteristics (1MHz)
Operating frequency range
Bus free time
Typ
VIL
Input leakage current
(6)
Min
Units
V
0.8
V
10
μA
10
pF
1000
kHz
(7)
10
Between stop and start
condition
0.5
μs
0.26
μs
0.26
μs
0.26
0
50
25
0.5
0.26
μs
ns
ns
ms
μs
μs
ns
ns
35
50
120
120
NOTE:
6) Guaranteed by design or characterization data, not tested in production.
7) The device supports 100kHz, 400kHz, and 1MHz bus speeds. The PMBus timing parameters in this table is for operation at 1MHz. If the
PMBus operating frequency is 100kHz or 400kHz, refer to the SMBus specification for timing parameters.
MP2884A Rev. 1.01
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12/25/2018
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8
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, COUT = 6400μF, RIMON = 4.42kΩ, PGOOD is pulled up to +3.3V. TA = +25°C, unless
otherwise noted.
Steady State
Steady State
VIN = 12V, VDD1 = 0.8V, FSW = 500kHz,
4-phase CCM, IOUT = 0A
VIN = 12V, VDD = 0.8V, FSW = 500kHz,
4-phase CCM, IOUT = 60A
CH4:
VDD/AC
10mV/div.
CH4: VDD/AC
3V/div.
CH1:
PWM1
3V/div.
CH1: PWM1
3V/div.
CH2:
PWM2
3V/div.
CH2: PWM2
3V/div.
CH3:
CH3: PWM3
10mV/div.
PWM3
3V/div.
500ns/div.
500ns/div.
EN Power On
EN Soft Off
VIN = 12V, VBOOST = 0.8V, RC slew rate,
TAU = 163.84μs
VIN = 12V, VBOOST = 0.8V, RC slew rate,
TAU = 163.84μs
CH2: VEN
2V/div.
CH2: VEN
2V/div.
CH1: PWM1
3V/div.
CH1:
PWM1
3V/div.
CH4: VDD
300mV/div.
CH3: VPG
2V/div.
CH4: VDD
300mV/div.
CH3: VPG
2V/div.
200μs/div.
200μs/div.
EN Power On
EN Soft Off
VIN = 12V, VBOOST = 0.8V, linear slew rate,
SR = 1.98mV/μs
VIN = 12V, VBOOST = 0.8V, linear slew rate,
SR = 1.98mV/μs
CH2: VEN
2V/div.
CH2: VEN
2V/div.
CH1: PWM1
3V/div.
CH1:
PWM1
3V/div.
CH4: VDD
300mV/div.
CH4: VDD
300mV/div.
CH3: VPG
2V/div.
CH3: VPG
2V/div.
200μs/div.
200μs/div.
MP2884A Rev. 1.01
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12/25/2018
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9
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, COUT = 6400μF, RIMON = 4.42kΩ, PGOOD is pulled up to +3.3V. TA = +25°C, unless
otherwise noted.
DVID Up
DVID Down
DVID from 0.4V to 1.2V, RC slew rate,
TAU = 18.2μs
DVID from 1.2V to 0.4V, RC slew rate,
TAU = 18.2μs
CH4: VDD
400mV/div.
CH3:
PWMVID
3V/div.
CH4: VDD
400mV/div.
CH3:
PWMVID
3V/div.
CH1: PWM1
3V/div.
CH1:PWM1
3V/div.
CH2: VPG
3V/div.
CH2: VPG
3V/div.
20μs/div.
20μs/div.
DVID Up
DVID Down
DVID from 0.4V to 1.2V, linear slew rate,
SR = 9.62mV/μs
DVID from 1.2V to 0.4V, linear slew rate,
SR = 9.62mV/μs
CH4: VDD
400mV/div.
CH3:
PWMVID
3V/div.
CH4: VDD
400mV/div.
CH3:
PWMVID
3V/div.
CH1:PWM1
3V/div.
CH1:PWM1
3V/div.
CH2: VPG
3V/div.
CH2: VPG
3V/div.
20μs/div.
20µs/div.
Load Transient with DC Load Line
Load Transient with AC Load Line
VIN = 12V, VDD = 1V, FSW = 500kHz,
RLL = 0.5mΩ, IOUT = 0 150A @ 500A/µs
VIN = 12V, VDD = 1V, FSW = 500kHz,
RLL = 0mΩ, IOUT = 0 150A @ 500A/µs
CH3:
VIOUT
(4mV/A)
500mV/div.
CH3: VIOUT
(4mV/A)
500mV/div.
CH4: VDD
50mV/div.
CH4: VDD
50mV/div.
CH1: PWM1
3V/div.
CH1: PWM1
3V/div.
CH2: PWM2
3V/div.
CH2:
PWM2
3V/div.
50µs/div.
50µs/div.
MP2884A Rev. 1.01
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12/25/2018
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10
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, COUT = 6400μF, RIMON = 4.42kΩ, PGOOD is pulled up to +3.3V. TA = +25°C, unless
otherwise noted.
PSI Changes between High and Low
PSI Changes between High- and
Middle-State
Enable APS, low phase count = 1, IOUT = 20A
(2-phase running according to APS levels)
Enable APS, low phase count = 1, IOUT = 20A
(2-phase running according to APS levels)
CH4: PSI
1V/div.
CH4: PSI
1V/div.
CH1: PWM1
3V/div.
CH1: PWM1
3V/div.
CH2:
PWM2
3V/div.
CH2: PWM2
3V/div.
CH3:
PWM3
3V/div.
CH3: PWM3
3V/div.
50µs/div.
50µs/div.
OVP
UVP
VIN = 12V, VDD = 1V, OVP delay time = 0.5µs,
latch-off mode
VIN = 12V, VDD = 1V, UVP delay time = 400µs,
latch-off mode
CH4: VDD
300mV/div.
CH4: VDD
300mV/div.
CH3:
CS1/os=1.23V
400mV/div.
CH3:
CS1/os=
1.23V
400mV/div.
CH1: PWM1
3V/div.
CH2: VPG
3V/div.
CH1: PWM1
3V/div.
CH2: VPG
3V/div.
10µs/div.
500µs/div.
OCP
OTP
VIN = 12V, VDD = 1V, OCP threshold = 500A,
check time = 200µs, latch-off mode
VIN = 12V, VDD = 1V, TJ = (100°C/V) * VTEMP +
10°C, OTP threshold = 120°C, latch-off mode
CH4: VDD
400mV/div.
CH4: VDD
400mV/div.
CH3:
Vlmon
(2.34mV/A)
500mV/div.
CH3:VTEMP
500mV/div.
CH1: PWM1
3V/div.
CH2: VPG
3V/div.
CH1: PWM1
3V/div.
CH2: VPG
3V/div.
50µs/div.
5ms/div.
MP2884A Rev. 1.01
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11
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
BLOCK DIAGRAM
Figure 1: System Functional Block
MP2884A Rev. 1.01
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12/25/2018
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12
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
OPERATION
The MP2884A is a single-output, digital, multiphase voltage regulator (VR) controller for highperformance GPU or CPU. It supports PWMVID’s controllable VOUT reference and is
compliant
with
NVIDIA’s
Open
VReg
specification.
The MP2884A uses MPS’s unique loop
compensation strategy to balance and optimize
steady and transient performance. It also
adopts adaptive phase-shedding and phaseadding strategies to optimize the overall VR
efficiency according to the load current.
The MP2884A contains precision DAC and
ADC, differential remote voltage sense amplifier,
fast comparators, current-sense amplifiers,
internal slope compensation, digital load-line
setting, power good monitor, and temperature
monitor.
The MP2884A provides rich programmable
functions with the PMBus 1.3 interface. On-chip
EEPROM is flexible for storing custom
configurations and auto-records the fault type
when a protection occurs.
Fault protection features include VIN undervoltage lockout (UVLO), VIN over-voltage
protection (OVP), VOUT OVP, VOUT undervoltage protection (UVP), VOUT reverse-voltage
protection (RVP), output over-current protection
(OCP), and over-temperature protection (OTP).
PMBus-programmable functions include phase
assignment, switching frequency, reference
voltage, loop stability parameters, protection
thresholds and behaviors, load-line parameters,
and so on.
The MP2884A can also detect the fault type of
the Intelli-Phase when a protection occurs. The
MP2884A can record all faults into the
EEPROM automatically in case the power
supply shuts off while the fault is occurring.
The MP2884A system state machine is shown
in Figure 2.
Figure 2: System State Machine
PWM Control and Switching Frequency
The MP2884A applies MPS’s unique digital
pulse-width modulation (PWM) control to
provide fast load transient response and easy
loop compensation. The switching frequency
can be set with the PMBus command MFR_FS
(BDh).
The PWM on time of each phase updates in
real time according to the input voltage, output
voltage, and the phase switching frequency
adaptively. TON can be calculated with Equation
(1):
Ton
VOUT 1
VIN Fs
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(1)
13
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Where VOUT is the real-time output voltage
reference, VIN is the input voltage, and FS is the
switching frequency set by the PMBus.
Voltage Reference
The MP2884A has an 8-bit VID-DAC, which
provides the reference voltage (VREF) for the
individual output. VREF is in a VID format with
6.25mV per step. The relationship between
VREF and the VID value in decimals is shown in
Equation (2):
VREF (V) VID 0.000625
(2)
When setting the unit gain for the differential
voltage sense amplifier and VID is higher than
256, VREF is limited to 1.6V.
When setting the half gain for the differential
voltage sense amplifier, VREF can range from 0
~ 3.19375V.
Output Voltage Setting and Sensing
In PMBus-VID control mode, the desired output
voltage can be set by the PMBus command
VOUT_COMMAND (21h). VOUT_COMMAND
(21h) is a 9-bit register in a VID format with
6.25mV per step. The output setting range is 0
~ 3.19375V.
N
I
M
D
I
V
M
W
P
D
I
V
D
N
I
M
D
I
V
X
A
M
D
I
V
D
I
V
In PWM-VID control mode, the desired output
voltage can be set according to Equation (3):
(3)
Where VIDMAX is the maximum voltage setting,
VIDMIN is the minimum voltage setting, and
DPWMVID is the duty of the PWM-VID signal.
The voltage at the load is sensed with the
differential voltage sense amplifier. This type of
sensing provides better load regulation.
The
MP2884A
provides
high-resolution
trimming and digital DC calibration for high
output voltage regulation accuracy. With a unit
gain of the differential voltage amplifier, the
VOUT regulation accuracy is within ±1.5625mV.
With a half-gain of the differential voltage
amplifier, the VOUT regulation accuracy is within
±3.125mV.
Active Voltage Positioning (AVP)
The MP2884A supports active voltage
positioning (AVP) by connecting a droop
resistor (RDROOP) between VDIFF and VFB. With
this function, the output voltage drops gradually
as the load current increases. This is also
known as load-line regulation. The relationship
of the output voltage and load current is shown
in Equation (4):
VOUT @IOUT VOUT @NO LOAD IOUT RLL
(4)
Where RLL is the equivalent load-line resistor.
The
MP2884A
provides
a
PMBusprogrammable load line. The final load-line
value is determined by RDROOP and the value in
the register IDROOP_SET (1Eh). The load-line
calculation is shown in Equation (5):
ID R O O P _ S E T 4
R LL
K C S R D R O O P (5)
64
Where IDROOP_SET is the value in register
MFR_IDROOP_CTRL (1Eh), and KCS is the
current sense gain of the power stage.
IDROOP_SET ranges from 1 ~ 15. When
setting IDROOP_SET = 0, the AVP function is
disabled.
When setting a half-gain for the differential
voltage sense amplifier, the RLL value in
Equation (5) should be doubled.
For
non-AVP
VR
applications,
it
is
recommended to enable the AC droop function
via register AC_DROOP_EN (1Eh) to increase
the phase margin of the loop regulation. The
AC droop function can inject the AC current of
the total inductor current to RDROOP to introduce
the current ripple signal to the loop regulation.
Boot Voltage Setting
In PMBus-VID control mode, the MP2884A can
pre-program the boot voltage (VBOOT) either by
register VOUT_COMMAND (21h) or by
TSNS/BOOT. Figure 3 shows the connection
for the pin-programmed VBOOT.
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Table 1b: Pin-Strap Boot Voltage Table 2
Figure 3: Circuit of Pin-Strap Boot Voltage
Table 1a and Table 1B show four options for
the TSNS/BOOT pin-programmed VBOOT.
Table 1: Pin-Strap Boot Voltage Table 1
TSNS/BOOT Boot Voltage (V) Boot Voltage (V)
(0.2V/step)
(0.1V/step)
Voltage Point
45h bit[1:0] = 00 45h bit[1:0] = 10
(V)
0.05
0.15
0.25
0.35
0.45
0.55
0.65
0.75
0.85
0.95
1.05
1.15
1.25
1.35
1.45
1.55
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
The boot-up linear slew rate is set via register
MFR_BOOT_SR (B9h) and ranges from 0.12 125mV/µs, as shown in Equation (6):
S lew R ate
6.25m V
(6)
M FR _ B O O T _ S R 0.05 s
In PWM-VID control mode, VBOOT can only be
set by the register MFR_VBOOT (BBh). When
PWM-VID is in mid-state, the VR output slews
to the boot voltage.
There are two boot-up slewing modes for PWMVID control mode: R-C filter mode and linear
mode.
TSNS/BOOT Boot Voltage (V) Boot Voltage (V)
(0.1V/step)
Voltage Point (0.05V/step)
45h bit[1:0] = 01 45h bit[1:0] = 11
(V)
0.025
0
0
0.075
0.05
0.1
0.125
0.1
0.2
0.175
0.15
0.3
0.225
0.2
0.4
0.275
0.25
0.5
0.325
0.3
0.6
0.375
0.35
0.7
0.425
0.4
0.8
0.475
0.45
0.9
0.525
0.5
1
0.575
0.55
1.1
0.625
0.6
1.2
0.675
0.65
1.3
0.725
0.7
1.4
0.775
0.75
1.5
0.825
0.8
1.6
0.875
0.85
1.7
0.925
0.9
1.8
0.975
0.95
1.9
1.025
1
2
1.075
1.05
2.1
1.125
1.1
2.2
1.175
1.15
2.3
1.225
1.2
2.4
1.275
1.25
2.5
1.325
1.3
2.6
1.375
1.35
2.7
1.425
1.4
2.8
1.475
1.45
2.9
1.525
1.5
3
1.575
1.55
3.1
The boot-up R-C filter time constant is set with
register MFR_PARM_RC_CONST (B5h) and
ranges from 10.40 - 655.36µs, as shown in
Equation (7):
RC s
0 .3 2 s
211
BOOT _ RC
(7)
Where BOOT_RC is the value in register
MFR_PARM_RC_CONST (B5h).
The boot-up linear slew rate is set with register
MFR_BOOT_SR (B9h) and ranges from 0.12 125mV/µs (see Equation (6)).
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Dynamic Voltage Identification (DVID)
The MP2884A supports dynamical output
voltage transition by changing VID via the
PMBus commands or the duty of the PWM-VID
signal.
The DVID process is active after VOUT is settled
and can be either upward or downward.
In PMBus-VID control mode, the DVID linear
slew rate is set with register MFR_DVID_SR
(BAh) and ranges from 0.12 - 125mV/µs, as
shown in Equation (8):
S le w R a te
6 .2 5 m V
(8)
M F R _ D V ID _ S R 0 .0 5 s
There are two slew rate modes in PWM-VID
control mode: R-C filter mode and linear mode.
Inductor Current Sensing
The MP2884A works with the Intelli-Phase for
inductor current sensing (see Figure 4). The
voltage on CSs is sampled, calculated, and
stored in the registers. The results are used for
multi-phase current balancing and thermal
balancing and can be monitored via the PMBus.
The MP2884A provides cycle-by-cycle perphase current limitation.
The resistor (RCS) is connected from
CSSUM. CSSUM is a 1.23V constant
and can sink or source current to
voltage shifts that meet the operating
range of CSs.
CSx to
voltage
provide
voltage
Short any unused CSx pin to AGND or CSSUM.
The DVID R-C filter slew rate is set with register
MFR_PARM_RC_CONST (B5h) and ranges
from 10.40 - 655.36µs, as shown in Equation
(9):
RC s
0 .3 2 s
211
D V ID _ R C
(9)
Where DVID_RC is the value in register
MFR_PARM_RC_CONST (B5h).
The DVID linear slew rate is set with register
MFR_DVID_SR (BAh) and ranges from 0.12 125mV/µs (see Equation (8)).
VID Offset
The MP2884A supports two types of VID offset.
︳
X
A
M
S
C
V
V
3
2
.
1
S
C
S
C
R
K
D
A
O
IL
︳
N
I
M
S
C
The second type is fine-tune offset for the VID
set point, which ranges from -31.5mV to
31.5mV with 0.5mV of resolution at a unity gain
of the differential voltage sense amplifier and
ranges from -50.4mV to 50.4mV with 0.8mV of
resolution at a half-gain of differential voltage
sense amplifier. Refer to the register map
MFR_RSAMP_OFFSET (2Dh) section on page
44 for details.
Different types of Intelli-Phase products have
different operating voltage ranges for CS
(VCS_MIN and VCS_MAX). Refer to each IntelliPhase’s datasheet to determine the minimum
and maximum operating voltage ranges.
Calculate a proper RCS value with Equation (10):
V
The first type is VID step offset, which ranges
from -0.69375V to 0.7V with 6.25mV of
resolution. When the PMBus writes a new offset
to register VOUT_OFFSET (23h), the VR
ramps with the slew rate shown in Equation (8).
Figure 4: Phase Current Sense
(10)
By working with the Intelli-Phase, the MP2884A
does not need temperature compensation and
impendence matching compared with traditional
DCR sensing to achieve an accurate current
sense.
Total Current Sensing
The total current is summed from CSSUM, and
a 1/16 proportional current emerges to IMON.
Connect a resistor from IMON to AGND to
generate a voltage proportional to the output
current. The IMON voltage is sampled,
calculated, and stored in the registers. This
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
result is used for total OCP, auto-phase
shedding, and output power calculation and can
be monitored via the PMBus.
If the auto-phase-shedding function is enabled,
the total current report is used to determine the
real-time phase number.
︳
t
e
s
f
f
O
N
I
A
G
I
G
I
D
︳
4
2
0
1
︳
5
0
2
n
i
Ma
I
R
G
tT
u
o
I
N
O
M
I
R
F
M
Table 2: Phase Mode Definition
PSI Pin
Mode
High
High-phase count
Hi-Z
Auto-power mode
Low
Low-phase count
E
S
N
E
Power Mode
To improve efficiency over the entire load range,
the MP2884A supports automatic phase
shedding and adjustable high/low phase count
with PSI (see Table 2).
T
R
O
P
E
Where IOUT is the load current, KCS is the current
sense gain of the Intelli-Phase, and RIMON is the
value of the resistor connected from IMON to
ground.
tS
u
o
I
(11)
tR
u
o
I
N
O
M
RI
T
U
N
O
M
VI
I O6
1
S
KC
The voltage at IMON can be calculated with
Equation (11):
M
I
R
In Figure 5, the MFR_IMON_DIGI_GAIN
register (2Fh) is used to fine-tune the ADC
sense value with 0.1% resolution. The
IOUT_CAL_GAIN register (38h) converts the
sensed and trimmed IMON voltage to an
ampere format with 0.25A/LSB. The detailed
calculation of the register value is provided in
the MP2884A application note and register map.
tT
u
o
I
The MP2884A provides a user-programmable
scaling factor and a user-programmable current
offset. The programmable parameters allow
users to match the IMON scaling to the design’s
voltage regulator tolerance band (VRTOB)
calculation. This provides the most accurate
current reporting across the entire load range
and maximizes the performance of the
processor turbo. The scaling factor can also be
reduced or offset to under-report the total
current to the system for higher performance.
Figure 5 shows the MP2884A IMON sense and
report block diagram.
Figure 5: Current Sense and Report
In high-phase count mode, the VR is forced to
operate with a full-phase count configured in
register MFR_VR_CONFIG (E1h).
In low-phase count mode, the VR is forced to
operate with a low-phase count configured in
register MFR_LOW_PHASE _CNT (AAh).
In auto-power mode, the VR can be optimized
to adjust the phase count according to the realtime sensed load current.
As shown in Figure 6, using 4-phase as an
example, the VR works at 4-phase continuous
conduction mode (CCM) at heavy loads, and 1phase CCM at light loads to optimize efficiency.
The VR enters 1-phase discontinuous
conduction mode (DCM) at extremely light
loads reduce the switching loss further.
The APM function is implanted by comparing
the sensed load current with each power state
current threshold. The MFR_APS_LEVEL
(E3h~E7h) registers set the power state
dropping thresholds. The hysteresis is set with
register MFR_APS_HYS (E8h) to prevent the
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
converter from changing the power state backand-forth at a steady load current. Figure 7
shows the APM current thresholds setting from
1-phase CCM to 1-phase DCM.
1. DVID makes the controller run in full-phase
CCM. After the output voltage is settled to
the target value, the VR resumes APM.
2. Load step-up causing a VFB window trip
triggers full-phase CCM to reduce the
output voltage undershoot.
3. Load step-up causing the frequency to
change exceeds a programmable threshold
and triggers full-phase CCM.
Figure 6: APM Function Diagram at 4-Phase
Mode
Current Balance and Thermal Balance
The MP2884A provides a current balance loop
to achieve fair current sharing at multi-phase
mode, since different circuit impedances lead to
difference phase currents.
The phase current is sensed and calculated
with the current reference in the current loop.
Each phase’s PWM on time is adjusted
individually to balance the currents accordingly.
Figure 7: APM Threshold Setting between 1Phase DCM and 1-Phase CCM
Table 3 lists the phase shedding and adding
entry conditions based on the current report for
4-phase applications.
Table 3: Phase Shedding/Adding Based on
Current Report for 4-Phase Applications
Condition
Phase Number
MFR_3PH_LOW + MFR_APS_HYS
4-Ph CCM
< ILOAD
MFR_2PH_LOW + MFR_APS_HYS
3-Ph CCM
< ILOAD ≤MFR_3PH_LOW
MFR_1PH_LOW + MFR_APS_HYS
2-Ph CCM
< ILOAD ≤MFR_2PH_LOW
MFR_DCM_LOW + MFR_APS_HYS
1-Ph CCM
< ILOAD ≤MFR_1PH_LOW
ILOAD ≤ MFR_DCM_LOW
1-Ph DCM
In addition to the sensed output current
comparison, the MP2884A provides three
conditions (listed below) to exit APM
immediately and run in full-phase CCM to
accelerate the load transient response and
reduce the output voltage undershoot.
The MP2884A applies Σ-∆ modulation and
delay line-loop technology in the currentbalance modulation to increase the resolution of
the function and reduce PWM jitter greatly. The
time resolution of the digital system is 5ns. By
applying Σ-∆ modulation technology, the digital
PWM resolution can be increased to 0.08ns.
Each current balance loop can also include a
programmable phase current offset to achieve
thermal balance among the phases. For
example, a phase can have a greater cooling
capability due to proximity to the airflow, which
allows it to take more phase current by
increasing the phase current reference with the
offset to keep the phase thermal more balanced.
The bandwidth of the current proportionalintegral (PI) loop is relatively lower than the
output voltage feedback loop, so it barely
impacts the output voltage.
Input Voltage Sensing
The input power supply voltage is sampled at
VINSEN with a resistor divider (see Figure 8).
The sensed input voltage is used for PWM ontime calculation, VIN_UVLO, VIN_OVP fault
protection, VIN_UV warning, and input voltage
monitoring.
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
In designs, the divided voltage on VINSEN
should not exceed the ADC sampling range
(1.6V) at the maximum input voltage. A 1 10nF ceramic capacitor from VINSEN to AGND
is recommended as an input sense filtering
capacitor (CIN) (see Figure 8).
Program the input voltage sensing divider ratio
with register MFR_VIN_SCALE_LOOP (C0h).
The calculation of the ratio (KIN) is shown in
Equation (12):
KIN
RIN2
RIN1 RIN2
VIN _ SCALE _ LOOP
210
(12)
Where VIN_SCALE_LOOP is the decimal value
in the register MFR_VIN_SCALE_LOOP (C0h).
In designs, match the resistor setting (KIN) and
register setting value for accurate input voltage
sensing.
CTEMP is a VTEMP pin filtering capacitor
(recommend to be a 10nF ceramic capacitor).
RTEMP is a discharging resistor when the
junction temperature is falling (ranging from 10 49.9kΩ).
The VTEMP pin of the Intelli-Phase reports a
voltage proportional to the junction temperature.
Set the calculation gain and offset in register
MFR_TEMP_GAIN_OFFSET (C1h).
An example of the Intelli-Phase VTEMP voltage
is shown in Equation (13):
TJUNCTION(C) 100 VTEMP (V) 10
for TJUNCTION 10C
(13)
If VTEMP is 700mV, then the junction
temperature of the Intelli-Phase is 80°C. Since
VTEMP cannot go below 0V, it reads 0V when
the junction temperature is lower than 10°C.
Refer to the datasheet of the Intelli-Phase for
more information.
Temperature Sense of the Thermistor
The MP2884A senses the external thermal
component’s temperature by connecting a
thermistor to TSNS (see Figure 10). The
sensed temperature is used for overtemperature fault protection and overtemperature warning (assert TALERT#).
Figure 8: Input Voltage Sense Connection
Temperature Sense of Intelli-Phase
The MP2884A senses the Intelli-Phase’s
temperature by connecting the Intelli-Phase’s
VTEMP pin to the MP2884A’s VTEMP pin (see
Figure 9). The sensed temperature is used for
over-temperature
fault
protection,
overtemperature warning (assert TALERT#), and
power stage temperature monitoring.
Figure 10: Temperature Sense with Thermistor
TSNS sources a 10µA current source to the
thermistor, and the MP2884A senses the
voltage of TSNS. The 10µA current source can
be disabled via register TSNS_CURRENT_DIS
(34h bit[10]), and a voltage signal can be
connected to TSNS as a new defined protection
function.
Note that if the 10µA current source is enabled,
TSNS cannot be floated.
Figure 9: Temperature Sense with Intelli-Phase
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
EEPROM Operation
The MP2884A provides an EEPROM to store
custom configurations. A 4-digit part number
suffix is assigned for each application. The
default configuration for each 4-digit part can be
pre-programmed at the MPS factory. The data
can be programmed again using the
STORE_USER_ALL (15h) command via the
PMBus and requires 200ms of time for the data
to be stored to the EEPROM. The EEPROM is
read automatically during the power-on
sequence or by the RESTORE_USER_ALL
(16h) command via the PMBus and requires at
least 300µs of time for data to be restored from
the EEPROM.
The operation to the EEPROM can be
accomplished easily with the MPS GUI software.
The MP2884A uses register DBh to enable
EEPROM write protection.
The EEPROM can be erased or written for
more than 100,000 cycles. When the EEPROM
is write-protected, the write into EEPROM
action is ineffective.
EEPROM Fault
If the data from the EEPROM is checked as
invalid by the cyclic redundancy code (CRC)
during the system initialization process, the
system enters an EEPROM fault state without
outputting power and waits for the error clear
command. The configuration from the EEPROM
is ignored.
There are three ways to clear the EEPROM
fault and start up again with the restored value
from the EEPROM:
1. Clear the EEPROM fault via the PMBus
command (FFh).
2. Clear the fault status via the PMBus
command (03h).
3. Store the configuration into the EEPROM
and restart.
Low-Power Mode
The MP2884A can be programmed to operate
in regular-power mode or low-power mode.
In
regular-power
mode,
the
PMBus
communication is available when EN is low.
With low-power mode enabled, when EN is low,
the PMBus communication is disabled, and the
quiescent current (IQ) can be reduced to 150µA.
Low-power mode is factory-programmable.
Power-On
The MP2884A is supplied by a +3.3V voltage at
VDD33. VDD33 provides the bias supply for the
analog circuit and internal 1.8V LDO. The 1.8V
LDO produces the +1.8V supply for the digital
circuit. The system is reset by the internal
power-on reset signal (POR) after the VDD33
supply is ready. If the MP2884A is in regularpower mode, EN must be high. After the system
exits POR, the data in the EEPROM is loaded
into the operating registers to configure the VR
operation.
Figure 11a shows the power-on sequence of
the MP2884A in regular-power mode.
t0~t1: at t0, VDD33 is supplied by a +3.3V
voltage and reaches the VDD33 UVLO_ON
threshold at t1. VDD18 reaches +1.8V when
VDD33 is higher than 1.8V.
t1~t2: at t1, the data in the EEPROM starts
loading into the operating registers. The entire
EEPROM copy process takes about 300µs,
typically. During this stage, the PMBus address
is detected if the voltage on ADDR is selected
to set the PMBus address.
t2~t3: at t2, after the EEPROM copy is finished,
the MP2884A waits for EN to pull high. The
PMBus is available at this stage.
t3~t4: when EN is high, if the PMBus command
OPERATION (01h) is pre-set to an off state.
The MP2884A halts at this stage and waits for
the OPERATION on command. If OPERATION
(01h) is pre-programmed to an on state, the
turn-on delay time (TON delay) begins counting.
The TON delay is PMBus-programmable from 0
to 3276.75ms with the command TON_DELAY
(60h).
t4~t5: when the TON delay time expires, the VIDDAC starts ramping up VREF and a programmed
slew rate to the boot-up voltage. During soft
start, OCP_Total, OVP, and UVP are masked
until VREF reaches the target value.
In PWM-VID mode, before t5, PWM-VID should
remain at a Hi-Z state.
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Figure 11a: MP2884A Power-On Sequence at Regular-Power Mode
Figure 11b shows the power-on sequence of
the MP2884A in low-power mode.
t0~t1: at t0, VDD33 is supplied by a +3.3V
voltage and reaches the VDD33 UVLO_ON
threshold at t1. VDD18 reaches +1.8V when
VDD33 is greater than 1.8V.
t1~t2: after t1, VDD33 rises above the
UVLO_ON threshold, and the MP2884A waits
for EN to pull high. The PMBus is unavailable at
this stage.
t2~t3: at t2, EN pulls high, the data in the
EEPROM starts loading into the operating
registers. The entire EEPROM copy process
takes about 300µs, typically. During this stage,
the PMBus address is detected if the voltage on
ADDR is selected to set the PMBus address.
t3~t4: after the EEPROM copy is finished, if the
PMBus command OPERATION (01h) is pre-set
to an off state. The MP2884A halts at this stage
and waits for an OPERATION on command. If
OPERATION (01h) is pre-programmed to an on
state, the turn-on delay time (TON delay) begins
counting. The TON delay is PMBusprogrammable from 0 to 3276.75ms with the
command TON_DELAY (60h).
t4~t5: when the TON delay time expires, the VIDDAC starts ramping up VREF with a programmed
slew rate to the boot-up voltage. During soft
start, OCP_Total, OVP, and UVP are masked
until VREF reaches the target value.
In PWM-VID mode, before t5, PWM-VID should
remain at Hi-Z.
Figure 11b: MP2884A Power-On Sequence at Low-Power Mode
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Power-Off
The MP2884A can be powered off by the
OPERATION command, EN, or VDD33.
1. OPERATION command off: The MP2884A
provides Hi-Z off and soft off with
commands. During soft off, VOUT drops
down with a pre-programmed slew rate in
register MFR_BOOT_SR (B9h) until VREF
reaches the level of register MFR_VID_SD
(BCh) and then enters Hi-Z off. This
prevents VOUT from becoming negative
during the shutdown process. A turn-off
delay can be set via register TOFF_DELAY
(64h).
2. EN off: The MP2884A provides Hi-Z off and
soft-off when EN is pulled low in regularpower mode. During soft off, VOUT drops
down with a pre-programmed slew rate in
register MFR_BOOT_SR (B9h) until VREF
reaches the level of register MFR_VID_SD
(BCh) and then enters Hi-Z off. This
prevents VOUT from becoming negative
during the shutdown process. A turn-off
delay can be set via TOFF_DELAY (64h).
In low-power mode when EN is pulled low,
the MP2884A can enter Hi-Z off without any
turn-off delay immediately, and enters
standby mode with the smallest amount of
power consumption.
3. VDD33 power-off: When the voltage on
VDD33 falls below the UVLO threshold, the
MP2884A powers off immediately. All
PWMs enter Hi-Z.
Figure 12a shows the EN soft-off power
sequence in regular-power mode.
Figure 12b shows the EN Hi-Z off power
sequence in low-power mode.
Figure 12a: MP2884A Power-Off Sequence in Regular-Power Mode
Figure 12b: MP2884A Power-Off Sequence in Low-Power Mode
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Power Good Indication (PGOOD)
The MP2884A power good (PGOOD) on/off
thresholds are programmable via POWER_
GOOD_ON (5Eh) and POWER_GOOD_OFF
(5Fh).
VFB Window
The MP2884A has a feedback voltage (VFB)
window (VREF ± 25mV), which provides an
advanced non-linear loop control to fasten the
transient performance.
During the soft-start process, when VREF rises
above the POWER_GOOD_ON threshold, the
MP2884A starts a delay counter before
asserting PGOOD. The delay counter time is
programmable via register MFR_DELAY_SET
(5Dh).
When VFB is higher than VREF + 25mV (VFB
positive window limit), all PWMs pull low and
blank the PWM set signal until VFB falls below
the positive limit. The VFB positive window is
used to reduce the output voltage overshoot at
the load release, typically, especially in multiphase operation.
During the soft-shutdown process, when VREF
falls below the POWER_GOOD_OFF threshold,
the MP2884A de-asserts PGOOD immediately.
The POWER_GOOD_OFF threshold must be
set below the VID value, which is regulated
during the normal operation process.
When VFB is lower than VREF - 25mV (VFB
negative window limit), VR exits auto-power
mode immediately and enters full-phase
running to improve the transient response.
For Hi-Z shutdown caused by protections or EN
turning off, PGOOD is de-asserted immediately.
Figure 13 shows the power good indication in
regular-power mode.
Figure 13: MP2884A Power Good On/Off Sequence in Regular-Power Mode
Fault and Protections
The MP2884A supports the following fault
monitoring and protections.
VIN UVLO and OVP
The VR can shut down immediately by forcing
the PWM signals into tri-state if the sensed
input voltage is below the VIN_OFF threshold.
The VR restarts when the sensed input voltage
is above the VIN_ON threshold. The VIN UVLO
threshold is programmable with register
VIN_ON (35h) and VIN_OFF (36h) with
0.125V/LSB.
VR latches if the input voltage is above the VIN
OVP threshold, which is set with register
VIN_OV_FAULT_LIMIT (55h).
Over-Current Protection (OCP)
OCP applies a dual OCP mechanism with two
types of thresholds.
The first OCP type, OCP_Total, is a time- and
current-based threshold. The PMBus sets the
OCP_Total threshold using MFR_OCP_TOTAL
(ECh). OCP_Total should trigger when the
sensed average output current exceeds the
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
threshold for a period of time referred to as the
OCP blanking time. OCP_Total can be
programmed to no action, hiccup, retry six
times, and latch-off mode via the PMBus.
The controller does not take action in no action
mode and keeps the PWMs switching. The fault
indication bit in register STATUS_IOUT (7Bh)
and STATUS_WORD (79h) is not set in no
action mode.
In hiccup mode, the controller forces the PWM
signals into tri-state to disable the output. The
controller attempts to restart after 12.5ms of
protection delay time.
In retry six times mode, the VR hiccups six
times at most. If the fault is removed within the
six restarts, the VR resumes normal operation.
If the fault remains after the six restarts, the VR
shuts down until a new power cycle, an EN
toggle, or a PMBus COMMAND ON occurs.
In latch mode, the VR shuts down until a new
power cycle, an EN toggle, or a PMBus
COMMAND on occurs.
These four protection types are also available
for VOUT UVP and VOUT OVP2.
The second OCP type, OCP_Phase, is a
current-based
limitation
threshold.
The
MP2884A monitors the phase current cycle-bycycle. When the phase current exceeds the
OCP_Phase threshold at the PWM off time, the
PWM remains low to discharge the inductor
current. If the load current continues rising, the
output voltage drops because the inductor
current is limited. OCP_Phase is implemented
with VOUT UVP, generally. The OCP_Phase
threshold is PMBus-programmable with register
MFR_OCP_PHASE (EDh).
Under-Voltage Protection (UVP)
The MP2884A monitors the VDIFF voltage to
provide UVP and uses a dual UVP approach.
The first UVP type, UVP1, is a digital UVP.
UVP1 is triggered when the internal ADC
senses that the VDIFF voltage is lower than the
threshold for a pre-set blanking time. The UVP1
threshold can be set from 0 - 480mV with 32mV
of
resolution.
Refer
to
the
register
MFR_SYS_CONFIG (44h) section on page 54.
The second UVP type, UVP2, is triggered when
the VDIFF voltage is lower than the threshold
for a pre-set blanking time. The register
OVUV_LEVEL (2Ch) can program the UVP2
threshold to VREF - 430mV, VREF - 310mV or
VREF - 190mV. Refer to the MFR_OVUV_SEL
(2Ch) section on page 44. When programming
the gain of the differential voltage sense
amplifier as half, the UVP2 threshold is doubled.
For example, set the register to a -430mV level
to achieve the VREF - 860mV threshold.
The UVP scheme is the same as the
OCP_Total protection scheme. When the
VDIFF voltage is lower than the UVP threshold
for a given amount of time (UVP blanking time),
the controller forces the PWM signals into tristate to disable the output. The register
MFR_OVP_UVP_SET (EEh) sets the UVP
mode and blanking time. Like the OCP_Total
protection scheme, the UVP scheme also
provides no action, hiccup, retry six times, and
latch-off options.
Over-Voltage Protection (OVP)
The MP2884A monitors the VDIFF voltage to
provide OVP and uses a dual OVP approach
(described below). When OVP is triggered, the
MP2884A pulls all activated PWMs low to turn
on the low-side MOSFET to discharge the
output capacitors until VOUT reaches +300mV.
Then all PWMs are set to Hi-Z.
The first OVP type, OVP1, is triggered when the
VDIFF voltage is higher than the OVP1
threshold without any delay time. The OVP1
fault is in latch-off mode.
The OVP1 threshold is VOUT_MAX (24h)
+400mV, regardless of the gain of the
differential voltage sense amplifier.
The second OVP type, OVP2, is triggered when
the VDIFF voltage above the OVP2 threshold
for a pre-set blanking time. Just like in UVP, the
MP2884A provides no action, hiccup, retry six
times, and latch-off modes for the OVP2 fault.
The register MFR_OVUV_LEVEL (2Ch) can
program the OVP2 level to VREF + 430mV, VREF
+ 310mV, and VREF + 190mV. Refer to the
MFR_OVUV_SEL (2Ch) section on page 44.
When programming the gain of the differential
voltage sense amplifier as half, the OVP2
threshold is doubled. For example, set the
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
register to a +190mV level to achieve the VREF +
380mV threshold.
Over-Temperature Protection (OTP)
The MP2884A uses a dual OTP approach.
The first OTP type is VTEMP protection from
the Intelli-Phase (see Figure 9). If the VTEMP
report value is higher than the threshold in the
register OT_WARN_LIMIT (51h), TALERT# is
asserted.
If the VTEMP report value is higher than the
threshold in the register VTEMP_OTP_THRE
(EAh), the VR Hi-Z shuts down.
The VTEMP fault can be programmed to either
latch-off mode or hiccup mode via register
VTEMP_OTP_MODE (EAh).
The second OTP type is TSNS protection from
the thermistor (see Figure 10). If the TSNS
report value is higher than the threshold in
register TSNS_T_ALT_THRE (34h), TALERT#
is asserted. If the TSNS report value is higher
than the threshold in register TSNS_OTP_
THRE (E9h), the VR shuts down.
The TSNS fault can be programmed to no
action, latch-off, or hiccup mode via register
TSNS_OTP_MODE (E9h).
Intelli-Phase Fault Detection
When VTEMP is pulled up to 3.3V or any CS
pin is pulled down to 0V, the MP2884A latches
off immediately. These protections are called
VTEMP fault protection and CS fault protection.
When VTEMP or CS fault protection occurs, the
MP2884A can detect the fault type of the IntelliPhase. There are four typical fault types:
Over-current fault
Over-temperature fault
Low-side MOSFET fault
High-side MOSFET fault
Figure 14: Flow Chart of Intelli-Phase Fault
Detection
The related registers are described below.
1. The enable bit of the VTEMP and CS fault
function is bit[9:8] of MFR_PROTECT_DIS
(3Ah).
2. The enable bit of the ADC sampling the fault
type from the Intelli-Phase PWM is bit[10] of
MFR_PROTECT_DIS (3Ah).
3. The enable bit to record a fault to the
EEPROM is bit[1] of MFR_EEPROM_CTRL
(06h).
Fault type detection only works when the IntelliPhase supports fault type indication via PWMx.
Refer to the datasheet of the Intelli-Phase for
specific details. Figure 14 shows the flow chart
of Intelli-Phase fault detection.
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Protection Type Storage in the EEPROM
Once any protection occurs, the fault type is
recorded to Page 0’s registers F8h ~ FBh. If the
EEPROM fault record is enabled, the last fault
event is recorded in Page 29’s registers FBh ~
FEh. EN must remain high for at least 20ms
after the fault occurs to save the fault type into
the EEPROM.
To clear the fault record in the EEPROM
registers, 0x0000 must be written to these
registers (Page 29 FBh ~ FEh). This is a direct
access to the EEPROM registers. The time
required for each write command is 5ms.
If the CS pins are enabled to program the
phase number, the register setting in E1h is
ignored. Pull down the unused CS pins to
ground. After EN is pulled high, the MP2884A
checks the voltage on the CS pins sequentially
from CS1 to CS4 until it finds the first low
voltage. Figure 15 shows an example of the
connection for 3-phase applications. The first
low voltage is on CS4.
Phase Number Configuration
The MP2884A can be configured to different
phase numbers via the PMBus register or by
CSx (see Table 4).
Table 4: Phase Number Configuration and
Activated PWM Pins
PHASE_CNT (E1h)
Activated PWM Pins
1
PWM1
2
PWM1~2
3
PWM1~3
4
PWM1~4
If PHASE_CNT is set to 0, the MP2884A
operates in 1-phase DCM.
Figure 15: CS Pins Program to 3-Phase
Any unused PWM pin enters tri-state, and the
activated phases interleave automatically. Float
the unused PWM pins. For the Intelli-Phase, if
the PWM input is in Hi-Z, the SW node is in HiZ as well.
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
PMBUS/I2C COMMUNICATION
General Description
The Power Management Bus (PMBus) is an
open-standard, power-management protocol
that defines a means of communicating with
power conversion and other devices. The
PMBus is a two-wire, bidirectional serial
interface consisting of a data line (SDA) and a
clock line (SCL). The lines are pulled to a bus
voltage externally when they are idle. When
connecting the PMBus to the line, a master
device generates the SCL signal and device
address and arranges the communication
sequence. This is based on the principles of I2C
operation.
The MP2884A supports 100kHz, 400kHz, and
1MHz bus timing requirements. Timing and
electrical characteristics of the PMBus can be
found in the Electrical Characteristics section
on page 7 to page 9 or in the PMBus Power
Management Protocol Specification part 1,
revision 1.3 available at http://PMBus.org.
Table 6: Pin Configuration for PMBus/I2C
Address
PMBus
Setting
RADDR1
RADDR2
Address
Point (V)
(kΩ) 1%
(kΩ) 1%
20h
0
0
21h
0.031
3.32
0.059
22h
0.057
3.32
0.11
23h
0.084
3.32
0.162
24h
0.116
3.32
0.226
25h
0.156
3.32
0.316
26h
0.205
3.32
0.43
27h
0.266
3.32
0.576
28h
0.340
3.32
0.768
29h
0.430
3.32
1.05
2Ah
0.540
3.32
1.43
2Bh
0.675
3.32
2
2Ch
0.844
3.32
2.94
2Dh
1.048
3.32
4.64
2Eh
1.301
3.32
8.66
2Fh
1.500
3.32
16.5
PMBus/I2C Address
To support multiple VR devices being used with
the same PMBus/I2C interface, the MP2884A
provides PMBus address programming via
ADDR or a register.
The device address is a 7-bit code and ranges
from 0x00 to 0x7F. The 3MSB bits are set by
the register. The 4LSB bits can be set either by
the register or by the ADDR voltage.
The address of 00h is reserved as the all-call
address. Do not use 00h as the MP2884A
address.
The register MFR_PMBUS_ADDR (BEh) is
used to program or store the device address.
Bit[7] sets the mode of the 4LSB address.
When bit[7] = 0, the 4LSB bits are determined
by the voltage of ADDR, and its value is stored
in register BEh bit[3:0] automatically.
The ADDR voltage can be set by a resistor
divider (see Figure 16). Using 3MSB = 3’b010
as an example, Table 6 shows the resistor
values for different 4LSB addresses.
Figure 16: Recommend Circuit Design of ADDR
Data and Numerical Format
The MP2884A uses the direct format internally
to represent real-world values such as voltage,
current, power, temperature, time, etc.
All numbers with no suffix in this document are
in a decimal format unless explicitly designated
otherwise.
Numbers in a binary format are indicated by a
prefix n’b, where n is the binary count. For
example, 3’b000 is a 3-bit binary data, and the
data is 000. The suffix h indicates a
hexadecimal format, which is used for the
register address number in this document.
The symbol 0x indicates a hexadecimal format,
which is used for the value in the register. For
example, 0x88 is a 1-byte number whose
decimal value is 136.
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
PMBus Communication Failure
A data transmission fault occurs when the data
is not transferred properly between the devices.
There are several types of data transmission
faults listed below.
Send command only
Write byte
Write word
Read byte
Read word
1
1.
2.
3.
4.
5.
1
x
PMBus/I2C Transmission Structure
The MP2884A supports five kinds of
transmission structures with or without PEC.
2
The CLEAR_FAULTS (03h) command can be
used to clear the fault record.
x
Unsupported command code
8
The PEC is calculated in CRC-8 represented by
the polynomial in Equation (14):
x
Sending too few data
Reading too few data
Master sending too many bytes
The MP2884A reading too many bytes
Improperly set read bit in the address byte
x
C
The MP2884A can support the packet error
checking (PEC) mechanism, which can improve
reliability and communication robustness. The
PEC is a CRC-8 error-checking byte calculated
on all the message bytes (including addresses
and read/write bits). The MP2884A only
processes the message if the PEC is correct.
(14)
Figure 17a shows the supported PMBus/I2C
transmission structure without PEC. Figure 17b
shows the supported PMBus/I2C transmission
structure with PEC.
To read or write registers of the MP2884A, the
PMBus/I2C command must be compliant with
the byte number of the registers in the table of
the register map.
Figure 17a: Supported PMBus/I2C Transmission Structure without PEC
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
1)
S
Slave address
wr
A
Command code
A
PEC Byte
A
2)
S
Slave address
wr
A
Command code
A
Data byte
A
PEC Byte
A
3)
S
Slave address
wr
A
Command code
A
Data byte low
A
Data byte high
A
4)
S
Slave address
wr
A
Command code
A
S
Slave address
Rd
A
Data byte
A
PEC Byte
NA
5)
S
Slave address
wr
A
Command code
A
S
Slave address
Rd
A
Data byte low
A
Data byte high
A
P
P
PEC Byte
A
PEC Byte
P
NA
P
P
Master to slave
S
start
P
stop
A
ACK
Wr write (bit value=0)
NA
NACK
Rd
Slave to master
read (bit value=1)
Figure 17b: Supported PMBus/I2C Transmission Structure with PEC
PMBus Reporting and Status Monitoring
The MP2884A supports real-time monitoring of
the VR operation parameters and status using
the PMBus interface (see Table 7).
For high-power applications with an output
current greater than 1024A, the MP2884A uses
register bits to scale the current rate of the
platform via register MFR_SYS_CONFIG (44h).
When the total current report range is doubled,
the setting of the registers in Table 8 should be
updated accordingly.
When the phase current report range is doubled,
the setting of the registers in Table 9 should be
updated accordingly.
Table 7: PMBus Monitored Parameters
Parameter
PMBus
Register
Output voltage
1mV/LSB
8Bh
8Ch
Output current
Refer to
Output power
96h
Table 8
Input power
97h
Temperature
0.1℃/LSB
8Dh
Input voltage
0.03125V/LSB
88h
Phase current
Refer to 73h~77h
VOUT OV fault
7Ah
VOUT UV fault
7Ah
OC fault
7Bh
OT fault
7Dh
VIN UVLO fault
7Ch
VIN OVP fault
7Ch
PMBus fault
7Eh
EEPROM fault
7Eh
VOUT UV warn
7Ah
VID max/min extend
7Ah
warn
OC warn
7Bh
OP warn
7Bh
OT warn
7Dh
VIN UV warn
7Ch
PEC error
7Eh
CRC error
7Eh
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Table 8: Registers Related to Total Current
Report Rate
MFR_SYS_CONFIG
(44h) Bit[3]
Register
1’b0
1’b1
Output current (8Ch)
0.25A/LSB 0.5A/LSB
Output power (96h)
0.5W/LSB
1W/LSB
Input power (97h)
POUT_OP_WARN_LIMIT
1W/LSB
2W/LSB
(6Ah)
IOUT_OC_WARN_LIMIT
(4Ah)
MFR_APS_LEVLE
1A/LSB
2A/LSB
(E3h~E7h)
MFR_APS_HYS (E8h)
OCP_THRESHOLD (ECh)
IOUT_CAL_GAIN (38h)
Refer to register map
IOUT_CAL_OFFSET (39h)
PMBus Write Protection
The MP2884A supports PMBus write protection
(WP) by entering a 16-bit password in register
MFR_USER_PWD (04h). Store the password
to the EEPROM, and after the power-on reset,
no register can be written via the PMBus until
the correct password is entered.
Note that if a wrong password is entered, the
MP2884A disables the PMBus write function
until the VDD33 supply toggles.
The correct password can be entered only once.
If the password is sent more than once, correct
or not, the MP2884A disables the PMBus write
function until the VDD33 supply toggles.
Set the register MFR_USER_PWD (04h) to
0x0000 if the password function is not needed.
Table 9: Registers Related to Phase Current
Report Rate
MFR_SYS_CONFIG
(44h) Bit[4]
Register
1’b0
1’b1
Phase current (73h~77h)
x1
x2
MFR_OCP_PHASE (EDh)
1A/LSB
2A/LSB
MFR_CUR_GAIN (C2h)
Refer to register map
MFR_CS_OFFSET
(4Ch~4Eh)
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
PMBUS COMMANDS @ PAGE 0
Command Code
00h
01h
03h
04h
05h
06h
13h
15h
16h
1Ch
1Dh
1Eh
1Fh
21h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
34h
35h
36h
38h
39h
3Ah
3Bh
3Dh
3Fh
40h
43h
44h
Command Name
PAGE
OPERATION
CLEAR_FAULTS
MFR_USER_PWD
BUF_REG_UPD
MFR_EEPROM_CTRL
WRITE_PROTECT
STORE_USER_ALL
RESTORE_USER_ALL
MFR_DROOP_CMPN1
MFR_DROOP_CMPN2
MFR_IDROOP_CTRL
VOUT_MIN
VOUT_COMMAND
VOUT_OFFSET
VOUT_MAX
VOUT_MARGIN_HIGH
VOUT_MARGIN_LOW
VENDOR_ID_USER
PRODUCT_ID_USER
PRODUCT_REV_USER
MFR_DC_DIV_SET
MFR_IDROOP_OFFSET
MFR_OVUV_SEL
MFR_RSAMP_OFFSET
MFR_VFB_DIGI_GAIN
MFR_IMON_DIGI_GAIN
MFR_DC_LOOP_CTRL
MFR_CB_LOOP_CTRL
MFR_FS_LOOP_CTRL
MFR_T_ALERT_CTRL
VIN_ON
VIN_OFF
IOUT_CAL_GAIN
IOUT_CAL_OFFSET
MFR_PROTECT_DIS
MFR_PS_FORCE
MFR_SLOPE_ADV
MFR_PWM_LIMIT
MFR_OSR_SET
MFR_T_ALERT_CTRL2
MFR_SYS_CONFIG
Type
r/w
r/w
Send
w
Send
r/w
r/w
Send
Send
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
MP2884A Rev. 1.01
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12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
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Bytes
1
1
0
2
0
1
1
0
0
2
2
1
2
2
2
2
2
2
1
1
1
2
1
2
1
2
2
2
1
2
2
2
2
2
2
2
2
2
2
2
2
2
31
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
PMBUS COMMANDS @ PAGE 0 (continued)
Command Code
45h
46h
47h
4Ah
4Ch
4Dh
4Eh
51h
55h
58h
5Dh
5Eh
5Fh
60h
64h
6Ah
6Bh
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
88h
8Bh
8Ch
8Dh
95h
96h
97h
A3h
A4h
A5h
A6h
A7h
Command Name
MFR_VR_CONFIG3
CONFIG_ID
CONFIG_REV_MPS
IOUT_OC_WARN_LIMIT
MFR_CS_OFFSET1
MFR_CS_OFFSET2
MFR_CS_OFFSET3
OT_WARN_LIMIT
VIN_OV_FAULT_LIMIT
VIN_UV_WARN_LIMIT
MFR_DELAY_SET
POWER_GOOD_ON
POWER_GOOD_OFF
TON_DELAY
TOFF_DELAY
POUT_OP_WARN_LIMIT
START_CATCH_AVE
READ_CS1_2
READ_CS3_4
READ_CS5_6
READ_CS7_8
READ_CS9_10
STATUS_BYTE
STATUS_WORD
STATUS_VOUT
STATUS_IOUT
STATUS_INPUT
STATUS_TEMPERATURE
STATUS_CML
READ_VIN
READ_VOUT
READ_IOUT
READ_TEMPERATURE
READ_EFFICIENCY
READ_POUT
READ_PIN
MFR_APS_FS_LIMIT1
MFR_APS_FS_LIMIT2
MFR_APS_FS_LIMIT3
MFR_APS_FS_LIMIT4
MFR_APS_FS_CTRL1
Type
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Send
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r/w
r/w
r/w
r/w
r/w
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
Bytes
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0
2
2
2
2
2
1
2
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
32
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
PMBUS COMMANDS @ PAGE 0 (continued)
Command Code
A8h
A9h
AAh
ABh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
C0h
C1h
C2h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
D2h
D3h
Command Name
MFR_APS_FS_CTRL2
MFR_PHASE_SHED_CTRL
MFR_LOW_PHASE_CNT
MFR_APS_CTRL
MFR_REPORT_CTRL
MFR_PWMVID_TARGET_CTRL
MFR_PWMVID_UP_COMP
MFR_PWMVID_MAX_DUTY
MFR_PWMVID_FLTR_CTRL1
MFR_PWMVID_FLTR_CTRL2
MFR_DUTY_TO_VID_GAIN
MFR_PARM_VOUT_MIN
MFR_PARM_RC_CONST
MFR_PARM_VBOOT_DUTY
MFR_PARM_SLEW_TRAN
MFR_PARM_BOOT_TRAN
MFR_BOOT_SR
MFR_SLEW_SR
MFR_VBOOT
MFR_VID_SD
MFR_FS
MFR_PMBUS_ADDR
MFR_VIN_SENSE_OFFSET
MFR_VIN_SCALE_LOOP
MFR_TEMP_GAIN_OFFSET
MFR_CUR_GAIN
MFR_BLANK_TIME
MFR_SLOPE_SR_DCM
MFR_SLOPE_CNT_DCM
MFR_SLOPE_SR_10P
MFR_SLOPE_CNT_10P
MFR_SLOPE_SR_9P
MFR_SLOPE_CNT_9P
MFR_SLOPE_SR_8P
MFR_SLOPE_CNT_8P
MFR_SLOPE_SR_7P
MFR_SLOPE_CNT_7P
MFR_SLOPE_SR_6P
MFR_SLOPE_CNT_6P
MFR_SLOPE_SR_5P
MFR_SLOPE_CNT_5P
Type
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
Bytes
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
33
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
PMBUS COMMANDS @ PAGE 0 (continued)
Command Code
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DDh
DEh
DFh
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
ECh
EDh
EEh
F8h
F9h
FAh
FBh
FFh
Command Name
MFR_SLOPE_SR_4P
MFR_SLOPE_CNT_4P
MFR_SLOPE_SR_3P
MFR_SLOPE_CNT_3P
MFR_SLOPE_SR_2P
MFR_SLOPE_CNT_2P
MFR_SLOPE_SR_1P
MFR_SLOPE_CNT_1P
MFR_SLOPE_TRIM1
MFR_SLOPE_TRIM2
MFR_SLOPE_TRIM3
MFR_SLOPE_TRIM4
MFR_VR_CONFIG1
MFR_VR_CONFIG2
MFR_APS_LEVEL1
MFR_APS_LEVEL2
MFR_APS_LEVEL3
MFR_APS_LEVEL4
MFR_APS_LEVEL5
MFR_APS_HYS
MFR_TSNS_OT_SET
MFR_VTEMP_OT_SET
MFR_OCP_TOTAL
MFR_OCP_PHASE
MFR_OVP_UVP_SET
MFR_FAULTS1
MFR_FAULTS2
MFR_FAULTS3
MFR_FAULTS4
CLEAR_EEPROM_FAULTS
Type
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r
r
r
r
Send
Bytes
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
2
2
2
2
1
2
2
2
1
2
2
2
2
2
0
PMBUS COMMANDS @ PAGE 29
Command Code
FBh
FCh
Command Name
MFR_LAST_FAULTS1
MFR_LAST_FAULTS2
FDh
FEh
MFR_LAST_FAULTS3
MFR_LAST_FAULTS4
Type
r/w
r/w
r/w
r/w
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
Bytes
2
2
2
2
34
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
PAGE 0 REGISTER MAP
PAGE (00h)
The PAGE command provides the ability to configure, control, and monitor all registers, including test
mode and the EEPROM, through only one physical address.
Command
Format
Bit
Access
Function
7
r/w
X
6
r/w
X
PAGE
Unsigned binary
4
3
r/w
r/w
5
r/w
2
r/w
1
r/w
0
r/w
PAGE
Bits
Bit Name
Description
7:6
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Register page selector.
5:0
00(hex): Page 0, all PMBus commands address normal function registers
02(hex): Page 2, all PMBus commands address test mode registers
28(hex): Page 28, all PMBus commands address EEPROM registers (00h~FFh)
29(hex): Page 29, all PMBus commands address EEPROM registers
(100h~1FFh)
PAGE
EE_WORD_WR_EN = 1: Page 28/Page 29 is accessible
EE_WORD_WR_EN = 0: Page 28/Page 29 is not accessible
EE_WORD_WR_EN is bit[2] of MFR_EEPROM_CTRL (06h)
OPERATION (01h)
This register is used to turn the output on or off when EN is high. OPERATION is also used to set the
output voltage to the upper or lower MARGIN voltages.
Command
Format
Bit
Access
Function
Bits
7
r/w
6
r/w
Bit Name
5
r/w
OPERATION
Unsigned binary
4
3
r/w
r/w
OPERATION_MODE
2
r/w
1
r/w
0
r/w
Description
Operation mode.
7:0
OPERATION_MODE
00xxxxxx: Hi-Z off
01xxxxxx: soft off
1000xxxx: normal on
1001xxxx: margin low
1010xxxx: margin high
The value of “x” does not matter.
CLEAR_FAULTS (03h)
The CLEAR_FAULTS command is used to clear any fault bits in all status registers (STATUS_BYTE,
STATUS_WORD, STATUS_VOUT, STATUS_IOUT, STATUS_INPUT, STATUS_TEMPERATURE,
and STATUS_CML).
This command is write only. There is no data byte for this command.
MP2884A Rev. 1.01
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12/25/2018
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35
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_USER_PWD (04h)
This register presets the password for PMBus write protection.
Command
MFR_USER_PWD
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
Function
MFR_USER_PWD
Bits
Bit Name
Description
16:0
MFR_USER_PWD
Password for PMBus write protection.
Set password to 0x0000 for unprotected mode.
BUF_REG_UPD (05h)
Registers PHASE_CNT (E1h) and MFR_FS (BDh) are double-buffered. The BUF_REG_UPD
command can update them on the fly simultaneously.
This command is write only. There is no data byte for this command.
MFR_EEPROM_CTRL (06h)
This register controls the memory behavior and selects the trim register for the ratio of IDROOP / ICSSUM to
increase overall droop accuracy.
Command
Format
Bit
Access
Function
7
r/w
x
6
r/w
x
5
r/w
x
MFR_EEPROM_CTRL
Unsigned binary
4
3
r/w
r/w
IDROOP_TRIM_SEL
2
r/w
1
r/w
Bits
Bit Name
Description
7:5
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
0
r/w
Trim register selector for the ratio of IDROOP / ICSSUM.
00: select TRIM_IDROOP1 (9Ch)
01: select TRIM_IDROOP2 (9Dh)
10: select TRIM_IDROOP3 (9Eh)
11: select TRIM_IDROOP4 (9Fh)
There are 16 types of ratios for IDROOP / ICSSUM divided into four groups. Each
group has one trim value for corresponding ratios (see table below). The
selection of the trim register must match IDROOP_SET in register 1Ch.
IDROOP_SET
4:3
IDROOP_TRIM_SEL
Trim Register
0 (0)
1 (5/64)
2 (6/64)
IDROOP_SET
8 (12/64)
TRIM_IDROOP1
(9Ch)
9 (13/64)
10 (14/64)
3 (7/64)
11 (15/64)
4 (8/64)
12 (16/64)
5 (9/64)
6 (10/64)
7 (11/64)
Trim Register
TRIM_IDROOP2
(9Dh)
13 (17/64)
14 (18/64)
TRIM_IDROOP3
(9Eh)
TRIM_IDROOP4
(9Fh)
15 (19/64)
MP2884A Rev. 1.01
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36
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
2
EE_WORD_WR_EN
Enable bit for writing and reading the EEPROM via the PMBus on Page 28/Page
29.
0: disable
1: enable
Enable bit for auto-saving a fault status into the EEPROM.
1
FAULT_SAVE_EN
0: disable
1: enable
Enable bit for CRC fault protection.
0: EEPROM CRC fault does not stop the output power
1: EEPROM CRC fault stops the output power. The device enters shutdown
mode.
0
CRC_PROTECT_EN
In the process of storing memory data into the EEPROM, the device calculates
the CRC for all saved bits and saves the CRC result in the EEPROM. In the
process of restoring the EEPROM data to the memory, the device calculates the
CRC for all restored bits. At the end of the restore process, the device checks the
CRC results saved in the EEPROM with the calculated CRC. If they do not
match, the device reports a CRC fault and sets bit[4] of STATUS_CML (7Eh).
WRITE_PROTECT (13h)
This register is used to enable EEPROM write protection.
Command
Format
Bit
Access
Function
7
r/w
Bits
Bit Name
7:0
EEPROM_WP
6
r/w
5
r/w
WRITE_PROTECT
Unsigned binary
4
3
r/w
r/w
EEPROM write protection
2
r/w
1
r/w
0
r/w
Description
Enable this bit for EEPROM write protection.
0x00: disable EEPROM write
0x63: enable EEPROM write
STORE_USER_ALL (15h)
The STORE_USER_ALL command instructs the PMBus device to copy the Page 0 contents of the
operating memory to the matching locations in the EEPROM. In the process, the device calculates the
CRC for all saved bits and saves the CRC result in the EEPROM.
This command is write only. There is no data byte for this command.
RESTORE_USER_ALL (16h)
The RESTORE_USER_ALL command instructs the PMBus device to copy the Page 0 contents from
the EEPROM and overwrite the matching locations in the operating memory. In this process, the device
calculates the CRC for all restored bits. If the calculated CRC does not match the CRC value saved in
the EEPROM, the device reports the CRC error via bit[4] of register STATUS_CML (7Eh). The CRC
error protect action is determined by bit[0] of MFR_EEPROM_CTRL (06h).
After the POR, the device triggers the memory copy operation from the EEPROM. This process is the
same as the operating RESTORE_USER_ALL command.
It is not permitted to send this command while the device is outputting power; otherwise, the command
will be ignored.
This command is write only. There is no data byte for this command.
MP2884A Rev. 1.01
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12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
37
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_DROOP_CMPN1 (1Ch)
This register is used to compensate for extra droop current for the linear upward DVID with a droop
resistor.
Command
MFR_DROOP_CMPN1
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Bits
CNT_DROOP_CMPN_DEC
Bit Name
DROOP_CMPN_LIMIT
Description
Enable bit of the droop compensation for the upward DVID.
15
DROOP_CMPN_EN
0: disable
1: enable
14:9
CNT_DROOP_CMPN_
DEC
Interval time to decrease each step of droop compensation after the upward
DVID. 50ns/LSB
8:6
CNT_DROOP_CMPN_
INC
VID step counter for increasing each step of droop compensation during the
upward DVID.
5:0
DROOP_CMPN_LIMIT
Maximum droop compensation value for upward DVID. 6.25mV/LSB.
MFR_DROOP_CMPN2 (1Dh)
This register is used to compensate for extra droop current for the linear upward DVID with a droop
resistor and set the VID-DAC filter parameter.
Command
MFR_DROOP_CMPN2
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Bits
CNT_DROOP_CMPN_HOLD
Bit Name
DROOP_CMPN_FALL_THRE
Description
Time constant of the VID-DAC output filter for the downward DVID and steady
state.
00: 2µs
01: 4µs
10: 6.5µs
11: 8.5µs
15:14
VID_DAC_FLT_SEL
13
VID_FLT_EN
12
DAC_CMPR_EN
0: disable
1: enable
11:6
CNT_DROOP_CMPN_
HOLD
Holding time before decreasing the droop compensation after the upward DVID.
50ns/LSB
5:0
DROOP_CMPN_FALL_
THRE
Droop compensation falling threshold for reactivating the VID-DAC output filter.
6.25mV/LSB. Only effective when VID_FLT_EN = 1.
Enable bit of the VID-DAC output filter for the downward DVID and steady state.
0: disable
1: enable
Enable bit of the comparator of the VID-DAC output with its filtered voltage.
MP2884A Rev. 1.01
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12/25/2018
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© 2018 MPS. All Rights Reserved.
38
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_IDROOP_CTRL (1Eh)
This register sets the droop current gain and AC droop.
Command
Format
Bit
Access
Function
7
r/w
x
6
r/w
x
MFR_IDROOP_CTRL
Unsigned binary
4
3
r/w
r/w
5
r/w
2
1
r/w
r/w
IDROOP_SET
0
r/w
Bits
Bit Name
Description
7:6
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
5
4
3:0
Enable bit of the AC droop loop. This loop eliminates the droop effect in steady
state but keeps the droop effective during the load transient or DVID.
AC_DROOP_EN
0: disable
1: enable
AC_DROOP_LOOP_BW
Sets the bandwidth of the AC droop loop. This bit is only effective when
AC_DROOP_EN = 1.
0: BW = 20kHz
1: BW = 40kHz
IDROOP_SET
0
1
2
3
4
5
6
7
IDROOP_SET
IDROOP / ICSSUM
0
5/64
6/64
7/64
8/64
9/64
10/64
11/64
IDROOP_SET
8
9
10
11
12
13
14
15
IDROOP / ICSSUM
12/64
13/64
14/64
15/64
16/64
17/64
18/64
19/64
VOUT_MIN (1Fh)
This register sets the minimum voltage setting for both PWM-VID mode and PMBus VID override mode.
VOUT_MIN
Command
Format
VID
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
Function
VOUT_MIN
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8:0
VOUT_MIN
Minimum voltage setting. Any setting smaller than this value is clamped. This is
the target VID when the pulse duty from PWM-VID is zero. 6.25mV/LSB.
VOUT_COMMAND (21h)
This register is used to set the output voltage on the fly for PMBus VID override mode.
Command
VOUT_COMMAND
Format
VID
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
Function
VOUT_COMMAND
MP2884A Rev. 1.01
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12/25/2018
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39
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8:0
VOUT_COMMAND
Output voltage for PMBus VID override mode. 6.25mV/LSB.
VOUT_OFFSET (23h)
This register is used to set the output voltage offset from the VID target for PMBus VID override mode.
VOUT_OFFSET
Command
Format
VID
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
x
Function
VOUT_OFFSET
Bits
Bit Name
Description
15:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
7:0
VOUT_OFFSET
Output voltage offset on the VID reference. 6.25mV/LSB. This value is in two’s
complement binary format. Bit[7] is the sign bit.
VOUT_MAX (24h)
This register sets the maximum voltage setting for both PWM-VID mode and PMBus VID override
mode.
VOUT_MAX
Command
Format
VID
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
Function
VOUT_MAX
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored reads are always 0.
VOUT_MAX
Maximum voltage setting. Any setting higher than this value is clamped. In PWMVID mode, this is the target VID when the pulse duty PWM-VID pin is 100%. In
PMBus VID override mode, the OVP1 level is VOUT_MAX + 400mV.
6.25mV/LSB.
8:0
VOUT_MARGIN_HIGH (25h)
This register sets the output voltage when the OPERATION (01h) is set to margin high. VID format.
Command
VOUT_MARGIN_HIGH
Format
VID
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
Function
VOUT_MARGIN_HIGH
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8:0
VOUT_MARGIN_HIGH
Sets the output voltage for the PMBus margin high mode. 6.25mV/LSB.
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
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© 2018 MPS. All Rights Reserved.
40
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
VOUT_MARGIN_LOW (26h)
This register sets the output voltage when OPERATION (01h) is set to margin low. VID format.
Command
VOUT_MARGIN_LOW
Format
VID
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
Function
VOUT_MARGIN_LOW
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8:0
VOUT_MARGIN_LOW
Sets the output voltage for PMBus margin low mode. 6.25mV/LSB.
VENDOR_ID_USER (27h)
This register sets the vendor ID for users.
Command
Format
Bit
Access
Function
7
r/w
6
r/w
5
r/w
VENDOR_ID_USER
Unsigned binary
4
3
r/w
r/w
VENDOR_ID_USER
2
r/w
Bits
Bit Name
Description
7:0
VENDOR_ID_USER
Vendor ID for users. 0x25 represents MPS Corporation.
1
r/w
0
r/w
1
r/w
0
r/w
1
r/w
0
r/w
PRODUCT_ID_USER (28h)
This register sets the product ID for users.
Command
Format
BIT
Access
Function
7
r/w
6
r/w
5
r/w
PRODUCT_ID_USER
Unsigned binary
4
3
r/w
r/w
PRODUCT_ID_USER
2
r/w
Bits
Bit Name
Description
7:0
PRODUCT_ID_USER
Product ID for users. 0x84 represents the MP2884A.
PRODUCT_REV_USER (29h)
This register configures the file code revision.
Command
Format
Bit
Access
Function
7
r/w
6
r/w
5
r/w
PRODUCT_REV_USER
Unsigned binary
4
3
r/w
r/w
PRODUCT_REV_USER
Bits
Bit Name
Description
7:0
PRODUCT_REV_USER
Configure file code revision.
2
r/w
MP2884A Rev. 1.01
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12/25/2018
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41
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_DC_DIV_SET (2Ah)
This register sets the output voltage sensing.
Command
MFR_DC_DIV_SET
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
Function
VOUT_SCALE
Bits
Bit Name
Description
15:14
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
DC loop feedback selector.
13
DC_LOOP_SNS_SEL
12
DC_LOOP_REF_SEL
0: VFB
1: VDIFF
DC loop reference accuracy selector.
0: with 2-bit fraction
1: without 2-bit fraction
Gain selector for the remote sense amplifier.
11
VDIFF_GAIN_SEL
0: unity gain. VOUT is limited to 1.6V. The DC loop regulation has 1.5625mV
resolution.
1: half gain. VOUT can be set to 3.19375V. The DC loop regulation has 3.125mV
resolution.
ADC sensing gain selector for VDIFF and VFB.
10:9
DIFF_FB_SENSE_GAIN
00: half gain
01: unity gain
10: three-quarter gain
11: invalid
When VDIFF_GAIN_SEL = 1, the DIFF_FB_SENSE_GAIN is forced to half the
gain of the inner MP2884A.
8:0
VOUT_SCALE
Calculated scale factor consistent with the gain of the external output voltage
divider. VOUT_SCALE = 32 x VOUT/VOUT_SENSE.
Figure 18: DC Loop Gain Selection Block Diagram
MP2884A Rev. 1.01
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12/25/2018
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© 2018 MPS. All Rights Reserved.
42
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_IDROOP_OFFSET (2Bh)
This register sets an additional offset on the droop current.
Command
Format
Bit
Access
Function
7
r/w
x
6
r/w
x
MFR_IDROOP_OFFSET
Signed binary
4
3
2
r/w
r/w
r/w
IDROOP_OFFSET
5
r/w
1
r/w
0
r/w
Bits
Bit Name
Description
7:6
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
5:0
IDROOP_OFFSET
User offset on the droop current. 0.81µA/LSB. This value is in two’s complement
binary format. Bit[5] is the sign bit.
MFR_OVUV_SEL (2Ch)
This register sets the output voltage OVP2 and UVP2 level.
MFR_OVUV_SEL
Command
Format
binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
Function
1
1
OVUV_LEVEL
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8:7
TRIM_UVP2_OFFSET
Trimming value of UVP2 offset. Factory settings. Do not change.
6
RESERVED
Fixed to 1.
5:4
TRIM_OVP2_OFFSET
Trimming value of OVP2 offset. Factory settings. Do not change.
3
RESERVED
Fixed to 1.
OVP2 and UVP2 level.
2:0
001: 190mV
010: 310mV
100: 430mV
others: invalid
OVUV_LEVEL
If the remote sense amplifier sets the unity gain, then the OVP2 level is VREF +
OVUV_LEVEL. The UVP2 level is VREF - OVUV_LEVEL.
If the remote sense amplifier sets the half gain, then the OVP2 level is VREF +
OVUV_LEVELx2. The UVP2 level is VREF - OVUV_LEVELx2.
MFR_RSAMP_OFFSET (2Dh)
This register is used to apply an offset to the remote sense amplifier. This is used to fine-tune the
output voltage offset.
Command
Format
Bit
Access
Function
7
r/w
x
6
r/w
5
r/w
MFR_RSAMP_OFFSET
Signed binary
4
3
r/w
r/w
RSAMP_OFFSET
2
r/w
1
r/w
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
0
r/w
43
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
Bit Name
Description
7
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Offset on the remote sense amplifier. This value is in two’s complement binary
format. Bit[6] is the sign bit.
6:0
RSAMP_OFFSET
If the remote sense amplifier sets the unity gain, the resolution is 0.5mV/LSB.
If the remote sense amplifier sets the half gain, the resolution is 0.8mV/LSB.
MFR_VFB_DIGI_GAIN (2Eh)
This register sets a digital gain to fine-tune the VFB sense value for the DC loop.
Command
MFR_VFB_DIGI_GAIN
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
Function
VFB_DIGI_GAIN
Bits
Bit Name
Description
15:11
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
10:0
VFB_DIGI_GAIN
Multiplies the VFB ADC sense value by the digital gain. The result is used for the
DC loop. Default value is 1024 for the unity gain.
VFB_SENSE_FINAL = VFB_ADC x VFB_DIGI_GAIN/1024
MFR_IMON_DIGI_GAIN (2Fh)
This register sets a digital gain used to fine-tune the IMON sense value for the output current report.
Command
MFR_ IMON_DIGI_GAIN
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
Function
IMON_DIGI_GAIN
Bits
Bit Name
Description
15:11
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
10:0
IMON_DIGI_GAIN
Multiplies the IMON ADC sense value by the digital gain. The result is used for
output current reporting. The default value is 1024 for the unity gain.
IMON_SENSE_FINAL = IMON_ADC x IMON_DIGI_GAIN/1024
MFR_DC_LOOP_CTRL (30h)
This register sets the output voltage DC loop performance and sets the power mode when adding
phases during the transient.
MFR_DC_LOOP_CTRL
Command
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
PWM_PRD_ERROR_THRE
DC_LOOP_HOLD_TIME
MP2884A Rev. 1.01
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12/25/2018
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44
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
15
Bit Name
Description
FREQ_ADD_PHASE_
MODE
Mode selector for adding phases due to the PWM frequency increasing. When
the controller runs in auto-phase shedding mode, it enters full-phase CCM if it
detects that the PWM frequency has risen higher than the setting limit due to the
load increasing.
0: idle PWMs switch from Hi-Z to low
1: idle PWMs switch from Hi-Z to high
14
13:7
UV_ADD_PHASE_
MODE
PWM_PRD_ERROR_
THRE
Mode selector for adding phases due to VFB dropping. When the controller runs
in auto-phase-shedding mode, it enters full-phase CCM if it detects that VFB has
dropped below VO_REF - 25mV due to the load increasing.
0: idle PWMs switch from Hi-Z to low
1: idle PWMs switch from Hi-Z to high
PWM period error threshold for holding the DC loop and current balance loop.
When the actual PWM period has a deviation from the configured period, either
the positive or negative deviation exceeds this threshold. The DC loop and
current balance loop are held. 80ns/LSB.
Enable bit for holding the DC loop for a certain amount of time when the error of
the PWM period exceeds the threshold PWM_PRD_ERROR_THRE.
6
PRD_HOLD_DC_EN
0: disable
1: enable
This function needs another condition. See MFR_PWM_LIMIT (3Fh) bit[10:7].
5
Enable bit for holding the DC loop for a certain amount of time when the phasecount changes.
PHASE_CNT_
HOLD_DC_EN
0: disable
1: enable
4
VFB_HOLD_DC_EN
3:0
DC_LOOP_HOLD_TIME
Enable bit for holding the DC loop for a certain amount of time when VFB
exceeds the VO_REF - 25mV or VO_REF + 20mV threshold.
0: disable
1: enable
DC loop holding time. 100µs/LSB.
MFR_CB_LOOP_CTRL (31h)
This register sets the current balance (CB) loop performance.
Command
Format
Bit
Access
Function
Bits
7
6
7
r/w
6
r/w
Bit Name
VFB_HOLD_CB_EN
PRD_HOLD_CB_EN
5
r/w
MFR_CB_LOOP_CTRL
Unsigned binary
4
3
r/w
r/w
2
1
r/w
r/w
CB_LOOP_HOLD_TIME
0
r/w
Description
Enable bit for holding the CB loop for a certain amount of time when VFB
exceeds the VO_REF - 25mV or VO_REF + 20mV threshold.
0: disable
1: enable
Enable bit for holding the CB loop for a certain amount of time when the error of
the PWM period exceeds the threshold PWM_PRD_ERROR_THRE.
0: disable
1: enable
MP2884A Rev. 1.01
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12/25/2018
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45
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
5
PHASE_CNT_HOLD_
CB_EN
Enable bit for holding the CB loop for a certain amount of time when the phase
count changes.
0: disable
1: enable
Enable bit for holding the CB loop for a certain amount of time during DVID.
4
DVID_HOLD_CB_EN
0: disable
1: enable
3:0
CB_LOOP_HOLD_TIME
Current balance loop holding time. 100µs/LSB.
MFR_FS_LOOP_CTRL (32h)
This register is used for PWM frequency loop setting.
Command
MFR_FS_LOOP_CTRL
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
x
FS_LOOP_HOLD_TIME
FS_LOOP_KI
Bits
Bit Name
Description
15
RESERVED
Unused. X indicates that writes are ignored and always read as 0.
14
13
Enable bit for holding the frequency loop for a certain amount of time when VFB
exceeds the VO_REF - 25mV or VO_REF + 20mV threshold.
VFB_HOLD_FS_EN
0: disable
1: enable
PHASE_CNT_HOLD_FS
_EN
Enable bit for holding the frequency loop for a certain amount of time when the
phase count changes.
0: disable
1: enable
Enable bit for holding the frequency loop for a certain amount of time during
DVID.
12
DVID_HOLD_FS_EN
11:8
FS_LOOP_HOLD_TIME
7
FS_LOOP_EN
0: disable
1: enable
6:0
FS_LOOP_KI
PWM frequency loop integral parameter.
0: disable
1: enable
Frequency loop holding time. 100µs/LSB.
Enable bit for the PWM frequency loop.
MFR_T_ALERT_CTRL (34h)
This register sets the thermal alert pin (TALERT#) behavior.
MFR_T_ALERT_CTRL
Command
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
Function
T_ALT_DELAY
TSNS_T_ALT_THRE
MP2884A Rev. 1.01
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12/25/2018
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46
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
Bit Name
Description
15:14
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
13:11
T_ALT_DELAY
Trigger delay time for pulling TALERT# low. 100µs/LSB.
10
9
TSNS_CURRENT_DIS
TEMP_T_ALT_EN
7:0
TSNS_T_ALT_THRE
0: enable
1: disable
Enable bit for pulling TALERT# low when the controller detects an overtemperature warning from TSNS.
TSNS_T_ALT_EN
8
Enable bit for sourcing a 10µA constant current from TSNS to the thermistor to
generate a voltage for the temperature sensing.
0: disable
1: enable
Enable bit for pulling TALERT# low when the controller detects an overtemperature warning from VTEMP.
0: disable
1: enable
Digital threshold of the over-temperature warning from TSNS.
TSNS_T_ALT_THRE = Rt x 10µA x 256 / 1.6V
VIN_ON (35h)
This register sets the input voltage UVLO rising threshold. When the input voltage rises higher than
VIN_ON, the MP2884A soft starts to the boot voltage with a programmed slew rate.
Command
VIN_ON
Format
Linear, two’s complement binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Exponent
Bits
Bit Name
15:11
Exponent
10:8
RESERVED
7:0
Mantissa
x
Mantissa
Description
This value is two’s complement binary format and fixed to 11101.
Exponent = -3 (fixed)
Unused. X indicates that writes are ignored and reads are always 0.
Input voltage UVLO rising threshold. 0.125V/LSB.
VIN_ON = Mantissa x 2exponent = Mantissa x 0.125
VIN_OFF (36h)
This register sets the input voltage UVLO falling threshold. When the input voltage falls below VIN_OFF,
all PWMs enter tri-state mode, and the VR shuts down.
Command
VIN_OFF
Format
Linear, two’s complement binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Exponent
x
Mantissa
MP2884A Rev. 1.01
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12/25/2018
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47
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
Bit Name
Description
15:11
Exponent
10:8
RESERVED
7:0
Mantissa
This value is two’s complement binary format and fixed to 11101.
Exponent = -3 (fixed)
Unused. X indicates that writes are ignored and always read as 0.
Input voltage UVLO falling threshold. 0.125V/LSB.
VIN_OFF = Mantissa x 2exponent = Mantissa x 0.125
IOUT_CAL_GAIN (38h)
This register sets the gain for the total current report in the READ_IOUT register. This is the ratio of the
IMON voltage to the total output current. This is related to the DrMOS current sense gain (Kcs) and
IMON current sense resistor (RIMON).
IOUT_CAL_GAIN
Command
Format
Linear, two’s complement binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Bits
Exponent
Mantissa
Bit Name
Description
This value is in two’s complement binary format.
15:11
10001: exponent = -15
10010: exponent = -14
10011: exponent = -13
others: invalid
Exponent
Mantissa
10:0
VIMON
K RIMON
2 exp onent CS
2 exp onent
IOUT
16000
Where VIMON is the voltage of IMON, IOUT is the total output current, RIMON is the
resistor connected from IMON to ground (in kΩ), and KCS is the current sense
gain of the DrMOS (in µA/A).
Mantissa
When RIMON is too big for Mantissa < 211, increase the exponent. This usually
meets small load-current applications.
If TOTAL_CURRENT_RESOLUTION (44h) = 1, then IOUT_CAL_GAIN must be
doubled.
IOUT_CAL_OFFSET (39h)
This register is used to set the offset for the total current report in READ_IOUT.
Command
IOUT_CAL_OFFSET
Format
Linear, two’s complement binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Exponent
Bits
Bit Name
15:10
Exponent
9:7
RESERVED
x
3
2
1
0
r/w
r/w
r/w
r/w
Mantissa
Description
This value is in two’s complement binary format (fixed at 111100).
Exponent = -2 (fixed)
Unused. X indicates that writes are ignored and reads are always 0.
MP2884A Rev. 1.01
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48
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
IOUT _ CAL _ OFFSET Mantissa 2exp onent Mantissa 0.25
6:0
0.25A/LSB (TOTAL_CURRENT_RESOLUTION = 0)
0.5A/LSB (TOTAL_CURRENT_RESOLUTION = 1)
Mantissa
This value is in two’s complement binary format. Bit[6] is the sign bit.
MFR_PROTECT_DIS (3Ah)
This register is used for protection selection.
Command
MFR_PROTECT_DIS
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
Function
OVP1_DIS
Bits
Bit Name
Description
15:11
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
OTP _DIS
Enable bit for ADC sampling of the Intelli-Phase PWM once a protection occurs.
10
PWM_CHK_FAULT_EN
In this process, all PWM outputs remain in Hi-Z status.
0: disable
1: enable
9
8
CS_FAULT_EN
TEMP_FAULT_EN
Enable bit for CSx fault protection from CS. Voltage on any CS pin falling below
0.3V can trigger CSx fault protection and latch the controller.
0: disable
1: enable
Enable bit for VTEMP fault protection from VTEMP. Voltage on VTEMP
exceeding a certain threshold can trigger VTEMP fault protection and latch the
controller.
0: disable
1: enable
7
TEMP_FAULT_BLOCK_
OTP
6
DVID_BLOCK_OVP1
5:4
VIN_PROTECT_DIS
3:2
OVP1_DIS
1:0
OTP_DIS
Enable bit for blocking OTP when a VTEMP fault protection is triggered.
0: enable
1: disable
Enable bit for blocking the output voltage OVP1 during DVID.
0: disable
1: enable
Enable bits for the input voltage UVLO and OVP.
11: disable
others: enable
Enable bits for the output voltage OVP1.
01: disable
others: enable
Enable bits for OTP from VTEMP.
01: disable
others: enable
MP2884A Rev. 1.01
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49
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_PS_FORCE (3Bh)
This register is used to set advanced functions of the controller, such as forced power state, and related
parameters.
Command
MFR_PS_FORCE
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
Function
x
x
TRI_STATE_DELAY
Bits
Bit Name
Description
15
PSI_CONTROL
0: jump to full-phase during soft start and DVID, even if PSI is low
1: follow PSI to reach the target phase-count during soft start and DVID
14
PWM_TRI_MODE
0: Hi-Z
1: force 1.5V middle voltage
13
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
12
VIN_MUX_SEL
11
PROTECT_ALL_DIS
0: enable protection
1: disable all protection
10:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 2’b11.
PWM tri-state mode selector.
VIN value mode selector for TON calculation.
0: real-time VIN
1: latched VIN
Master enable bit for all protections.
8
Enable bit for updating TON when VIN varies or moves away from the previous
latched VIN value.
VIN2TON_EN
0: disable
1: enable
Enable bit of DLL. DLL can increase the PWM resolution to 0.625ns/LSB.
7
DLL_EN
0: disable
1: enable
6
RESERVED
Unused. X indicates that writes are ignored and reads are always 1.
5
IOUT_FILTER_SET
4:0
TRI_STATE_DELAY
Output current reporting mode selector.
0: average IOUT report
1: real-time IOUT report
PWM low-time inserted between PWM high and tri-state when the PWM logic
changes from high-state to middle-state. 5ns/LSB.
MFR_SLOPE_ADV (3Dh)
This register is used for advanced slope compensation setting.
Command
Format
Bit
Access
Function
15
r/w
x
14
r/w
13
r/w
12
r/w
11
r/w
10
r/w
MFR_SLOPE_ADV
Unsigned binary
9
8
7
6
r/w
r/w
r/w
r/w
INI_SLOPE_CURRENT
5
r/w
4
r/w
3
r/w
MP2884A Rev. 1.01
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12/25/2018
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2
r/w
1
r/w
0
r/w
50
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
Bit Name
Description
15
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
14
SS_PHASE_CUR_LIMIT
_EN
Enable bit of the per-phase valley current limit during soft start.
Trigger delay time for phase skipping when a certain phase triggers the phase
current limit. 20ns/LSB with 15ns offset.
13:12
OC_SKIP_PHASE_TIME
When a certain phase's current is above the phase current limit, its PWM high
logic is delayed until the current drops below the limitation. If the delay time is
reached, this phase's PWM high logic is passed to the next phase.
Enable bit of the initial slope compensation before the first PWM during soft start.
11
INI_SLOPE_EN
0: disable
1: enable
If enabled, the initial slope slew rate is set via INI_SLOPE_CURRENT.
Current source value for initial slope compensation before the first PWM during
soft start. 0.25µA/LSB.
10:5
INI_SLOPE_CURRENT
VSLOPE@INI
INI_SLOPE_CURRENT
Tcharge(us)
161.85(pF)
The maximum charging time is 0.4µs.
Slope compensation blank time selector.
4
SLOPE_BLANK_SEL
0: use the calculated TON
1: use register SLOPE_BLANK_TIME
The blank time starts when the PWM rises high. During the blank time, the slope
compensation capacitor is discharged.
Mode selector for idle PWMs to exit tri-state during phase-adding.
3
PRE_BIAS_MODE
2
EXIT_DCM_SLOPE_
MODE
1
DCM_SLOPE_CLAMP
0: idle PWMs rise high from tri-state when their own high logic comes
1: all idle PWMs drop low from tri-state when the first high logic of any phase
comes. This high logic phase's PWM rises high directly.
Mode selector of the first CCM compensating slope when the controller exits
DCM.
0: first CCM slope rises on the base of the DCM slope voltage
1: first CCM slope rises after clearing the DCM slope voltage
Enable bit of the 60mV maximum limit for DCM slope compensation.
0
SLOPE_SWITCH_OFF_
EN
0: disable
1: enable
Enable bit for turning off the low leakage switch when the slope compensation
current source turns off. The low leakage switch is in series with the capacitor
and current source of slope compensation.
0: disable
1: enable
MP2884A Rev. 1.01
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51
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_PWM_LIMIT (3Fh)
This register sets the PWM minimum on time and minimum off time.
Command
MFR_PWM_LIMIT
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
Function
ON_TIME_LIMIT
MIN_ON_TIME
MIN_OFF_TIME
Bits
Bit Name
Description
15:11
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
10:7
ON_TIME_LIMIT
PWM on-time threshold for the DC loop hold function. This is another condition
for the function of holding the DC loop via an error of the PWM period. If the
calculated TON is less than this threshold, the DC loop cannot be held via the
PWM period, even if bit[6] of MFR_DC_LOOP_CTRL (30h) is set. 5ns/LSB.
6:4
MIN_ON_TIME
PWM minimum on time. 5ns/LSB.
3:0
MIN_OFF_TIME
PWM minimum off time. 20ns/LSB with 15ns offset.
MFR_OSR_SET (40h)
This register sets the minimum PWM off-time and block time of the OSR function.
Command
MFR_OSR_SET
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
Function
OSR_DEGLITCH_TIME
OSR_BLOCK_TIME
Bits
Bit Name
Description
15:14
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
13:8
OSR_DEGLITCH_TIME
Minimum PWM off time in the OSR process. 5ns/LSB.
7:0
OSR_BLOCK_TIME
Block time between two OSR events. 5ns/LSB.
MFR_T_ALERT_CTRL2 (43h)
This register sets thermal alert pin (TALERT#) behavior.
Command
MFR_T_ALERT_CTRL2
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
Function
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8
TSNS_RES_SEL
Type selection bit of TSNS thermistor.
0: PTC
1: NTC
MP2884A Rev. 1.01
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52
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Digital threshold of the over-temperature warning de-assertion from TSNS.
7:4
TSNS_T_ALT_DST_
THRE
3:0
OT_WARN_DST_THRE
TSNS_T_ALT_DST_THRE = Rt_dst x 10µA x 16 /1.6V
Digital threshold of the over-temperature warning deassertion from VTEMP.
16°C/LSB.
MFR_SYS_CONFIG (44h)
This register sets the system configuration.
Command
MFR_SYS_CONFIG
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
x
Bits
Bit Name
Description
15:12
DGTL_UVP_LEVEL
Threshold of digital Vo_UVP. 32mV/LSB
11
DGTL_UVP_EN
Enable bit of digital Vo_UVP.
10
OC_BLK_UVP_EN
9
ANA_UVP_DIS
0: disable
1: enable
Enable bit for blocking analog Vo_UVP when any phase's current reaches the
per-phase-valley-current limit (the internal OC signal rises high).
1: block
0: do not block
Enable bit of analog Vo_UVP.
1: disable
0: enable
Deglitch time of the internal OC signal which is boolean and with a digital UV
signal to trigger digital Vo_UVP.
8:7
OC_DGLTCH_FOR_
DGTL_UVP
6
AC_LL_ACTIVATE_
MODE
5
RESERVED
4
PHASE_CURRENT_
RESOLUTION
3
TOTAL_CURRENT_
RESOLUTION
00: 800ns
01: 1000ns
10: 1200ns
11: force the internal OC signal high
AC droop loop activation mode.
1: activate AC Droop loop when soft-start begins.
0: activate AC Droop loop once the controller finishes POR.
Unused. X indicates that writes are ignored and reads are always 0.
Resolution selector for per-phase current report and protection.
0: original resolution
1: half resolution (double range)
Resolution selector for total current report, protection, warning, and auto-phase
shedding (APS) levels.
0: original resolution
1: half resolution (double range)
MP2884A Rev. 1.01
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53
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
DrMOS current sense gain indicator for GUI.
2:0
000: CS gain is 8.5µA/A
001: CS gain is 9.7µA/A
010: CS gain is 10µA/A
011: CS gain is 5µA/A
others: reserved
DRMOS_CS_TYPE
MFR_VR_CONFIG3 (45h)
This register selects the main functions of the controller.
MFR_VR_CONFIG3
Command
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
0
1
Bits
Bit Name
Description
15
RESERVED
Fixed to 0.
0
Mode selector of VTEMP_FAULT.
14
TEMP_FAULT_MODE
0: hiccup
1: latch
APS activation mode after soft start when PSI is in mid-state.
13
APS_ACTIVATE_MODE
1: activate APS when soft start has finished and PWM-VID signal starts switching
(exiting Hi-Z state for the first time)
0: activate APS when soft start finishes, regardless of PWM-VID signal
Phase-count setting mode.
12
PHASE_CNT_SET_
MODE
11
PARM_VOUT_MIN_
MSB
10
MFR_CB_SS_EN
0: phase count set by bit[3:0] of MFR_VR_CONFIG1 (E1h)
1: phase count set by external CSx pin. CSx pins of unused phases should be
shorted to GND in this mode. The controller only detects CSx pins during the first
POR. Short the CS of certain phases to GND to block all higher-number phases.
Highest bit of parameter PARM_VOUT_MIN.
Parameter
PARM_VOUT_MIN_16LSB
MFR_PARM_VOUT_MIN (B4h).
is
described
in
register
Enable bit for not holding the CB loop during soft start.
0: disable
1: enable
Enable bit for variable parameter control of CB loop.
9
CB_LARGE_PI_EN
8:6
MFR_CB_LARGE_PI
0: disable. The PI parameter of the CB loop is always at a constant value.
1: enable. When the voltage error between CSx and CS1 is more than 50mV, a
large PI parameter is adopted in the CB loop to make the regulation process
faster. The large PI parameter is decided by bit[8:6] of MFR_VR_CONFIG3
(45h).
Large PI parameter of the CB loop for variable parameter control.
Internal PI parameter = MFR_CB_LARGE_PI * 32 + 31
MP2884A Rev. 1.01
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54
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Enable bit for 3-level VID control by the PWMVID pin in PMBus mode.
0: disable
1: enable
5
PWMVID_3_LEVEL_EN
The relationship between the PWMVID pin state and VID is shown in the table
below.
PWMVID
High
VID
VOUT_MAX
VOUT_COMMAND
/ Vboot
VOUT_MIN
Hi-Z
Low
Register 24h
Register 21h
/ Determined by BOOT pin
Register 1Fh
Enable bit for clamping the PWM on time to avoid a negative overflow.
4
TON_CLAMP_EN
3
VTEMP_OFFSET_
SIGNED
0: disable. PWM on-time range must be designed within 90ns to 1120ns. If the
on time is less than 90ns, it risks a negative overflow.
1: enable. PWM on time can be clamped to MIN_ON_TIME(3Fh bit[6:4]). The on
time design range is from MIN_ON_TIME to 1120ns.
Sign bit of parameter VTEMP_OFFSET.
The definition of the parameter VTEMP_OFFSET is described in register
MFR_TEMP_GAIN_OFFSET (C1h).
The VBOOT control mode selection in PMBus mode.
2
PMBUS_VBOOT_SEL
0: VBOOT is determined by the value of VOUT_COMMAND (21h)
1: VBOOT is determined by the voltage of TSNS/BOOT. After the soft start, the
real-time VID can be updated by register VOUT_COMMAND (21h).
Pin-strap VBOOT table selector.
1:0
00: VBOOT table is 0.1V/step, up to 1.5V
01: VBOOT table is 0.05V/step, up to 1.55V
10: VBOOT table is 0.2V/step, up to 3.0V
11: VBOOT table is 0.1V/step, up to 3.1V
PIN_VBOOT_TABLE
_SEL
Refer to Table 1a and Table 1b for detail.
CONFIG_ID (46h)
This register is the identification code for different applications.
Command
CONFIG_ID
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Bits
Bit Name
Description
15:0
CONFIG_ID
Identification code for different applications. This is part of MPS product part
numbers.
CONFIG_REV_MPS (47h)
This register saves the revision number to indicate different configurations.
Command
CONFIG_REV_MPS
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
APPLICATION_REV
SILICON_REV
FIRMWARE_REV
MP2884A Rev. 1.01
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55
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
Bit Name
Description
15:12
APPLICATION_REV
Application version. “E” is for engineering version, “0” is for production version.
11:8
SILICON_REV
Silicon version. "0" indicates R0, "1" indicates R1, and so on.
7:0
FIRMWARE_REV
Revision number indicates different firmware configurations.
IOUT_OC_WARN_LIMIT (4Ah)
This register sets the output current OC warning threshold.
Command
IOUT_OC_WARN_LIMIT
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
Function
IOUT_OC_WARN_LIMIT
Bits
Bit Name
Description
15:10
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
9:0
IOUT_OC_WARN_LIMIT
Output current OC warning threshold. If the sensed output current is greater than
this threshold, bit[5] of STATUS_IOUT (7Bh) is set.
1A/LSB (TOTAL_CURRENT_RESOLUTION = 0)
2A/LSB (TOTAL_CURRENT_RESOLUTION = 1)
MFR_CS_OFFSET1 (4Ch)
This register sets the phase-current offset for the current balance loop.
Command
MFR_CS_OFFSET1
Format
Signed binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
x
CS_OS_PHASE4
CS_OS_PHASE3
CS_OS_PHASE2
Bits
Bit Name
Description
15
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
14:10
CS_OS_PHASE4
Phase 4 current offset. Two’s complement binary format. Bit[14] is the sign bit.
9:5
CS_OS_PHASE3
Phase 3 current offset. Two’s complement binary format. Bit[9] is the sign bit.
4:0
CS_OS_PHASE2
Phase 2 current offset. Two’s complement binary format. Bit[4] is the sign bit.
Calculate the phase-current offset with Equation (15):
CS_OS_PHASEn = 512 x IOFFSET x KCS x RCS / 1600
(15)
Where RCS is the phase current sense resistor (in kΩ), and KCS is the current sense gain of the DrMOS
(in µA/A).
MP2884A Rev. 1.01
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12/25/2018
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56
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_CS_OFFSET2 (4Dh)
This register sets the phase-current offset for the current balance loop.
Command
MFR_CS_OFFSET2
Format
Signed binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
x
x
x
x
Bits
Bit Name
Description
15
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
14:10
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
9:5
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
4:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Calculate the phase-current offset with Equation (16):
CS_OS_PHASEn = 512 x IOFFSET x KCS x RCS / 1600
(16)
Where RCS is the phase current sense resistor (in kΩ), and KCS is the current sense gain of the DrMOS
(in µA/A).
MFR_CS_OFFSET3 (4Eh)
This register sets the phase-current offset for the current balance loop.
Command
Format
Bit
Access
Function
15
r/w
x
Bits
Bit Name
Description
15
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
14:10
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
9:5
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
4:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
14
r/w
13
r/w
12
r/w
x
11
r/w
10
r/w
MFR_CS_OFFSET3
Signed binary
9
8
7
6
r/w
r/w
r/w
r/w
x
5
r/w
4
r/w
3
r/w
2
r/w
x
1
r/w
0
r/w
Calculate the phase-current offset with Equation (17):
CS_OS_PHASEn = 512 x IOFFSET x KCS x RCS / 1600
(17)
Where RCS is the phase current sense resistor (in kΩ), and KCS is the current sense gain of the DrMOS
(in µA/A).
OT_WARN_LIMIT (51h)
This register sets the over-temperature warning threshold via VTEMP.
Command
OT_WARN_LIMIT
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
x
Function
OT_WARN_LIMIT
MP2884A Rev. 1.01
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57
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
Bit Name
Description
15:8
RESERVED
Unused. X indicates writes are ignored and reads are always 0.
7:0
OT_WARN_LIMIT
Over-temperature warning threshold. If the sensed temperature via VTEMP is
higher than this value, bit[6] of STATUS_TEMPERATURE (7Dh) is set. 1°C/LSB.
VIN_OV_FAULT_LIMIT (55h)
This register sets the input OVP threshold.
Command
VIN_OV_FAULT_LIMIT
Format
Linear, two’s complement binary
Bit
15
14
Access
r/w
r/w
Function
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Exponent
Bits
Bit Name
15:11
Exponent
10:8
RESERVED
x
Mantissa
Description
This value is in two’s complement binary format (fixed at 11101).
Exponent = -3
Unused. X indicates that writes are ignored and always read as 0.
VIN_OV_FAULT_LIMIT Mantissa 2exponent Mantissa 0.125
7:0
Mantissa
If the sensed input voltage is greater than this threshold, the input OVP is
triggered, and the VR shuts down immediately.
VIN_UV_WARN_LIMIT (58h)
This register sets the input under-voltage warning threshold.
Command
VIN_UV_WARN_LIMIT
Format
Linear, two’s complement binary
Bit
15
14
Access
r/w
r/w
Function
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Exponent
Bits
Bit Name
15:11
Exponent
10:8
RESERVED
x
Mantissa
Description
This value is in two’s complement binary format (fixed at 11101).
Exponent = -3
Unused. X indicates that writes are ignored and always read as 0.
VIN_UV_WARN_LIMIT Mantissa 2exp onent Mantissa 0.125
7:0
Mantissa
If the sensed input voltage is lower than this threshold, bit[5] of the status register
STATUS_INPUT (7Ch) is set.
MP2884A Rev. 1.01
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58
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_DELAY_SET (5Dh)
The register sets the delay time of the power good signal and internal VOUT settle signal.
Command
MFR_ DELAY_SET
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
Function
SETTLE_DELAY
PG_DELAY
Bits
Bit Name
Description
15:13
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Delay time from when the output voltage reference reaches the target level to
when the internal VOUT settle signal becomes high. 100µs/LSB.
12:9
SETTLE_DELAY
When VREF is ramping (soft start or DVID), the settle signal is low. When VREF is
settled, the settle signal is high. The DC loop or auto-power mode operate only
when the settle signal is high.
8:0
PG_DELAY
Delay time for asserting the power good signal. 1µs/LSB.
POWER_GOOD_ON (5Eh)
This register sets the output voltage threshold at which the power good signal is asserted.
Command
POWER_GOOD_ON
Format
VID
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
Function
POWER_GOOD_ON
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8:0
POWER_GOOD_ON
Output voltage threshold at which the power good signal is asserted.
6.25mV/LSB.
POWER_GOOD_OFF (5Fh)
This register sets the output voltage threshold at which the power good signal is deasserted.
Command
POWER_GOOD_OFF
Format
VID
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
Function
POWER_GOOD_OFF
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8:0
POWER_GOOD_OFF
Output voltage threshold at which the power good signal is deasserted.
6.25mV/LSB
MP2884A Rev. 1.01
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59
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
TON_DELAY (60h)
This register sets the time from when the controller receives the EN on signal to when VREF starts to
boot up.
Command
TON_DELAY
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Bits
EN_ON_DELAY
Bit Name
Description
Delay time from EN on to VREF boot-up.
15:0
EN_ON_DELAY
50µs/LSB (DLY_CLK_SEL = 1)
20µs/LSB (DLY_CLK_SEL = 0)
TOFF_DELAY (64h)
This register sets the time from when the controller receives the EN off signal to when VREF starts to
soft-shut down.
Command
TOFF_DELAY
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
EN_OFF_DELAY
Bits
Bit Name
Description
15:0
EN_OFF_DELAY
Delay time from EN off to VREF soft-shutdown.
50µs/LSB (DLY_CLK_SEL = 1)
20µs/LSB (DLY_CLK_SEL = 0)
POUT_OP_WARN_LIMIT (6Ah)
This register sets the output over-power warning threshold.
Command
POUT_OP_WARN_LIMIT
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
Function
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
POUT_OP_WARN_LIMIT
Bits
Bit Name
Description
15:10
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
9:0
POUT_OP_WARN_
LIMIT
Output over-power warning threshold. If the sensed output power is higher than
this threshold, bit[0] of STATUS_IOUT (7Bh) is set.
1W/LSB (TOTAL_CURRENT_RESOLUTION = 0)
2W/LSB (TOTAL_CURRENT_RESOLUTION = 1)
START_CATCH_AVE (6Bh)
This command is used for READ_IOUT, READ_PIN, READ_POUT, and READ_EFFICIENCY when
these registers are in latch mode. Send the START_CATCH_AVE command to trigger the averaging
process within a certain average window. At the end of the average window, the results are latched.
MP2884A Rev. 1.01
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
The averaging mode and average window are determined by MFR_REPORT_CTRL (ADh).
This command is write only. There is no data byte for this command.
READ_CS1_2 (73h)
This register is phase-current ADC value of phase 1 and phase 2. An internal low-pass filter is used
before ADC.
Command
READ_CS1_2
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Function
READ_CS2
READ_CS1
Bits
Bit Name
Description
15:8
READ_CS2
Phase 2 current ADC sense value.
7:0
READ_CS1
Phase 1 current ADC sense value.
Calculate the per-phase current sense with Equation (18):
CSn = 256 x (ICS x Kcs x Rcs/1000 + 1.23) / 3.2
(18)
Where RCS is the phase current sense resistor (in kΩ), and KCS is the current sense gain of the DrMOS
(in µA/A).
If PHASE_CURRENT_RESOLUTION = 1 in register 44h, the CS report should be doubled.
READ_CS3_4 (74h)
This register is the phase-current ADC value of phase 3 and phase 4. An internal low-pass filter is used
before ADC.
Command
READ_CS3_4
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Function
READ_CS4
Bits
Bit Name
Description
15:8
READ_CS4
Phase 4 current ADC sense value.
7:0
READ_CS3
Phase 3 current ADC sense value.
READ_CS3
Calculate the per-phase current sense with Equation (19):
CSn = 256 x (ICS x Kcs x Rcs/1000 + 1.23) / 3.2
(19)
Where RCS is the phase current sense resistor (in kΩ), and KCS is the current sense gain of the DrMOS
(in µA/A).
If PHASE_CURRENT_RESOLUTION = 1 in register 44h, the CS report should be doubled.
MP2884A Rev. 1.01
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61
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
READ_CS5_6 (75h)
This register is the phase-current ADC value of phase 5 and phase 6. An internal low-pass filter is used
before ADC.
Command
READ_CS5_6
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Function
x
x
Bits
Bit Name
Description
15:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
7:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Calculate the per-phase current sense with Equation (20):
CSn = 256 x (ICS x Kcs x Rcs/1000 + 1.23) / 3.2
(20)
Where RCS is the phase current sense resistor (in kΩ), and KCS is the current sense gain of the DrMOS
(in µA/A).
If PHASE_CURRENT_RESOLUTION = 1 in register 44h, the CS report should be doubled.
READ_CS7_8 (76h)
This register is the phase-current ADC value of phase 7 and phase 8. An internal low-pass filter is used
before ADC.
Command
READ_CS7_8
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Function
x
x
Bits
Bit Name
Description
15:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
7:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Calculate the per-phase current sense with Equation (21):
CSn = 256 x (ICS x Kcs x Rcs/1000 + 1.23) / 3.2
(21)
Where RCS is the phase current sense resistor (in kΩ), and KCS is the current sense gain of the DrMOS
(in µA/A).
If PHASE_CURRENT_RESOLUTION = 1 in register 44h, the CS report should be doubled.
MP2884A Rev. 1.01
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
READ_CS9_10 (77h)
This register is the phase-current ADC value of phase 9 and phase 10. An internal low-pass filter is
used before ADC.
Command
READ_CS9_10
Format
Unsigned binary
Bit
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Function
x
x
Bits
Bit Name
Description
15:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
7:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Calculate the per-phase current sense with Equation (22):
CSn = 256 x (ICS x Kcs x Rcs/1000 + 1.23) / 3.2
(22)
Where RCS is the phase current sense resistor (in kΩ), and KCS is the current sense gain of the DrMOS
(in µA/A).
If PHASE_CURRENT_RESOLUTION = 1 in register 44h, the CS report should be doubled.
STATUS_BYTE (78h)
This register returns one byte of information for critical faults.
Command
Format
Bit
Access
Function
7
r/w
x
6
r/w
5
r/w
STATUS_BYTE
Unsigned binary
4
3
r/w
r/w
2
r/w
1
r/w
0
r/w
x
Bits
Bit Name
Description
7
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
6
OFF
This bit is asserted if the unit is not providing power to the output. This bit is in
live mode.
5
VOUT_OV_FAULT
Once output OVP occurs, this bit is set. This bit is in latch mode. The
CLEAR_FAULTS command can reset this bit.
4
IOUT_OC_FAULT
Once output OCP occurs, this bit is set. This bit is in latch mode. The
CLEAR_FAULTS command can reset this bit.
3
VIN_UV_FAULT
Once input UVP occurs, this bit is set. This bit is in latch mode. The
CLEAR_FAULTS command can reset this bit.
2
TEMPERATURE
Once OTP or a warning occur, this bit is set. This bit is in latch mode. The
CLEAR_FAULTS command can reset this bit.
1
CML
Once a communications, memory, or logic fault occurs, this bit is set. This bit is
in latch mode. The CLEAR_FAULTS command can reset this bit.
0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
MP2884A Rev. 1.01
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
STATUS_WORD (79h)
This register returns two bytes of information for fault statuses. Based on this information, the host can
get more information by reading the appropriate status registers. The low byte of STATUS_WORD is
the same as the STATUS_BYTE register.
Command
STATUS_WORD
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
x
x
Function
x
x
Bits
Bit Name
Description
15
VOUT
Once output OVP, UVP, or a warning occurs, this bit is set. This bit is in latch
mode. The CLEAR_FAULTS command can reset this bit.
14
IOUT/POUT
Once output OCP, over-power protection (OPP), or a warning occurs, this bit is
set. This bit is in latch mode. The CLEAR_FAULTS command can reset this bit.
13
INPUT
Once any protection or warning of the input voltage, input current, or input power
occurs, this bit is set. This bit is in latch mode. The CLEAR_FAULTS command
can reset this bit.
12
READ_DATA_RDY
When READ_PIN, READ_POUT, or READ_EFFECIENCY uses average window
mode and once the average window calculation is done, the data is ready in the
resistor, and this bit is set. Sending the command START_CATCH_AVE triggers
a new averaging process and resets this bit.
11
POWER_GOOD
When VOUT rises higher than the POWER_GOOD_ON level during the soft-start
process and the delay time is reached, this bit is asserted. This bit is in live
mode.
10:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8
WATCH_DOG_OVF
The monitor value calculation has a watchdog timer. If the timer expires, the
monitor value calculation state machine and the timer are reset. Meanwhile, this
bit is set. This bit is in latch mode. The CLEAR_FAULTS command can reset this
bit
7
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
6
OFF
This bit is asserted if the unit is not providing power to the output. This bit is in
live mode.
5
VOUT_OV_FAULT
Once output OVP occurs, this bit is set. This bit is in latch mode. The
CLEAR_FAULTS command can reset this bit.
4
IOUT_OC_FAULT
Once output OCP occurs, this bit is set. This bit is in latch mode. The
CLEAR_FAULTS command can reset this bit.
3
VIN_UV_FAULT
Once input UVP occurs, this bit is set. This bit is in latch mode. The
CLEAR_FAULTS command can reset this bit.
2
TEMPERATURE
Once OTP or a warning occurs, this bit is set. This bit is in latch mode. The
CLEAR_FAULTS command can reset this bit.
1
CML
Once a communication, memory, or logic fault occurs, this bit is set. This bit is in
latch mode. The CLEAR_FAULTS command can reset this bit.
0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
MP2884A Rev. 1.01
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
STATUS_VOUT (7Ah)
This register records the fault and warning status of the output voltage.
Command
Format
Bit
Access
Function
7
r
6
r
x
5
r
STATUS_VOUT
Unsigned binary
4
3
r
r
2
r
x
1
r
0
r
Bits
Bit Name
Description
7
VOUT_OV_FAULT
Once output OVP occurs, this bit is set. This bit is in latch mode. The
CLEAR_FAULTS command can reset this bit.
6
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
5
VOUT_UV_WARNING
Once an output over-voltage warning occurs, this bit is set. This bit is in latch
mode. The CLEAR_FAULTS command can reset this bit.
4
VOUT_UV_FAULT
Once output UVP occurs, this bit is set. This bit is in latch mode. The
CLEAR_FAULTS command can reset this bit.
3
VOUT_MAX_MIN_
WARNING
Once
the
value
of
the
PMBus
command
VOUT_COMMAND,
VOUT_MARGIN_HIGH, or VOUT_MARGIN_LOW exceeds VOUT_MAX or
VOUT_MIN, this bit is set. This bit is in latch mode. The CLEAR_FAULTS
command can reset this bit.
2
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
1
LINE_FLOAT
During the EEPROM restore process after the chip powers on, the controller can
check if the output voltage remote sense pin is floating with this function enabled.
Once the controller detects that VOSEN is floating, it enters shutdown mode, and
this bit is set.
0
VDIFF_FAULT
During the soft-start process, once the MP2884A detects that VOSEN is greater
than VDIFF by 0.5V, the VR is shut down immediately, and this bit is set.
STATUS_IOUT (7Bh)
This register records the fault and warning status of the output current.
Command
Format
Bit
Access
Function
7
r
6
r
5
r
STATUS_IOUT
Unsigned binary
4
3
r
r
x
x
2
r
x
1
r
x
0
r
Bits
Bit Name
Description
7
IOUT_OC_FAULT
Once output OCP occurs, this bit is set. This bit is in latch mode. The
CLEAR_FAULTS command can reset this bit.
6
OC_UV_FAULT
If both output OCP and OVP occur, this bit is set. This bit is in latch mode. The
CLEAR_FAULTS command can reset this bit.
5
IOUT_OC_WARNING
Once an output OC warning occurs, this bit is set. This bit is in latch mode. The
CLEAR_FAULTS command can reset this bit.
4:1
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
0
POUT_OP_WARNING
Once output over-power protection (OPP) occurs, this bit is set. This bit is in
latch mode. The CLEAR_FAULTS command can reset this bit.
MP2884A Rev. 1.01
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12/25/2018
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65
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
STATUS_ INPUT (7Ch)
This register records the fault and warning status of the input voltage, input current, and input power.
Command
Format
Bit
Access
Function
7
r
6
r
x
5
r
STATUS_INPUT
Unsigned binary
4
3
r
r
2
r
x
1
r
x
0
r
x
Bits
Bit Name
Description
7
VIN_OV_FAULT
Once the sensed input voltage is greater than VIN_OV_FAULT_LIMIT (55h), this
bit is set. This bit is in latch mode. The CLEAR_FAULTS command can reset this
bit.
6
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
5
VIN_UV_WARNING
Once the sensed input voltage is less than VIN_UV_WARN_LIMIT (58h), this bit
is set. This bit is in latch mode. The CLEAR_FAULTS command can reset this
bit.
4
VIN_UVLO_LATCH
Once the sensed input voltage is less than VIN_OFF, the VR turns off the power,
and this bit is set. This bit is in latch mode. The CLEAR_FAULTS command can
reset this bit.
3
VIN_UVLO_LIVE
Once the sensed input voltage is less than VIN_OFF, this bit is set. Once the
sensed input voltage is greater than VIN_ON, this bit is reset. This bit is in live
mode.
2:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
STATUS_TEMPERATURE (7Dh)
This register records the fault and warning status of temperature.
Command
Format
Bit
Access
Function
7
r
6
r
5
r
x
STATUS_ TEMPERATURE
Unsigned binary
4
3
r
r
x
2
r
1
r
x
0
r
x
Bits
Bit Name
Description
7
TEMP_OT_FAULT
Once the sensed temperature via VTEMP is greater than VTEMP_OTP_LIMIT,
this bit is set. This bit is in latch mode. The CLEAR_FAULTS command can reset
this bit.
6
TEMP_OT_WARNING
Once
the
sensed
temperature
via
VTEMP
is
greater
than
VTEMP_OT_WARN_LIMIT, this bit is set. This bit is in latch mode. The
CLEAR_FAULTS command can reset this bit.
5:4
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
3
TSNS_OT_FAULT
Once the sensed temperature via TSNS is greater than the TSNS_OTP_LIMIT,
this bit is set. This bit is in latch mode. The CLEAR_FAULTS command can reset
this bit.
2
TSNS_OT_WARNING
Once
the
sensed
temperature
via
TSNS
is
greater
than
TSNS_OT_WARN_LIMIT, this bit is set. This bit is in latch mode. The
CLEAR_FAULTS command can reset this bit.
1:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
MP2884A Rev. 1.01
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66
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
STATUS_CML (7Eh)
This register records the fault status of PMBus communication and EEPROM operation.
Command
Format
Bit
Access
Function
7
r
6
r
5
r
STATUS_CML
Unsigned binary
4
3
r
r
2
r
1
r
0
r
Bits
Bit Name
Description
7
INVALID_CMD
This bit is set when it receives an unsupported command code. This bit is in latch
mode. The CLEAR_FAULTS command can reset this bit.
6
INVALID_DATA
This bit is set when it receives invalid or unsupported data (host sends too many
bytes). This bit is in latch mode. The CLEAR_FAULTS command can reset this
bit.
PEC_FAULT
The PMBus interface supports the use of a packet error checking (PEC) byte that
is defined in the SMBus standard. The PEC byte is transmitted by the MP2884A
during a read transaction or sent by the bus host to the MP2884A during a write
transaction. If the PEC byte sent during a write transaction is incorrect, the
command is not executed, and this bit is set. This bit is in latch mode. The
CLEAR_FAULTS command can reset this bit.
4
CRC_FAULT
During the process of storing memory data to the EEPROM, the MP2884A
calculates the CRC for each bit and saves the final CRC code to the EEPROM.
During the process of restoring the EEPROM data to the memory, the MP2884A
calculates the CRC code with each bit. The MP2884A checks the CRC results
when the restore process is done. If the CRC result is incorrect, the VR does not
start up, and this bit is set. This bit is in latch mode. The CLEAR_FAULTS
command can reset this bit
3
MEMORY_PWD_
MATCH
There is write protection for the PMBus registers. If enabled, the PMBus registers
can be read only and are not writeable. The register MFR_USER_PWD (04h)
stores the password. Once the key is matched with MFR_USER_PWD, this bit is
set. Otherwise, this bit is reset. This bit is in live mode.
FAULT_STORE_FLAG
This device automatically records fault statuses to the EEPROM. Once the
power shuts down for any protection, the fault status record process is triggered,
and this bit is set. This bit is in latch mode. The CLEAR_FAULTS command can
reset this bit.
CML_OTHER_FAULTS
If any of the below faults occur during PMBus communication, this bit is set.
1) Sending too few bits
2) Reading too few bits
3) Host sends or reads too few bytes
4) Reading too many bytes
This bit is in latch mode. The CLEAR_FAULTS command can reset this bit.
EEPROM_FAULTS
When restoring data from the EEPROM to the memory, this bit first checks the
signature register in address 00h of the EEPROM. If the signature is not
matched, this process is ceased immediately, and this bit is set. This bit is in
latch mode. The CLEAR_FAULTS command can reset this bit.
5
2
1
0
MP2884A Rev. 1.01
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67
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
READ_VIN (88h)
This register records the sensed input voltage.
Command
READ_VIN
Format
Bit
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Function
x
x
x
x
x
x
READ_VIN
Bits
Bit Name
Description
15:10
RESERVED
Unused. Fixed to 111011.
9:0
READ_VIN
0.03125V/LSB.
READ_VOUT (8Bh)
This register records the sensed output voltage.
Command
READ_VOUT
Format
Bit
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Function
x
x
x
x
READ_VOUT
Bits
Bit Name
Description
15:12
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
11:0
READ_VOUT
1mV/LSB.
READ_IOUT (8Ch)
This register records the sensed output current.
Command
READ_IOUT
Format
Bit
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Function
x
x
x
x
READ_IOUT
Bits
Bit Name
Description
15:12
RESERVED
Unused. Fixed to 1110.
11:0
READ_IOUT
0.25A/LSB (TOTAL_CURRENT_RESOLUTION = 0)
0.5A/LSB (TOTAL_CURRENT_RESOLUTION = 1)
READ_TEMPERATURE (8Dh)
This register records the sensed temperature.
Command
READ_TEMPERATURE
Format
Bit
Unsigned binary
15
14
13
12
11
10
9
8
7
r
r
r
r
Access
r
r
r
r
r
Function
x
x
x
x
x
6
5
4
3
2
1
0
r
r
r
r
r
r
r
READ_TEMPERATURE
MP2884A Rev. 1.01
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68
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
Bit Name
Description
15:11
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
10:0
READ_TEMPERATURE
0.1°C/LSB.
READ_EFFECIENCY (95h)
This register records the calculated efficiency of the VR.
Command
READ_EFFECIENCY
Format
Bit
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Function
x
x
x
x
x
x
x
READ_EFFECIENCY
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8:0
READ_EFFECIENCY
0.195%/LSB.
READ_POUT (96h)
This register records the sensed output power.
Command
READ_POUT
Format
Bit
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Function
x
x
x
x
x
READ_POUT
Bits
Bit Name
Description
15:11
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
10:0
READ_POUT
0.5W/LSB (TOTAL_CURRENT_RESOLUTION = 0)
1W/LSB (TOTAL_CURRENT_RESOLUTION = 1)
READ_PIN (97h)
This register records the calculated input power.
Command
READ_PIN
Format
Bit
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Function
x
x
x
x
x
READ_PIN
Bits
Bit Name
Description
15:11
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
10:0
READ_PIN
0.5W/LSB (TOTAL_CURRENT_RESOLUTION = 0)
1W/LSB (TOTAL_CURRENT_RESOLUTION = 1)
MP2884A Rev. 1.01
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69
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_ APS_FS_LIMIT1 (A3h)
This register sets the interval time threshold between the consecutive phases' PWM rising edges to
detect a fast load increase. When APS is enabled and the system sheds phases, once the interval time
is lower than this threshold, the VR exits phase shedding and runs with a full phase for a configurable
amount of time.
Command
Format
Bit
Access
Function
15
r/w
14
r/w
13
r/w
12
r/w
11
r/w
10
r/w
MFR_APS_FS_LIMIT1
Unsigned binary
9
8
7
6
r/w
r/w
r/w
r/w
5
r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
Bits
Bit Name
Description
15:8
FS_LIMIT_4P
Threshold of the interval time between consecutive phases' PWM rising edges
when the VR has shed to four phases. 5ns/LSB.
Add PHASE_BLANK_TIME to the final threshold.
7:0
Threshold of the interval time between consecutive phases' PWM rising edges
when the VR has shed to three phases. 5ns/LSB.
FS_LIMIT_3P
Add PHASE_BLANK_TIME to the final threshold.
MFR_APS_FS_LIMIT2 (A4h)
This register sets the interval time threshold between the consecutive phases' PWM rising edges to
detect a fast load increase. When APS is enabled and the system sheds phases, once the interval time
is lower than this threshold, the system exits phase shedding and runs with a full phase for a
configurable amount of time.
Command
Format
Bit
Access
Function
15
r/w
14
r/w
13
r/w
12
r/w
11
r/w
10
r/w
MFR_APS_FS_LIMIT2
Unsigned binary
9
8
7
6
r/w
r/w
r/w
r/w
5
r/w
4
r/w
x
3
r/w
2
r/w
1
r/w
0
r/w
x
Bits
Bit Name
Description
15:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
7:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
MFR_APS_FS_LIMIT3 (A5h)
This register sets the interval time threshold between the consecutive phases' PWM rising edges to
detect a fast load increase. When APS is enabled and the system sheds phases, once the interval time
is lower than this threshold, the system exits phase shedding and runs with a full-phase for a
configurable amount of time.
Command
Format
Bit
Access
Function
15
r/w
14
r/w
13
r/w
12
r/w
11
r/w
x
10
r/w
MFR_APS_FS_LIMIT3
Unsigned binary
9
8
7
6
r/w
r/w
r/w
r/w
5
r/w
4
r/w
3
r/w
2
r/w
1
r/w
0
r/w
x
MP2884A Rev. 1.01
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70
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
Bit Name
Description
15:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
7:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
MFR_APS_FS_LIMIT4 (A6h)
This register sets the interval time threshold between the consecutive phases' PWM rising edges to
detect a fast load increase. When APS is enabled and the system sheds phases, once the interval time
is lower than this threshold, the system exits phase shedding and runs with a full-phase for a
configurable amount of time.
Command
MFR_APS_FS_LIMIT4
Format
Unsigned binary
Bit
15
14
13
12
Access
r/w
r/w
r/w
r/w
Function
11
10
9
8
7
6
5
4
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
3
2
1
0
r/w
r/w
r/w
r/w
x
Bits
Bit Name
Description
15:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
7:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
MFR_APS_FS_CTRL1 (A7h)
This register sets the interval time threshold for phase 1's PWM to detect a fast load increase. When
APS is enabled and the system sheds phases, once the controller detects that the PWM interval is
lower than this threshold, the system exits phase shedding and runs with a full-phase for a configurable
amount of time. This register also sets the enable bit for the exit-phase-shedding strategy via PWM
frequency detection.
Command
MFR_APS_FS_CTRL1
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
Function
Bits
Bit Name
Description
15:13
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
FS_EXIT_APS_EN1
Enable bit of exit-phase-shedding according to phase 1’s PWM interval time.
0: disable
1: enable
The controller detects phase 1’s PWM interval time from the end of
MIN_OFF_TIME.
FS_EXIT_APS_EN2
Enable bit of exit-phase-shedding according to the PWM interval time between
consecutive phases.
0: disable
1: enable
The controller detects the consecutive phases' PWM interval time from the end of
PHASE_BLANK_TIME.
12
11
MP2884A Rev. 1.01
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
10:8
FS_EXIT_APS_CNT1
Continuous counting threshold for exit-phase-shedding according to phase 1’s
PWM interval time.
7:0
FS_LIMIT_1P
Threshold of phase 1’s PWM interval time. 5ns/LSB.
Add MIN_OFF_TIME to the final threshold.
MFR_APS_FS_CTRL2 (A8h)
This register sets the threshold of the interval time between the consecutive phases' PWM rising edges
to detect a fast load increase. When APS is enabled and the system sheds phases, once the controller
detects that the PWM interval is lower than this threshold, the system exits phase shedding and runs
with a full phase for a configurable amount of time. This register also sets the full-phase running time
from exiting phase shedding to returning to phase-shedding mode.
Command
MFR_APS_FS_CTRL2
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
x
Bits
Bit Name
Description
15
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
14:11
RETURN_APS_DELAY
Delay time for returning APS from exiting phase shedding due to the PWM
interval time being shorter than the configured threshold. 20µs/LSB.
10:8
FS_EXIT_APS_CNT2
Continuous counting time threshold for exit-phase-shedding mode according to
the PWM interval time between consecutive phases.
7:0
FS_LIMIT_2P
Threshold of the interval time between consecutive phases' PWM rising edges
when the VR has shed to two phases. 5ns/LSB.
Add PHASE_BLANK_TIME to the final threshold.
MFR_PHASE_SHED_CTRL (A9h)
This register sets the checking time for phase shedding by detecting the output current and set
compensation to reduce voltage undershoot during phase dropping.
Command
MFR_PHASE_SHED_CTRL
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Bits
APS_DROP_CHECK_CNT
EXIT_VO_CMPN_STEP_TIME
Bit Name
Description
15:9
APS_DROP_CHECK_
CNT
Continuous counting-times threshold for phase shedding when the APS function
is enabled. Once the output current enters the drop-phase window, an internal
timer starts counting until it reaches this counting-times threshold. Then the VR
drops phases. The timer resets if the output current exits the drop-phase window
before it reaches the counting-times threshold.
8:4
EXIT_VO_CMPN_STEP
_TIME
Interval time for reducing each 1.37mV step for VOUT compensation when the
phase-dropping process ends. 50ns/LSB.
3:0
DROP_PHASE_VO_
CMPN
VOUT undershoot compensation value for phase dropping. 1.37mV/LSB.
MP2884A Rev. 1.01
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12/25/2018
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72
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_LOW_PHASE_CNT (AAh)
This register sets the phase number when PSI is low (low-phase mode).
Command
MFR_LOW_PHASE_CNT
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
x
Function
Bits
Bit Name
Description
15:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
7:4
LOW_PHASE_CNT_
WARM
Phase number in low-phase mode (PSI is low) for warm boot. First time poweron after POR is considered to be a cool boot.
3:0
LOW_PHASE_CNT_
COLD
Phase number in low-phase mode (PSI is low) for cold boot. Boot-up process
beside the first power-on after POR is considered to be a warm boot.
MFR_APS_CTRL (ABh)
This register configures the detailed performance related to APS.
MFR_APS_CTRL
Command
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
RETURN_APS_DELAY
DROP_PHASE_INTERVAL
Bits
Bit Name
Description
15:10
RETURN_APS_DELAY
Delay time for returning APS from exiting phase shedding due to phase 1
triggering the valley current limit when the system runs at 1-phase or VFB drops
below VREF - 25mV. 20µs/LSB.
9
8
N25MV_EXIT_EN
PRD_EXIT_EN
7
OC_EXIT_EN
6:1
DROP_PHASE_
INTERVAL
Enable bit for exiting phase shedding (jumping to full-phase running) due to VFB
dropping below VREF - 25mV when APS mode is enabled.
0: disable
1: enable
Enable bit for exiting phase-shedding (jumping to full-phase running) due to the
PWM interval being shorter than the configured threshold.
0: disable
1: enable
Enable bit for exiting phase-shedding (jumping to full-phase running) due to
phase 1 triggering the valley current limit when the system runs at 1-phase.
0: disable
1: enable
Interval time between dropping two adjacent phases when drop-phase mode is
dropping sequentially (bit[0] = 1). 1µs/LSB.
Drop-phase mode selector.
0
DROP_PHASE_MODE
0: phases drop together
1: phases drop one-by-one with interval time determined by bit[6:1]
MP2884A Rev. 1.01
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12/25/2018
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73
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_REPORT_CTRL (ADh)
This register controls the reporting mode for READ_VIN, READ_VOUT, READ_IOUT, READ_PIN,
READ_POUT, READ_EFFECIENCY, READ_TON, and READ_SWITCH_PRD.
Command
MFR_REPORT_CTRL
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
Function
Bits
Bit Name
Description
15:12
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Reporting mode selector.
00: average mode
01: real-time mode
1x: latch mode. Send the command START_CATCH_AVE to trigger the
averaging process within the average window. At the end of the average window,
the average results are latched.
When reporting mode is set to real time or latch, some registers that do not have
real time or latch mode report with average mode.
11:10
READ_TEMPERATURE is always in real-time mode.
REPORT_MODE
Average
mode
READ_VIN
READ_VOUT
READ_IOUT
READ_TEMPERATURE
READ_EFFICIENCY
READ_POUT
READ_PIN
9:0
AVE_WINDOW
Real-time
mode
Latch mode
Averaging window for reporting. 100µs/LSB.
MFR_PWMVID_TARGET_CTRL (AEh)
This register sets the relationship between the PWM-VID duty and target output voltage.
Command
MFR_PWMVID_TARGET_CTRL
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
Function
Bits
Bit Name
Description
15:11
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Time constant of the digital low-pass filter for sensing the PWM frequency and
on-time used for efficiency calculation.
10:9
TON_PRD_FIL_SEL
00: (500kHz / Fs) x 6ms
01: (500kHz / Fs) x 12ms
10: (500kHz / Fs) x 24ms
11: (500kHz / Fs) x 48ms
Fs is the configured PWM frequency.
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
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© 2018 MPS. All Rights Reserved.
74
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
8:6
Delay time from when DVID completes to when the internal DVID flag resets.
20µs/LSB.
DVID_FLAG_DELAY
If the output voltage is in PMBus-controlling mode (VID_CONTROL_MODE = 1),
this register is ignored (delay time is zero).
Gain mode selector for target VID calculation. The target output voltage is
calculated by the defined register VOUT_MIN (1Fh), real-time PWM-VID on-time,
and a GAIN factor as shown below:
VID_TARGET = PWMVID_ON_TIME GAIN + VOUT_MIN
5
DUTY_TO_VID_GAIN_
MODE
0: always use the register value from DUTY_TO_VID_GAIN (B3h)
1: update the current GAIN by the real-time calculated value when the error
between the latest calculated GAIN and the current GAIN exceeds
DUTY_TO_VID_GAIN_HYS (but is still within ±10% deviation from the current
GAIN). In this case, the register DUTY_TO_VID_GAIN (B3h) is used as the initial
GAIN.
Averaging window of digital filter for VID_TARGET calculation.
4:3
2:0
DUTY_TO_VID_GAIN_
FIL_SEL
DUTY_TO_VID_GAIN_
HYS
00: average of four points
01: average of eight points
10: average of 16 points
11: average of 32 points
Gain hysteresis used to update the current GAIN for the target VID calculation if
DUTY_TO_VID_GAIN_SEL = 1. When the error between the latest calculated
GAIN and current GAIN exceeds this hysteresis (but is still within the 10%
deviation from the current GAIN), the current GAIN is updated by the mostrecently calculated one. In this case, the register DUTY_TO_VID_GAIN (B3h) is
used as the initial GAIN.
MFR_PWMVID_UP_COMP (AFh)
This register sets VID compensation for upward DVID.
Command
MFR_PWMVID_UP_COMP
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Bits
DVID_UP_CMPN
Bit Name
DVID_UP_END_THRE
Description
PWM-VID duty compensation value based on the desired compensation step.
This bit is added in the detected PWM-VID duty during upward DVID.
15:5
DVID_UP_CMPN
DVID_UP_CMPN =
VID_CMPN_STEP + 2
212
VOUT_MAX - VOUT_MIN
VOUT_MAX (24h) and VOUT_MIN (1Fh) are in VID format.
Enable bit of the extra VID step for upward DVID.
4
3:0
DVID_UP_CMPN_EN
DVID_UP_END_THRE
0: disable
1: enable
Threshold for the upward DVID ending indicator. During upward DVID, the
controller uses the output of the first-stage filter as VO_REF. When the current
VO_REF is greater than the calculated VID_TARGET - DVID_UP_END_THRE,
this bit switches to the output of the second-stage filter.
DVID_UP_START_THRE must be greater than DVID_UP_END_THRE.
MP2884A Rev. 1.01
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12/25/2018
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© 2018 MPS. All Rights Reserved.
75
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_PWMVID_MAX_DUTY (B0h)
This register sets the PWM-VID on-time threshold used to indicate 100% PWM-VID duty.
Command
MFR_PWMVID_MAX_DUTY
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
Function
PWMVID_MAX_DUTY
Bits
Bit Name
Description
15:10
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
9:1
PWMVID_MAX_DUTY
PWM-VID on-time threshold to indicate 100% PWM-VID duty. When the
detected PWM-VID on time is greater than this threshold, the controller considers
the current PWM-VID duty to be 100%. 10ns/LSB.
0
PWMVID_HIGHLOW_
DET_EN
Enable bit for PWM-VID constant high/low detection.
0: disable
1: enable
MFR_PWMVID_FLTR_CTRL1 (B1h)
This register sets the performance of the digital PWM-VID filters.
Command
MFR_PWMVID_FLTR_CTRL1
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Bits
15:13
Bit Name
DVID_DOWN_START_
THRE
Description
Threshold for the downward DVID starting indicator (DVID_TRIG_MODE = 0).
When VOUT is settled, the controller uses the output of the second-stage filter as
VO_REF. When the calculated VID_TARGET is less than the current VO_REF DVID_DOWN_START_THRE, the controller enters the downward DVID, and
VO_REF switches to the first-stage filter output.
DVID_DOWN_START_THRE must be greater than DVID_DOWN_END_THRE.
12:10
DVID_UP_START_
THRE
Threshold for the upward DVID starting indicator (DVID_TRIG_MODE = 0).
When VOUT is settled, the controller uses the output of the second-stage filter as
VO_REF. When the calculated VID_TARGET is greater than the current
VO_REF + DVID_UP_START_THRE, the controller enters the upward DVID,
and VO_REF switches to the output of the first-stage filter.
DVID_UP_START_THRE must be greater than DVID_UP_END_THRE.
9:7
DVID_DOWN_END_
THRE
Threshold for the downward DVID ending indicator. During the downward DVID,
the controller uses the output of the first-stage filter as VO_REF. When the
current VO_REF is less than the calculated VID_TARGET +
DVID_DOWN_END_THRE, this bit switches to the output of the second-stage
filter.
DVID_DOWN_START_THRE must be greater than DVID_DOWN_END_THRE.
MP2884A Rev. 1.01
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12/25/2018
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76
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Check time of the synchronizing function of the second-stage PWM-VID filter to
improve output voltage accuracy after DVID. 100µs/LSB.
6:2
The second-stage PWM-VID filter uses an internal hysteresis module to avoid
jitter on its output. When the output remains unchanged for this checking time,
the hysteresis module synchronizes its output with the input to eliminate small
DC errors.
FILT2_CHECK_TIME
Averaging window of the second-stage PWM-VID filter.
1:0
00: average of 512 points
01: average of 1024 points
10: average of 2048 points
11: average of 4056 points
SECOND_FIL_AVE
MFR_PWMVID_FLTR_CTRL2 (B2h)
This register sets the performance of the digital PWM-VID filters.
Command
MFR_PWMVID_FLTR_CTRL2
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Bits
Bit Name
Description
DVID trigger mode selector.
15
DVID_TRIG_MODE
0: according to the relationship between the calculated VID_TARGET and
current VO_REF
1: according to whether the real-time counted PWM-VID on-time changes more
than the threshold set in bit[5:3] or bit[2:0]
Enable bit for the synchronizing function of the second stage PWM-VID filter to
improve output voltage accuracy after DVID.
14
FILT2_SYNC_EN
0: disable
1: enable
The second stage PWM-VID filter uses an internal hysteresis module to avoid
jitter on its output. When the output remains unchanged for this checking time,
the hysteresis module synchronizes its output with the input to eliminate small
DC errors.
13:10
DVID_DOWN_THRE
DVID direction identification threshold for downward DVID. When the current
VO_REF is greater than VID_TARGET + DVID_DOWN_THRE, the controller
considers the DVID to be downward.
9:6
DVID_UP_THRE
DVID direction identification threshold for upward DVID. When the current
VO_REF is less than VID_TARGET - DVID_UP_THRE, the controller considers
the DVID to be upward.
TON_CHANGE_THRE_
N
Threshold for the downward DVID starting indicator (DVID_TRIG_MODE = 1).
When VOUT is settled, the controller uses the output of the second stage filter as
VO_REF. When the detected on-time negative variation of PWM-VID is greater
than TON_CHANGE_THRE_N, the controller enters downward DVID, and
VO_REF switches to the first- stage filter output. 5ns/LSB.
TON_CHANGE_THRE_
P
Threshold for the upward DVID starting indicator (DVID_TRIG_MODE = 1).
When VOUT is settled, the controller uses the output of the second-stage filter as
VO_REF. When the detected on-time positive variation of PWM-VID is greater
than TON_CHANGE_THRE_P, the controller enters upward DVID, and VO_REF
switches to the first-stage filter output. 5ns/LSB.
5:3
2:0
MP2884A Rev. 1.01
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12/25/2018
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© 2018 MPS. All Rights Reserved.
77
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_DUTY_TO_VID_GAIN (B3h)
This register is the initial parameter for the target voltage calculation.
Command
MFR_DUTY_TO_VID_GAIN
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
Function
DUTY_TO_VID_GAIN
Bits
Bit Name
Description
15:11
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Initial parameter for the VID_TARGET calculation. It is calculated according to
the period of PWM-VID, VOUT_MAX, and VOUT_MIN:
DUTY_TO_VID_GAIN =
10:0
VOUT_MAX-VOUT_MIN
29
PWM_VID_PERIOD(ns)/5(ns)
VOUT_MAX (24h) and VOUT_MIN (1Fh) are in VID format.
DUTY_TO_VID_GAIN
VID_TARGET is calculated by the register VOUT_MIN (1Fh), real-time PWMVID on-time, and DUTY_ ADC sense of VDIFF, and VFB TO_VID_GAIN:
VID_TARGET =
PWM-VID_ON_TIME DUTY_TO_VID_GAIN + VOUT_MIN
MFR_PARM_VOUT_MIN (B4h)
This register is a parameter corresponding to VOUT_MIN.
Command
MFR_PARM_VOUT_MIN
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Bits
PARM_VOUT_MIN
Bit Name
Description
The parameter corresponds to VOUT_MIN:
15:0
PARM_VOUT_MIN =
PARM_VOUT_MIN
VOUT_MIN
211
VOUT_MAX - VOUT_MIN
VOUT_MAX (24h) and VOUT_MIN (1Fh) are in VID format.
MFR_PARM_RC_CONST (B5h)
This register is the parameter corresponding to the desired output voltage slew rate during boot-up and
DVID.
Command
MFR_PARM_RC_CONST
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
Function
BOOT_RC
DVID_RC
MP2884A Rev. 1.01
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12/25/2018
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© 2018 MPS. All Rights Reserved.
78
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
Bit Name
Description
15:12
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
The parameter corresponds to the desired time constant of the PWM-VID lowpass filter in the boot-up process:
11:6
BOOT_RC =
BOOT_RC
320(ns)
211
BOOT (ns)
Where τBOOT is the desired time constant of the PWM-VID low-pass filter in the
boot-up process.
The parameter corresponds to the desired time constant of the PWM-VID lowpass filter in the DVID process:
5:0
DVID_RC =
DVID_RC
320(ns)
DVID (ns)
211
Where τDVID is the desired time constant of the PWM-VID low-pass filter in the
DVID process.
MFR_PARM_VBOOT_DUTY (B6h)
This register is the parameter corresponding to desired VBOOT for PWM-VID mode.
Command
MFR_PARM_VBOOT_DUTY
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Bits
VBOOT_DUTY
Bit Name
Description
The parameter corresponds to the desired VBOOT:
15:0
VBOOT_DUTY =
VBOOT_DUTY
VBOOT-VOUT_MIN
216
VOUT_MAX-VOUT_MIN
VBOOT (BBh), VOUT_MAX (24h), and VOUT_MIN (1Fh) are all in VID format.
MFR_PARM_SLEW_TRAN (B7h)
This register is the parameter corresponding to DVID_RC in MFR_PARM_RC_CONST (B5h).
Command
MFR_PARM_SLEW_TRAN
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Bits
DVID_RC_PARM
Bit Name
Description
The parameter corresponds to DVID_RC in MFR_PARM_RC_CONST (B5h):
15:0
DVID_RC_PARM
DVID_RC_PARM =
1
2 24
DVID_RC (VOUT_MAX-VOUT_MIN)
VOUT_MAX (24h) and VOUT_MIN (1Fh) are all in VID format.
MP2884A Rev. 1.01
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12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
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79
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_PARM_BOOT_TRAN (B8h)
This register is the parameter corresponding to BOOT_RC in MFR_PARM_RC_CONST (B5h).
Command
MFR_PARM_BOOT_TRAN
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Bits
BOOT_RC_PARM
Bit Name
Description
The parameter corresponds to BOOT_RC in MFR_PARM_RC_CONST (B5h):
15:0
BOOT_RC_PARM =
BOOT_RC_PARM
1
2 24
BOOT_RC (VOUT_MAX-VOUT_MIN)
VOUT_MAX (24h) and VOUT_MIN (1Fh) are all in VID format.
MFR_BOOT_SR (B9h)
This register sets the output voltage slew rate for linear boot-up.
Command
MFR_BOOT_SR
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
Function
Bits
Bit Name
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
LINEAR_BOOT_SR_CNT
Description
Sets the linear boot-up slew rate.
LINEAR_BOOT_SR_CNT =
9:0
LINEAR_BOOT_SR_
CNT
6.25mV
SR BOOT 50ns
Bit[0] of MFR_VR_CONFIG2 (E2h) sets the boot-up and DVID mode.
VO_SR_MODE_SEL= 0: linear mode
VO_SR_MODE_SEL= 1: R-C filter mode
Set LINEAR_BOOT_SR_CNT to 0002h when VO_SR_MODE_SEL= 1 (R-C filter
mode).
MFR_SLEW_SR (BAh)
This register sets the output voltage slew rate for linear DVID.
Command
MFR_SLEW_SR
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
Function
LINEAR_DVID_SR_CNT
MP2884A Rev. 1.01
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12/25/2018
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© 2018 MPS. All Rights Reserved.
80
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
Bit Name
Description
Sets the linear DVID slew rate.
LINEAR_DVID_SR_CNT =
9:0
LINEAR_DVID_SR_
CNT
6.25mV
SR DVID 50 ns
Bit[0] of MFR_VR_CONFIG2 (E2h) sets the boot-up and DVID mode.
VO_SR_MODE_SEL= 0: linear mode
VO_SR_MODE_SEL= 1: R-C filter mode
Set LINEAR_DVID_SR_CNT to 0002h when VO_SR_MODE_SEL= 1 (R-C filter
mode).
MFR_VBOOT (BBh)
This register is used to set the boot voltage for PWM-VID mode. It is in VID format.
Command
MFR_VBOOT
Format
VID
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
Function
VBOOT
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8:0
VBOOT
Boot voltage for PWM-VID mode. 6.25mV/LSB.
MFR_VID_SD (BCh)
This register sets the VID threshold to set all PWMs to tri-state during soft shutdown or the DVID-tozero process.
Command
MFR_VID_SD
Format
VID
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
Function
VID_SHUT_DOWN
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8:0
VID_SHUT_DOWN
VID threshold to set all PWMs to tri-state during soft shutdown or the DVID-tozero process. 6.25mV/LSB.
MFR_FS (BDh)
This register sets the PWM frequency.
Command
MFR_FS
Format
VID
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
Function
MFR_FS
MP2884A Rev. 1.01
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12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
81
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8:0
MFR_FS
10kHz/LSB.
MFR_PMBUS_ADDR (BEh)
This register sets the PMBus address for the controller.
Command
Format
Bit
Access
Function
7
r/w
MODE
6
r/w
MFR_PMBUS_ADDR
Unsigned binary
4
3
r/w
r/w
5
r/w
ADDR_MSB
Bits
Bit Name
7
ADDR_LSB_MODE
0: set by ADDR
1: set by register
6:4
ADDR_MSB
MSB of address.
3:0
ADDR_LSB
LSB of address.
2
1
r/w
r/w
ADDR_LSB
0
r/w
Description
ADDR_LSB mode selector.
MFR_VIN_SENSE_OFFSET (BFh)
This register sets input voltage sensing offset and input power loss calibrating parameter.
Command
MFR_VIN_SENSE_OFFSET
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Bits
PWR_LOSS_OFFSET
Bit Name
VIN_SENSE_OFFSET
Description
Power loss offset for the input power report and efficiency calculation.
15:8
PWR_LOSS_OFFSET
0.5W/LSB (TOTAL_CURRENT_RESOLUTION = 0)
1W/LSB (TOTAL_CURRENT_RESOLUTION = 1)
Input voltage sensing offset:
7:0
VIN_SENSE_OFFSET
Vin_offset =
1.6 VIN_SENSE_OFFSET (R TOP + R BOTTOM )
1024 R BOTTOM
Where Vin_offset is the target offset on the input voltage sensing, and RTOP and
RBOTTOM are the resistor divider for input voltage sensing. Bit[7] is the sign bit.
MFR_VIN_SCALE_LOOP (C0h)
This register sets the ratio of the resistor divider for the input voltage sensing.
Command
Format
Bit
Access
Function
7
r/w
6
r/w
5
r/w
MFR_VIN_SCALE_LOOP
Unsigned binary
4
3
r/w
r/w
VIN_SENSE_SCALE
2
r/w
1
r/w
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
0
r/w
82
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
Bit Name
Description
Parameter used to set the input voltage sensing scale.
7:0
VIN_SENSE_SCALE
VIN_SENSE_SCALE=
1024 VINSEN
1024 R BOTTOM
=
VIN
R TOP + R BOTTOM
MFR_TEMP_GAIN_OFFSET (C1h)
This register sets the gain and offset for temperature sensing via VTEMP.
Command
MFR_TEMP_GAIN_OFFSET
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
x
VTEMP_OFFSET
VTEMP_GAIN
Bits
Bit Name
Description
15
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Offset used to report the temperature from VTEMP:
14:8
VTEMP_OFFSET =
VTEMP_OFFSET
DrMOS_TEMP_OFFSET
DrMOS_TEMP_GAIN
Assuming that:
VTEMP = DrMOS_TEMP_GAIN Temperature - DrMOS_TEMP_OFFSET
Gain used to report the temperature from VTEMP. VTEMP has an internal 1/2
divider before ADC:
7:0
VTEMP_GAIN =
VTEMP_GAIN
2 1.6 2 9 1000
DrMOS_TEMP_GAIN 1024
Assuming that:
VTEMP = DrMOS_TEMP_GAIN Temperature - DrMOS_TEMP_OFFSET
MFR_CUR_GAIN (C2h)
This register sets the gain for phase-current sensing.
Command
MFR_CUR_GAIN
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
Function
PHASE_CUR_GAIN
Bits
Bit Name
Description
15:10
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Gain for phase-current sensing.
9:0
PHASE_CUR_GAIN
PHASE_CUR_GAIN = KCS x RCS x 213 (PHASE_CURRENT_RESOLUTION = 0)
PHASE_CUR_GAIN = KCS x RCS x 214 (PHASE_CURRENT_RESOLUTION = 1)
Where RCS is the phase-current sensing resistor, and KCS is the current sensing
gain of the DrMOS.
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
83
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_BLANK_TIME (C5h)
This register sets the minimum interval time between consecutive phases' PWM rising edges and the
discharging time of slope compensation capacitors.
Command
MFR_BLANK_TIME
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
Function
SLOPE_BLANK_TIME
PHASE_BLANK_TIME
Bits
Bit Name
Description
15:12
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
11:6
SLOPE_BLANK_TIME
5:0
PHASE_BLANK_TIME
Discharging time of slope compensation capacitors. 5ns/LSB.
SLOPE_BLANK_TIME must be less than or equal to PHASE_BLANK_TIME.
Minimum interval time between consecutive phases' PWM rising edges.
5ns/LSB.
PHASE_BLANK_TIME must be greater than SLOPE_BLANK_TIME.
MFR_SLOPE_SR_DCM (C6h)
This register sets the slew rate of slope compensation for 1-phase DCM.
Command
MFR_SLOPE_SR_DCM
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
x
x
x
Function
CURRENT_SOURCE
Bits
Bit Name
Description
15:6
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
5:0
CURRENT_SOURCE
Current source value for slope compensation. 0.25µA/LSB.
Calculate the slope compensation slew rate with Equation (23):
VS L O P E @ D C M
0 .2 5(μ A ) C U R R E N T _ S O U R C E
(TS W TB L A N K )
1 6 1 .8 5 (p F )
(23)
Where VSLOPE@DCM is the desired voltage of slope compensation for 1-phase DCM, TSW is the PWM
period determined by register MFR_FS (BDh), and TBLANK is SLOPE_BLANK_TIME set in register
MFR_BLANK_TIME (C5h).
If setting VDIFF_GAIN_SEL (2Ah) = 1 to get a half gain for the remote sense amplifier, VSLOPE should
be doubled.
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
84
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_SLOPE_CNT_DCM (C7h)
This register sets the maximum ramping time of slope compensation for 1-phase DCM. Once the timer
is over, the current source turns off, and the slope compensation voltage is held.
Command
MFR_SLOPE_CNT_DCM
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
Function
SLOPE_CNT
Bits
Bit Name
Description
15:10
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Maximum ramping time of slope compensation for 1-phase DCM. 5ns/LSB.
9:0
SLOPE _ CNT
SLOPE_CNT
1.3 (TSW TBLANK )(ns)
5(ns)
Where TSW is the PWM period determined by register MFR_FS (BDh), and
TBLANK is SLOPE_BLANK_TIME set in register MFR_BLANK_TIME (C5h).
Figure 19: Slope Compensation for 1-Phase DCM
MFR_SLOPE_SR_10P (C8h)
This register sets the slew rate of slope compensation for 10-phase status.
Command
MFR_SLOPE_SR_10P
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
Function
x
x
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8:6
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
5:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
85
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Calculate the slope compensation slew rate with Equation (24):
VSLOPE@10P
0.25(μA) CURRENT_SOURCE TSW
(
TBLANK )
( 8 - CAP ) 1.85(pF)
10
(24)
Where VSLOPE@10P is the desired voltage of slope compensation for 10-phase, TSW is the PWM period
determined by register MFR_FS (BDh), and TBLANK is SLOPE_BLANK_TIME set in register
MFR_BLANK_TIME (C5h).
If setting VDIFF_GAIN_SEL (2Ah) = 1 to get a half gain for the remote sense amplifier, VSLOPE should
be doubled.
MFR_SLOPE_CNT_10P (C9h)
This register sets the maximum ramping time of slope compensation for 10-phase status. Once the
timer ends, the current source turns off, and the slope compensation voltage is held.
Command
MFR_SLOPE_CNT_10P
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
x
Function
x
Bits
Bit Name
Description
15:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
7:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
MFR_SLOPE_SR_9P (CAh)
This register sets the slew rate of slope compensation for 9-phase status.
Command
MFR_SLOPE_SR_9P
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
Function
x
x
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8:6
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
5:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Calculate the slope compensation slew rate with Equation (25):
VSLOPE@9P
0.25(μA) CURRENT_SOURCE TSW
(
TBLANK )
( 8 - CAP ) 1.85(pF)
9
(25)
Where VSLOPE@9P is the desired voltage of slope compensation for 9-phase status, TSW is the PWM
period determined by register MFR_FS (BDh), and TBLANK is SLOPE_BLANK_TIME set in register
MFR_BLANK_TIME (C5h).
If setting VDIFF_GAIN_SEL (2Ah) = 1 to get a half gain for the remote sense amplifier, VSLOPE should
be doubled.
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
86
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_SLOPE_CNT_9P (CBh)
This register sets the maximum ramping time of slope compensation for 9-phase status. Once the timer
is over, the current source turns off, and the slope compensation voltage is held.
Command
MFR_SLOPE_CNT_9P
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
x
Function
x
Bits
Bit Name
Description
15:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
7:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
MFR_SLOPE_SR_8P (CCh)
This register sets the slew rate of slope compensation for 8-phase status.
Command
MFR_SLOPE_SR_8P
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
Function
x
x
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8:6
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
5:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Calculate the slope compensation slew rate with Equation (26):
VSLOPE@8P
0.25(μA) CURRENT_SOURCE TSW
(
TBLANK )
( 8 - CAP ) 1.85(pF)
8
(26)
Where VSLOPE@8P is the desired voltage of slope compensation for 8-phase status, TSW is the PWM
period determined by register MFR_FS (BDh), and TBLANK is SLOPE_BLANK_TIME set in register
MFR_BLANK_TIME (C5h).
If setting VDIFF_GAIN_SEL (2Ah) = 1 to get a half gain for the remote sense amplifier, VSLOPE should
be doubled.
MFR_SLOPE_CNT_8P (CDh)
This register sets the maximum ramping time of slope compensation for 8-phase status. Once the timer
is over, the current source turns off, and the slope compensation voltage is held.
Command
MFR_SLOPE_CNT_8P
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
x
Function
x
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
87
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
Bit Name
Description
15:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
7:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
MFR_SLOPE_SR_7P (CEh)
This register sets the slew rate of slope compensation for 7-phase status.
Command
MFR_SLOPE_SR_7P
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
Function
x
x
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8:6
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
5:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Calculate the slope compensation slew rate with Equation (27):
VSLOPE@7P
0.25(μA) CURRENT_SOURCE TSW
(
TBLANK )
( 8 - CAP ) 1.85(pF)
7
(27)
Where VSLOPE@7P is the desired voltage of slope compensation for 7-phase status, TSW is the PWM
period determined by register MFR_FS (BDh), and TBLANK is SLOPE_BLANK_TIME set in register
MFR_BLANK_TIME (C5h).
If setting VDIFF_GAIN_SEL (2Ah) = 1 to get a half gain for the remote sense amplifier, VSLOPE should
be doubled.
MFR_SLOPE_CNT_7P (CFh)
This register sets the maximum ramping time of slope compensation for 7-phase status. Once the timer
is over, the current source turns off, and the slope compensation voltage is held.
Command
MFR_SLOPE_CNT_7P
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
x
Function
3
2
1
0
r/w
r/w
r/w
r/w
x
Bits
Bit Name
Description
15:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
7:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
88
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_SLOPE_SR_6P (D0h)
This register sets the slew rate of slope compensation for 6-phase status.
Command
MFR_SLOPE_SR_6P
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
Function
x
x
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8:6
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
5:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Calculate the slope compensation slew rate with Equation (28):
VSLOPE@6P
0.25(μA) CURRENT_SOURCE TSW
(
TBLANK )
( 8 - CAP ) 1.85(pF)
6
(28)
Where VSLOPE@6P is the desired slope compensation voltage for 6-phase status, TSW is the PWM period
determined by register MFR_FS (BDh), and TBLANK is SLOPE_BLANK_TIME set in register
MFR_BLANK_TIME (C5h).
If setting VDIFF_GAIN_SEL (2Ah) = 1 to get a half gain for the remote sense amplifier, VSLOPE should
be doubled.
MFR_SLOPE_CNT_6P (D1h)
This register sets the maximum slope compensation ramping time for 6-phase status. Once the timer is
over, the current source turns off, and the slope compensation voltage is held.
Command
MFR_SLOPE_CNT_6P
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
x
Function
x
Bits
Bit Name
Description
15:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
7:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
MFR_SLOPE_SR_5P (D2h)
This register sets the slope compensation slew rate for 5-phase status.
Command
MFR_SLOPE_SR_5P
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
Function
x
x
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
89
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8:6
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
5:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Calculate the slope compensation slew rate with Equation (29):
VSLOPE@5P
0.25(μA) CURRENT_SOURCE TSW
(
TBLANK )
( 8 - CAP ) 1.85(pF)
5
(29)
Where VSLOPE@5P is the desired slope compensation voltage for 5-phase status, TSW is the PWM period
determined by register MFR_FS (BDh), and TBLANK is SLOPE_BLANK_TIME set in register
MFR_BLANK_TIME (C5h).
If setting VDIFF_GAIN_SEL (2Ah) = 1 to get a half gain for the remote sense amplifier, VSLOPE should
be doubled.
MFR_SLOPE_CNT_5P (D3h)
This register sets the maximum slope compensation ramping time for 5-phase status. Once the timer is
over, the current source turns off, and the slope compensation voltage is held.
Command
MFR_SLOPE_CNT_5P
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
Function
x
Bits
Bit Name
Description
15:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
7:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
MFR_SLOPE_SR_4P (D4h)
This register sets the slope compensation slew rate for 4-phase status.
Command
MFR_SLOPE_SR_4P
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
Function
CAP
CURRENT_SOURCE
Bits
Bit Name
Description
15:9
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
8:6
CAP
Capacitor value for slope compensation. 1.85pF/LSB.
5:0
CURRENT_SOURCE
Current source value for slope compensation. 0.25µA/LSB.
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
90
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Calculate the slope compensation slew rate with Equation (30):
VSLOPE@ 4P
0.25(μA) CURRENT_SOURCE TSW
(
TBLANK )
( 8 - CAP ) 1.85(pF)
4
(30)
Where VSLOPE@4P is the desired slope compensation voltage for 4-phase status, TSW is the PWM period
determined by register MFR_FS (BDh), and TBLANK is SLOPE_BLANK_TIME set in register
MFR_BLANK_TIME (C5h).
If setting VDIFF_GAIN_SEL (2Ah) = 1 to get a half gain for the remote sense amplifier, VSLOPE should
be doubled.
MFR_SLOPE_CNT_4P (D5h)
This register sets the maximum slope compensation ramping time for 4-phase status. Once the timer is
over, the current source turns off, and the slope compensation voltage is held.
Command
MFR_SLOPE_CNT_4P
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
Function
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
SLOPE_CNT
Bits
Bit Name
Description
15:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Maximum ramping time of slope compensation for 4-phase status. 5ns/LSB.
7:0
SLOPE _ CNT
SLOPE_CNT
1.3 (
TSW
TBLANK )(ns)
4
5(ns)
Where TSW is the PWM period determined by register MFR_FS (BDh), and
TBLANK is SLOPE_BLANK_TIME set in register MFR_BLANK_TIME (C5h).
MFR_SLOPE_SR_3P (D6h)
This register sets the slope compensation slew rate for 3-phase status.
Command
MFR_SLOPE_SR_3P
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
Function
CAP
CURRENT_SOURCE
Bits
Bit Name
Description
15:10
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
9:6
CAP
Capacitor value for slope compensation. 1.85pF/LSB.
5:0
CURRENT_SOURCE
Current source value for slope compensation. 0.25µA/LSB.
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
91
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Calculate the slope compensation slew rate with Equation (31):
VSLOPE@3P
0.25(μA) CURRENT_SOURCE TSW
(
TBLANK )
( 16 - CAP ) 1.85(pF)
3
(31)
Where VSLOPE@3P is the desired slope compensation voltage for 3-phase status, TSW is the PWM period
determined by register MFR_FS (BDh), and TBLANK is SLOPE_BLANK_TIME set in register
MFR_BLANK_TIME (C5h).
If setting VDIFF_GAIN_SEL (2Ah) = 1 to get a half gain for the remote sense amplifier, VSLOPE should
be doubled.
MFR_SLOPE_CNT_3P (D7h)
This register sets the maximum slope compensation ramping time for 3-phase status. Once the timer is
over, the current source turns off, and the slope compensation voltage is held.
Command
MFR_SLOPE_CNT_3P
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
Function
SLOPE_CNT
Bits
Bit Name
Description
15:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Maximum ramping time of slope compensation for 3-phase status. 5ns/LSB.
7:0
SLOPE _ CNT
SLOPE_CNT
1.3 (
TSW
TBLANK )(ns)
3
5(ns)
Where TSW is the PWM period determined by register MFR_FS (BDh), and
TBLANK is SLOPE_BLANK_TIME set in register MFR_BLANK_TIME (C5h).
MFR_SLOPE_SR_2P (D8h)
This register sets the slope compensation slew rate for 2-phase status.
Command
MFR_SLOPE_SR_2P
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
Function
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
CAP
CURRENT_SOURCE
Bits
Bit Name
Description
15:10
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
9:6
CAP
Capacitor value for slope compensation. 1.85pF/LSB.
5:0
CURRENT_SOURCE
Current source value for slope compensation. 0.25µA/LSB.
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
92
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Calculate the slope compensation slew rate with Equation (32):
VSLOPE@ 2P
0.25(μA) CURRENT_SOURCE TSW
(
TBLANK )
( 16 - CAP ) 1.85(pF)
2
(32)
Where VSLOPE@2P is the desired slope compensation voltage for 2-phase status, TSW is the PWM period
determined by register MFR_FS (BDh), TBLANK is SLOPE_BLANK_TIME set in register
MFR_BLANK_TIME (C5h).
If setting VDIFF_GAIN_SEL (2Ah) = 1 to get a half gain for the remote sense amplifier, VSLOPE should
be doubled.
MFR_SLOPE_CNT_2P (D9h)
This register sets the maximum slope compensation ramping time for 2-phase status. Once the timer is
over, the current source turns off, and the slope compensation voltage is held.
Command
MFR_SLOPE_CNT_2P
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
Function
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
SLOPE_CNT
Bits
Bit Name
Description
15:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Maximum ramping time of slope compensation for 2-phase status. 5ns/LSB.
7:0
SLOPE _ CNT
SLOPE_CNT
1.3 (
TSW
TBLANK )(ns)
2
5(ns)
Where TSW is the PWM period determined by register MFR_FS (BDh), and
TBLANK is SLOPE_BLANK_TIME set in register MFR_BLANK_TIME (C5h).
MFR_SLOPE_SR_1P (DAh)
This register sets the slope compensation slew rate for 1-phase CCM status.
Command
MFR_SLOPE_SR_1P
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
x
x
x
Function
CURRENT_SOURCE
Bits
Bit Name
Description
15:7
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
6
CAP
Capacitor value for slope compensation. 1.85pF/LSB.
5:0
CURRENT_SOURCE
Current source value for slope compensation. 0.25µA/LSB.
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
93
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Calculate the slope compensation slew rate with Equation (33):
V S L O P E @ 1P
0 .2 5 (μ A ) C U R R E N T _ S O U R C E
( T S W TB L A N K )
( 1 6 - C A P ) 1 .8 5 (p F )
(33)
Where VSLOPE@1P is desired slope compensation voltage for 1-phase CCM status, TSW is the PWM
period determined by register MFR_FS (BDh), and TBLANK is SLOPE_BLANK_TIME set in register
MFR_BLANK_TIME (C5h).
If setting VDIFF_GAIN_SEL (2Ah) = 1 to get a half gain for the remote sense amplifier, VSLOPE should
be doubled.
MFR_SLOPE_CNT_1P (DBh)
This register sets the maximum slope compensation ramping time for 1-phase CCM status. Once the
timer is over, the current source turns off, and the slope compensation voltage is held.
Command
Format
Bit
Access
Function
15
r/w
x
Bits
Bit Name
Description
15:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
14
r/w
x
13
r/w
x
12
r/w
x
11
r/w
x
10
r/w
x
MFR_SLOPE_CNT_1P
Unsigned binary
9
8
7
6
r/w
r/w
r/w
r/w
5
4
r/w
r/w
SLOPE_CNT
3
r/w
2
r/w
1
r/w
0
r/w
Maximum ramping time of slope compensation for 1-phase CCM status.
5ns/LSB.
7:0
SLOPE_CNT
SLOPE _ CNT
1.3 (TSW TBLANK )(ns)
5(ns)
Where TSW is the PWM period determined by register MFR_FS (BDh), and
TBLANK is SLOPE_BLANK_TIME set in register MFR_BLANK_TIME (C5h).
MFR_SLOPE_TRIM1 (DDh)
This register is used to calibrate the VOUT offset caused by the slope compensation and VOUT ripple.
Command
Format
Bit
Access
Function
15
r/w
x
Bits
Bit Name
Description
15
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
14:10
VTRIM_2P
9:5
VTRIM_1P
4:0
VTRIM_DCM
14
r/w
13
12
11
r/w
r/w
r/w
VTRIM_2P
10
r/w
MFR_SLOPE_TRIM1
Unsigned binary
9
8
7
6
r/w
r/w
r/w
r/w
VTRIM_1P
5
r/w
4
r/w
3
2
1
r/w
r/w
r/w
VTRIM_DCM
0
r/w
Output voltage calibration value for 2-phase status.
2.35mV/LSB, when VDIFF_GAIN_SEL (2Ah) = 0
4.7mV/LSB, when VDIFF_GAIN_SEL (2Ah) = 1
Output voltage calibration value for 1-phase CCM status.
2.35mV/LSB, when VDIFF_GAIN_SEL (2Ah) = 0
4.7mV/LSB, when VDIFF_GAIN_SEL (2Ah) = 1
Output voltage calibration value for 1-phase DCM status.
2.35mV/LSB, when VDIFF_GAIN_SEL (2Ah) = 0
4.7mV/LSB, when VDIFF_GAIN_SEL (2Ah) = 1
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
94
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_SLOPE_TRIM2 (DEh)
This register is used to calibrate the VOUT offset caused by the slope compensation and VOUT ripple.
Command
MFR_SLOPE_TRIM2
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
x
x
VTRIM_4P
VTRIM_3P
Bits
Bit Name
Description
15
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
14:10
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Output voltage calibration value for 4-phase status.
9:5
VTRIM_4P
4:0
VTRIM_3P
2.35mV/LSB, when VDIFF_GAIN_SEL (2Ah) = 0
4.7mV/LSB, when VDIFF_GAIN_SEL (2Ah) = 1
Output voltage calibration value for 3-phase status.
2.35mV/LSB, when VDIFF_GAIN_SEL (2Ah) = 0
4.7mV/LSB, when VDIFF_GAIN_SEL (2Ah) = 1
MFR_SLOPE_TRIM3 (DFh)
This register is used to calibrate VOUT offset caused by the slope compensation and VOUT ripple.
Command
MFR_SLOPE_TRIM3
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
x
x
x
x
Bits
Bit Name
Description
15
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
14:10
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
9:5
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
4:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
MFR_SLOPE_TRIM4 (E0h)
This register is used to calibrate the VOUT offset caused by the slope compensation and VOUT ripple.
Command
MFR_SLOPE_TRIM4
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
x
x
x
Function
x
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
x
95
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
Bit Name
Description
15:10
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
9:5
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
4:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
MFR_VR_CONFIG1 (E1h)
This register sets the main functions of the controller.
Command
Format
Bit
Access
15
r/w
14
r/w
13
r/w
12
r/w
11
r/w
10
r/w
MFR_VR_CONFIG1
Unsigned binary
9
8
7
6
r/w
r/w
r/w
r/w
Function
Bits
5
r/w
4
r/w
3
r/w
0
Bit Name
2
r/w
1
r/w
0
r/w
PHASE_CNT
Description
Enable bit of the DC loop for DCM.
15
DC_LOOP_EN_PS2
14
DC_LOOP_EN
13
PSI_SEL
0: disable
1: enable
Enable bit of the DC loop for CCM.
0: disable
1: enable
PSI controlling mode selector.
0: controlled by PSI
1: controlled by PMBus command (bit[12:11] of this register)
PSI command via PMBus.
12:11
PSI_PMBUS
00: full-phase CCM
01: 1-phase CCM
1x: 1-phase DCM
10
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
9
PS2_TON_REDUCE_
EN
8
PMBUS_PSI_BYPASS_
EN
7
CB_EN
6
OSR_EN
Enable bit for reducing PWM on-time to 3/4 of its normal value at PS2.
0: disable
1: enable
Enable bit for bypassing the PSI command. When APS is enabled, set this bit to
ignore the PSI command from PSI or the PMBus.
0: disable
1: enable
Enable bit for current balance loop.
0: disable
1: enable
Enable bit for overshoot reduction.
0: disable
1: enable
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
96
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Enable bit for auto-phase shedding.
5
APS_EN
4
VID_CTRL_MODE
0: output voltage is controlled via PWM-VID
1: output voltage is controlled via the PMBus
3
RESERVED
Fixed to 0.
0: disable
1: enable
Output voltage controlling mode.
Phase number setting for full-phase mode.
2:0
PHASE_CNT
000
001
010
011
PHASE_CNT
Mode
1-phase DCM
1-phase CCM
2 phases
3 phases
PHASE_CNT
100
101
110
111
Mode
4 phases
Forbidden
Forbidden
Forbidden
Figure 20: Conceptual View of how Output Voltage Related Commands are Applied
MFR_VR_CONFIG2 (E2h)
This register sets the main functions of the controller.
Command
Format
Bit
Access
Function
7
r/w
x
6
r/w
x
5
r/w
x
MFR_VR_CONFIG2
Unsigned binary
4
3
r/w
r/w
x
2
r/w
1
r/w
0
r/w
Bits
Bit Name
Description
7:6
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
5
RESERVED
Fixed to 0.
4
RESERVED
Fixed to 0.
LOW_PWR_EN
Enable bit for low-power mode. Low-power mode is when EN is low and the
controller disables some internal circuits to save power. PMBus communication
is also disabled in low-power mode.
3
0: disable
1: enable
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
97
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Shutdown mode via EN.
2
0: immediate shutdown (all PWMs are set to tri-state)
1: soft shutdown (output voltage falls to zero with a boot-up slew rate)
EN_SD_MODE
If LOW_PWR_EN = 1, only immediate shutdown is available.
Delay time clock selector for TON_DELAY and TOFF_DELAY.
1
DLY_CLK_SEL
0: 20µs/LSB
1: 50µs/LSB
Output voltage (boot-up, shutdown, and DVID) slewing mode selector for PWMVID mode.
0
VOUT_SLEWRATE_
MODE
0: linear mode
1: R-C filter mode
In PMBus override mode, the slew rate is always linear.
MFR_APS_LEVEL1 (E3h)
This register sets the output current threshold for phase dropping when APS is enabled.
Command
MFR_APS_LEVEL1
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
DROP_LEVEL_1P
Bits
Bit Name
15:8
DROP_LEVEL_1P
DROP_LEVEL_DCM
Description
Output current threshold for dropping to 1-phase CCM status.
1A/LSB (TOTAL_CURRENT_RESOLUTION = 0)
2A/LSB (TOTAL_CURRENT_RESOLUTION = 1)
Output current threshold for dropping to the 1-phase DCM status.
7:0
DROP_LEVEL_DCM
1A/LSB (TOTAL_CURRENT_RESOLUTION = 0)
2A/LSB (TOTAL_CURRENT_RESOLUTION = 1)
MFR_APS_LEVEL2 (E4h)
This register sets the output current threshold for phase dropping when APS is enabled.
Command
MFR_APS_LEVEL2
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
DROP_LEVEL_3P
Bits
Bit Name
15:8
DROP_LEVEL_3P
7:0
DROP_LEVEL_2P
DROP_LEVEL_2P
Description
Output current threshold for dropping to 3-phase status.
1A/LSB (TOTAL_CURRENT_RESOLUTION = 0)
2A/LSB (TOTAL_CURRENT_RESOLUTION = 1)
Output current threshold for dropping to 2-phase status.
1A/LSB (TOTAL_CURRENT_RESOLUTION = 0)
2A/LSB (TOTAL_CURRENT_RESOLUTION = 1)
MP2884A Rev. 1.01
www.MonolithicPower.com
12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
98
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_APS_LEVEL3 (E5h)
This register sets the output current threshold for phase dropping when APS is enabled.
Command
MFR_APS_LEVEL3
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Function
Bits
Bit Name
Description
15:8
RESERVED
Fixed to 11111111.
7:0
RESERVED
Fixed to 11111111.
MFR_APS_LEVEL4 (E6h)
This register sets the output current threshold for phase dropping when APS is enabled.
Command
MFR_APS_LEVEL4
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bits
Bit Name
Description
15:8
RESERVED
Fixed to 11111111.
7:0
RESERVED
Fixed to 11111111.
MFR_APS_LEVEL5 (E7h)
This register sets the output current threshold for phase dropping when APS is enabled.
Command
MFR_APS_LEVEL6
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Function
Bits
Bit Name
Description
15:8
RESERVED
Fixed to 11111111.
7:0
RESERVED
Fixed to 11111111.
MFR_APS_HYS (E8h)
This register sets the output current hysteresis threshold for APS.
Command
Format
Bit
Access
Function
7
r/w
6
r/w
5
r/w
MFR_APS_HYS
Unsigned binary
4
3
r/w
r/w
HYS_APS
2
r/w
1
r/w
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r/w
99
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
Bit Name
7:0
HYS_APS
Description
Hysteresis of output current threshold for APS function.
1A/LSB (TOTAL_CURRENT_RESOLUTION = 0)
2A/LSB (TOTAL_CURRENT_RESOLUTION = 1)
MFR_TSNS_OT_SET (E9h)
This register sets the OTP function via TSNS.
Command
MFR_TSNS_OT_SET
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
TSNS_OTP_HYS
Bits
Bit Name
15
TSNS_OTP_EN
TSNS_OTP_THRE
Description
Enable bit for OTP via TSNS.
0: disable
1: enable
Mode selector for OTP via TSNS.
14
TSNS_OTP_MODE
0: hiccup mode
1: latch mode
Hysteresis for exiting OTP via TSNS in hiccup mode.
13:8
TSNS_OTP_HYS
T S N S _ O T P _ H YS
2 56 V T S N S _ H YS
1.6
Where VTSNS_HYS is the voltage hysteresis of TSNS for TSNS OTP.
Threshold for triggering OTP via TSNS.
7:0
TSNS_OTP_THRE
TSNS _ OTP _ THRE
2 5 6 VT S N S _ T H R E
1 .6
Where VTSNS_THRE is the voltage threshold of TSNS for OTP.
MFR_VTEMP_OT_SET (EAh)
This register sets the OTP function via VTEMP.
Command
MFR_VTEMP_OT_SET
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
VTEMP_OTP_THRE
Bits
Bit Name
Description
15:8
VTEMP_OTP_THRE
Threshold for OTP via VTEMP. 1°C/LSB.
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
VTEMP_OTP_HYS
Mode selector for OTP via VTEMP.
7
VTEMP_OTP_MODE
0: hiccup mode
1: latch mode
6:0
VTEMP_OTP_HYS
Hysteresis for exiting OTP via VTEMP in hiccup mode. 1℃/LSB.
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_OCP_TOTAL (ECh)
This register sets the total output over-current protection (OCP). Total OCP is not active during soft
start.
Command
MFR_OCP_TOTAL
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
x
OCP_ DEGLITCH_TIME
OCP_THRE
Bits
Bit Name
Description
15
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Total OCP action mode selector.
00: no action
01: latch off
10: hiccup
11: retry six times
14:13
OCP_MODE
12:7
OCP_ DEGLITCH_TIME
Deglitch time for total OCP. When the protection condition lasts for this deglitch
time, the VR shuts down. 100µs/LSB.
Threshold of total OCP.
6:0
OCP_THRE
1A/LSB (TOTAL_CURRENT_RESOLUTION = 0)
2A/LSB (TOTAL_CURRENT_RESOLUTION = 1)
MFR_OCP_PHASE (EDh)
This register sets the phase valley current limit. When a certain phase's inductor current is greater than
this threshold, its PWM cannot turn high.
Command
Format
Bit
Access
Function
7
r/w
x
6
r/w
MFR_OCP_PHASE
Unsigned binary
4
3
2
r/w
r/w
r/w
PHASE_CUR_LIMIT
5
r/w
1
r/w
0
r/w
Bits
Bit Name
Description
7
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
Per-phase valley current limit.
6:0
PHASE_CUR_LIMIT
1A/LSB (PHASE_CURRENT_RESOLUTION = 0)
2A/LSB (PHASE_CURRENT_RESOLUTION = 1)
MFR_OVP_UVP_SET (EEh)
This register sets VOUT OVP and UVP. The OVP2 and UVP2 level is selected by bit[2:0] of register
MFR_OVUV_SEL (2Ch). OVP2 and UVP are not active during the soft-start process.
Command
MFR_OVP_UVP_SET
Format
Unsigned binary
Bit
15
14
13
12
Access
r/w
r/w
r/w
r/w
Function
11
10
9
8
7
6
5
r/w
r/w
r/w
r/w
r/w
r/w
r/w
OVP2_DEGLITCH_TIME
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
UVP_DEGLITCH_TIME
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
Bit Name
Description
OVP mode selector.
000: no action
010: latch off
100: hiccup
110: retry six times
111: retry three times
15:13
OVP2_MODE
12:8
OVP2_DEGLITCH_TIME
Deglitch time for OVP. When the protection condition lasts for this deglitch time,
the VR shuts down. 100ns/LSB.
UVP mode selector.
00: no action
01: latch off
10: hiccup
11: retry six times
7:6
UVP_MODE
5:0
UVP_DEGLITCH_TIME
Deglitch time for UVP. When the protection condition lasts for this deglitch time,
the VR shuts down. 20µs/LSB.
MFR_FAULTS1 (F8h)
This register returns the faults of the present protection. These bits are in latch mode. The
CLEAR_FAULTS command can reset these bits.
Command
MFR_FAULTS1
Format
Unsigned binary
Bit
15
14
13
12
11
r
r
Access
r
r
r
Function
x
x
x
10
9
8
r
r
r
CS_FAULT_TRG
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
x
Bits
Bit Name
Description
15:13
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
12
TEMP_FAULT_TRG
Flag of TEMP_FAULT protection.
0: protection not triggered by TEMP_FAULT of the Intelli-Phase
1: protection triggered by TEMP_FAULT of the Intelli-Phase
Flag for CS_FAULT triggering VR protection.
0000: protection not triggered by CS_FAULT of the Intelli-Phase
0001: protection triggered by CS1_FAULT of the Intelli-Phase
0010: protection triggered by CS2_FAULT of the Intelli-Phase
0011: protection triggered by CS3_FAULT of the Intelli-Phase
0100: protection triggered by CS4_FAULT of the Intelli-Phase
11:8
CS_FAULT_TRG
7
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
6
VIN_OV_FLAG
Flag of input OVP.
5
VIN_UVLO_FLAG
Flag of input UVP.
4
VTEMP_OTP_FLAG
Flag of OTP from VTEMP.
3
TSNS_OTP_FLAG
Flag of OTP from TSNS.
2
OVP_FLAG
Flag of output OVP.
1
UVP_FLAG
Flag of output UVP.
0
OCP_FLAG
Flag of output OCP.
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102
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
MFR_FAULTS2 (F9h)
This register returns the faults of the present protection. These bits are in latch mode. The
CLEAR_FAULTS command can reset these bits.
Command
MFR_FAULTS2
Format
Bit
Access
Unsigned binary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Function
Bits
PWM1_FAULTS
PWM2_FAULTS
Bit Name
PWM3_FAULTS
PWM4_FAULTS
Description
Intelli-Phase fault type indication of phase 1.
0000: no fault
0001: VIN-SW short
0010: current-limit protection
0100: over-temperature protection
1000: SW-PGND short protection
15:12
PWM1_FAULTS
11:8
PWM2_FAULTS
Intelli-Phase fault type indication of phase 2. Same types as bit[15:12].
7:4
PWM3_FAULTS
Intelli-Phase fault type indication of phase 3. Same types as bit[15:12].
3:0
PWM4_FAULTS
Intelli-Phase fault type indication of phase 4. Same types as bit[15:12].
MFR_FAULTS3 (FAh)
This register returns the faults of the present protection. These bits are in latch mode. The
CLEAR_FAULTS command can reset these bits.
MFR_FAULTS3
Command
Format
Bit
Access
Unsigned binary
15
14
r
r
Function
13
12
11
10
r
r
r
r
x
9
8
7
6
r
r
r
r
x
5
4
3
2
r
r
r
r
x
1
0
r
r
x
Bits
Bit Name
Description
15:12
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
11:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
7:4
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
3:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
MFR_FAULTS4 (FBh)
This register returns the faults of the present protection. These bits are in latch mode. The
CLEAR_FAULTS command can reset these bits.
Command
MFR_FAULTS4
Format
Unsigned binary
Bit
Access
Function
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
x
x
x
x
x
x
x
x
x
x
MP2884A Rev. 1.01
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0
103
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
Bit Name
Description
15:12
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
11:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
7:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
CLEAR_EEPROM_FAULTS (FFh)
This command is used to clear the EEPROM fault. This command is write only. There is no data byte
for this command.
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
PAGE 29 REGISTER MAP
MFR_LAST_FAULTS1 (FBh)
This register returns the faults of the last protection. To clear the fault bits, 0x0000 can be written to this
register. Then wait for 5ms.
Command
MFR_LAST_FAULTS1
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
x
x
x
Function
CS_FAULT_TRG
x
Bits
Bit Name
Description
15:13
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
12
TEMP_FAULT_TRG
Flag of TEMP_FAULT protection.
0: protection not triggered by TEMP_FAULT of the Intelli-Phase
1: protection triggered by TEMP_FAULT of the Intelli-Phase
Flag for CS_FAULT triggering VR protection.
0000: protection is not triggered by CS_FAULT of the Intelli-Phase
0001: protection is triggered by CS1_FAULT of the Intelli-Phase
0010: protection is triggered by CS2_FAULT of the Intelli-Phase
0011: protection is triggered by CS3_FAULT of the Intelli-Phase
0100: protection is triggered by CS4_FAULT of the Intelli-Phase
11:8
CS_FAULT_TRG
7
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
6
VIN_OV_FLAG
Flag of input OVP.
5
VIN_UVLO_FLAG
Flag of input UVP.
4
VTEMP_OTP_FLAG
Flag of OTP from VTEMP.
3
TSNS_OTP_FLAG
Flag of OTP from TSNS.
2
OVP_FLAG
Flag of output OVP.
1
UVP_FLAG
Flag of output UVP.
0
OCP_FLAG
Flag of output OCP.
MFR_LAST_FAULTS2 (FCh)
This register returns the faults of the last protection. To clear the fault bits, 0x0000 can be written to this
register. Then wait for 5ms.
Command
MFR_LAST_FAULTS2
Format
Unsigned binary
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
PWM1_FAULTS
PWM2_FAULTS
PWM3_FAULTS
PWM4_FAULTS
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MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
Bits
Bit Name
Description
Intelli-Phase fault type indication of phase 1.
0000: no fault
0001: VIN-SW short
0010: current-limit protection
0100: over-temperature protection
1000: SW-PGND short protection
15:12
PWM1_FAULTS
11:8
PWM2_FAULTS
Intelli-Phase fault type indication of phase 2. Same types as bit[15:12].
7:4
PWM3_FAULTS
Intelli-Phase fault type indication of phase 3. Same types as bit[15:12].
3:0
PWM4_FAULTS
Intelli-Phase fault type indication of phase 4. Same types as bit[15:12].
MFR_LAST_FAULTS3 (FDh)
This register returns the faults of the last protection. To clear the fault bits, 0x0000 can be written to this
register. Then wait for 5ms.
Command
Format
Bit
Access
Function
15
r/w
14
r/w
13
r/w
12
r/w
11
r/w
MFR_LAST_FAULTS3
Unsigned binary
9
8
7
6
r/w
r/w
r/w
r/w
10
r/w
x
x
5
r/w
4
r/w
3
r/w
2
r/w
x
1
r/w
0
r/w
x
Bits
Bit Name
Description
15:12
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
11:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
7:4
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
3:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
MFR_LAST_FAULTS4 (FEh)
This register returns the faults of the last protection. To clear the fault bits, 0x0000 can be written to this
register. Then wait for 5ms.
Command
Format
Bit
Access
Function
15
r/w
14
r/w
13
r/w
x
12
r/w
11
r/w
MFR_LAST_FAULTS4
Unsigned binary
10
9
8
7
6
r/w
r/w
r/w
r/w
r/w
x
x
x
5
r/w
x
4
r/w
x
3
r/w
x
2
r/w
x
Bits
Bit Name
Description
15:12
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
11:8
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
7:0
RESERVED
Unused. X indicates that writes are ignored and reads are always 0.
MP2884A Rev. 1.01
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12/25/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
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1
r/w
x
0
r/w
x
106
MP2884A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID
PACKAGE INFORMATION
QFN-40 (5mmx5mm)
PIN 1 ID
0.30x45° TYP.
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
BOTTOM VIEW
TOP VIEW
SIDE VIEW
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD
FLASH.
3) LEAD COPLANARITY SHALL BE 0.08 MILLIMETERS MAX.
4) DRAWING CONFIRMS TO JEDEC MO-220, VARIATION
VHHE-1
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
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