MPQ1530
Triple Output Step-Up
Plus Linear Regulators for TFT Bias
AEC-Q100 Qualified
DESCRIPTION
The MPQ1530 combines a triple output step-up
converter with linear regulators to provide a
complete DC/DC solution. It is designed to
power TFT LCD panels from a regulated 3.3V
or 5V supply.
This
device
integrates
a
1.4MHz
fixed-frequency step-up converter with positive
and negative linear regulators. The step-up
converter switch node drives two charge pumps,
which supply powers to their respective linear
regulators. The positive and negative linear
regulator inputs can withstand up to 38V and
down to -20V, respectively.
A single on/off control enables all 3 outputs.
The outputs are internally sequenced at startup
for ease of use. An internal soft-start prevents
input overload at startup. Cycle-by-cycle current
limiting reduces component stress.
The MPQ1530 is available in a tiny 3x3mm, 16pin QFN package.
FEATURES
Guaranteed Industrial/Automotive Temp
Range Limits
2.7 to 5.5V Operating Input Range
2.8A Switch Current Limit
3 Outputs In a Single Package
Step-Up Converter up to 22V
Positive 20mA Linear Regulator
Negative 20mA Linear Regulator
250mΩ Internal Power MOSFET Switch
Up to 95% Efficiency
1.4MHz Fixed Frequency
Internal Power-On Sequencing
Adjustable Soft-Start/Fault Timer
Cycle-by-Cycle Over Current Protection
Under Voltage Lockout
Ready Flag
16-Pin QFN (3x3mm) Package
Available in AEC-Q100 Qualified Grade 1
APPLICATIONS
TFT LCD Displays
Portable DVD Players
Tablet PCs
Car Navigation Displays
All MPS parts are lead-free, halogen free, and adhere to the RoHS directive. For
MPS green status, please visit MPS website under Quality Assurance. “MPS”
and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
MPQ1530 Rev. 1.02
www.MonolithicPower.com
7/14/2017
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
1
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED
ORDERING INFORMATION
Part Number
MPQ1530DQ*
Package
Top Marking
QFN16 (3x3mm)
B8
MPQ1530DQ-AEC1**
* For Tape & Reel, add suffix -Z (e.g. MPQ1530DQ-Z).
For RoHS Compliant Packaging, add suffix -LF (e.g. MPQ1530DQ-LF-Z)
** For Tape & Reel, add suffix -Z (e.g. MPQ1530DQ-AEC1-Z).
For RoHS Compliant Packaging, add suffix -LF (e.g. MPQ1530DQ-AEC1-LF-Z)
PACKAGE REFERENCE
QFN16
ABSOLUTE MAXIMUM RATINGS (1)
IN Supply Voltage ......................... –0.3V to +6V
SW Voltage................................. –0.3V to +25V
IN2, GL Voltage .......................... +0.3V to –25V
IN3, GH Voltage.......................... –0.3V to +40V
IN2 to IN3 Voltage ...................... –0.3V to +60V
All Other Pins ................................ –0.3V to +6V
(2)
Continuous Power Dissipation (TA = +25°C)
QFN16 (3 x 3mm)…………………………....2.1W
Junction Temperature……………………..125C
Lead Temperature ................................... 260C
Storage Temperature ............. –65C to +150C
ESD Susceptibility (3)
HBM (Human Body Mode)
•IN3: CLASS 1A;
•GH: CLASS 1B;
•GL: CLASS 1C;
•Other Pins: CLASS 2;
CDM (Charged Device Mode)
•All Pins: CLASS IV;
Recommended Operating Conditions (4)
Input Voltage ..................................2.7V to 5.5V
Main Output Voltage .......................... VIN to 22V
IN2, GL Voltage ................................0V to –20V
IN3, GH Voltage ................................ 0V to 38V
Operating Junction Temp. (TJ). -40°C to +125°C
Thermal Resistance (5)
θJA
θJC
QFN16 (3 x 3mm) ................... 60 ...... 12 ... C/W
Notes:
1) Absolute maximum are rated under room temperature unless
otherwise noted. Exceeding these ratings may damage the
device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) Devices are ESD sensitive. Handle with precaution.
4) The device is not guaranteed to function outside of its
operating conditions.
5) Measured on approximately 1” square of 1 oz copper.
MPQ1530 Rev. 1.02
www.MonolithicPower.com
7/14/2017
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
2
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED
ELECTRICAL CHARACTERISTICS (6)
VIN = 5V, TJ = -40C to +125C, Typical value are at TJ = +25C, unless otherwise noted.
Parameter
Symbol Condition
Input Voltage Range
IN Undervoltage Lockout Threshold
IN Undervoltage Lockout Hysteresis
VIN
VUVLO
Typ
Max
Units
5.5
2.65
V
V
mV
0.5
1
μA
1.3
1.6
mA
V
V
mV
2.7
2.25
100
IN Shutdown Current
IN Quiescent Current
EN Input High Voltage
EN Input Low Voltage
EN Hysteresis
IN Rising
Min
VEN HIGH
VEN 0.3V
VEN > 2V, VFB1 = 1.4V
EN Rising
1.6
0.3
250
EN Input Bias Current
Oscillator
1
Switching Frequency
Maximum Duty Cycle
Soft Start Period
fSW
DM
1
85
CCT = 10nF
Regulator #2 Turn-On/Turn-Off Delay
CCT = 10nF
μA
1.4
90
6
3
MHz
%
ms
μs
6
ms
400
1000
±100
1.25
0
V/V
μA/V
μA
V
mV
Error Amplifier
(6)
Error Amplifier Voltage Gain
Error Amplifier Transconductance
COMP Maximum Output Current
FB1, FB3 Regulation Voltage
FB2 Regulation Voltage
AvEA
GmEA
1.22
–25
FB1, FB3 Input Bias Current
FB2 Input Bias Current
Reference (REF)
VFB1 = VFB3 = 1.25V
VFB2 = 0V
REF Regulation Voltage
REF Load Regulation
Output Switch (SW)
IREF = 50μA
0μA < IREF < 200μA
SW On Resistance
(6)
SW Current Limit
ILIM
SW Leakage Current
(7)
GL Dropout Voltage
GH Dropout Voltage
GL Leakage Current
GH Leakage Current
Thermal Shutdown
(6)
(7)
VIN = 5V
VIN = 3V
o
TJ=+25 C
o
o
TJ=-40 C to +125 C
VSW = 22V
VGL = –10V, IGL = –20mA
VGH = 20V, IGH = 20mA
VIN2 = –15V, VGL = GND
VIN3 = 25V, VGH = GND
1.28
+25
±100
±100
1.22
2.5
2.2
1.25
1
250
400
3.6
3.6
0.5
0.1
0.45
nA
nA
1.28
1.2
V
%
mΩ
mΩ
A
1
0.3
μA
V
1
1
1
V
μA
μA
160
C
Notes:
6) Not production tested.
7) Dropout Voltage is the input to output differential at which the circuit ceases to regulate against further reduction in input voltage.
MPQ1530 Rev. 1.02
www.MonolithicPower.com
7/14/2017
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
3
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED
TYPICAL PERFORMANCE CHARACTERISTICS
Circuit of Figure 3, VIN = 5V, VMAIN = 13V, IMAIN = 200mA, VGL = -8.5V, IGL = 10mA, VGH = 27V,
IGH = 10mA, TA = +25C, unless otherwise noted.
MPQ1530 Rev. 1.02
www.MonolithicPower.com
7/14/2017
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
4
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Circuit of Figure 3, VIN = 5V, VMAIN = 13V, IMAIN = 200mA, VGL = -8.5V, IGL = 10mA, VGH = 27V,
IGH = 10mA, TA = +25C, unless otherwise noted.
MPQ1530 Rev. 1.02
www.MonolithicPower.com
7/14/2017
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
5
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED
PIN FUNCTIONS
QFN
Pin #
Name Description
1
SW
2
CT
3
RDY
4
FB1
5
COMP
6
IN
7
GND
8
REF
9
FB2
10
FB3
11
EN
12
GL
13
IN2
14
GH
15
IN3
16
PGND
Pad
Expos
ed pad
Step-Up Converter Power Switch Node. Connect an inductor between the input source and SW,
and connect a rectifier from SW to the main output to complete the step-up converter. SW is the
drain of the internal 250mΩ N-Channel MOSFET switch.
Timing Capacitor for Power Supply Soft-Start and Power-On Sequencing. A capacitor from CT to
GND controls the soft-start and sequencing turn-on delay periods. See Power-On Sequencing and
Start Up Timing Diagram.
Regulators Not Ready. During startup RDY will be left high. Once the turn-on sequence is
complete, this pin will be pulled low if all FB voltages exceed 80% of their specified thresholds. After
all regulators are turned-on, a fault in any regulator that causes the respective FB voltage to fall
below 80% of its threshold will cause RDY to go high after approximately 15μs. If the fault persists
for more than approximately 6ms (for CCT=10nF), the entire chip will shut down. See Fault Sensing
and Timer.
Step-Up Converter Feedback Input. FB1 is the inverting input of the internal error amplifier. Connect
a resistive voltage divider from the output of the step-up converter to FB1 to set the step-up
converter output voltage.
Step-Up Converter Compensation Node. COMP is the output of the error amplifier. Connect a series
RC network to compensate the regulation control loop of the step-up converter.
Internal Power Input. IN supplies the power to the MPQ1530. Bypass IN to PGND with a 10μF or
greater capacitor.
Signal Ground.
Reference Output. REF is the 1.25V reference voltage output. Bypass REF to GND with a 0.1μF or
greater capacitor. Connect REF to the low-side resistor of the negative linear regulator feedback
string.
Negative Linear Regulator Feedback Input. Connect the FB2 feedback resistor string between GL
and REF to set the negative linear regulator output voltage. FB2 regulation threshold is GND.
Positive Linear Regulator Feedback Input. Connect the FB3 feedback resistor string between GH
and GND to set the positive linear regulator output voltage. FB3 regulation threshold is 1.25V.
On/Off Control Input. Drive EN high to turn on the MPQ1530, drive EN low to turn it off. For
automatic startup, connect EN to IN. Once the MPQ1530 is turned on, it sequences the outputs on
(See Power-On Sequencing). When turned off, all outputs are immediately disabled.
Negative Linear Regulator Output. GL is the output of the negative linear regulator. GL can supply
up to 20mA to the load. Bypass GL to GND with a 1μF or greater, low-ESR, ceramic capacitor.
Negative Linear Regulator Input. IN2 is the input of the negative linear regulator. Drive IN2 with an
inverting charge pump powered from SW. IN2 can go as low as -20V. For QFN package, connect
the exposed pad to IN2 pin.
Positive Linear Regulator Output. GH is the output of the positive linear regulator. GH can supply as
much as 20mA to the load. Bypass GH to GND with a 1μF or greater, low-ESR, ceramic capacitor.
Positive Linear Regulator Input. IN3 is the input to the positive linear regulator. Drive IN3 with a
doubling, tripling, or quadrupling charge pump from SW. IN3 voltage can go as high as 38V.
Power Ground. PGND is the source of the internal 250mΩ N-Channel MOSFET switch. Connect
PGND to GND as close to the MPQ1530 as possible.
No internal electrical connections. Solder it to the lowest potential (IN2 pin) plane to reduce
thermal resistance.
MPQ1530 Rev. 1.02
www.MonolithicPower.com
7/14/2017
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
6
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED
BLOCK DIAGRAM
Figure 1—Functional Block Diagram
MPQ1530 Rev. 1.02
www.MonolithicPower.com
7/14/2017
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
7
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED
OPERATION
The MPQ1530 is a step-up converter with two
integrated linear regulators to power TFT LCD
panels. Typically the linear regulators are
powered from charge-pumps driven from the
switch node (SW). The user can set the positive
charge-pump to be a doubler, tripler, or
quadrupler to achieve the required linear
regulator input voltage for the selected output
voltage. Typically the negative charge-pump is
configured as a 1x inverter.
Step-Up Converter
The step-up, fixed-frequency, 1.4MHz converter
employs a current-mode control architecture
that maximizes loop bandwidth to provide fasttransient responses needed for TFT LCD
drivers. High switching frequency allows for
smaller inductors and capacitors minimizing
board space and thickness.
Linear Regulators
The positive linear regulator (GH) uses a
P-Channel pass element to drop the input
voltage down to the regulated output voltage.
The feedback of the positive linear regulator is
a conventional error amplifier with the
regulation threshold at 1.25V.
The negative linear regulator (GL) uses a
N-Channel pass element to raise the negative
input voltage up to the regulated output voltage.
The feedback threshold for the negative linear
regulator is ground. The resistor string goes
from REF (1.25V) to FB2 and from FB2 to GL to
set the negative output voltage.
The difference between the voltage at IN3 and
the voltage at IN2 is limited to 60V abs. max.
Fault Sensing and Timer
Each of the 3 outputs has an internal
comparator that monitors its respective output
voltage by measuring the voltage at its
respective FB input. When any FB input
indicates that the output voltage is below
approximately 80% of the correct regulation
voltage, the fault timer enables and the RDY
pin goes high.
The fault timer uses the same CT capacitor as
the soft-start sequencer. If any fault persists to
the end of the fault timer (One CT cycle is 6ms
for a 10nF capacitor), all outputs are disabled.
Once the outputs are shut down due to the fault
timer, the MPQ1530 must be re-enabled by
either cycling EN or by cycling the input power.
If the fault persists for less than the fault timer
period, RDY will be pulled low and the part will
function as though no fault has occurred.
Power-On Sequencing and Soft-Start
The MPQ1530 automatically sequences its
outputs at startup. When EN goes from low to
high, or if EN is held high and the input voltage
IN rises above the under-voltage lockout
threshold, the outputs turn on in the following
sequence:
1. Step-up Converter
2. Negative Linear Regulator (GL)
3. Positive Linear Regulator (GH)
Each output turns on with a soft-start voltage
ramp. The soft-start ramp period is set by the
timing capacitor connected between CT and
GND. A 10nF capacitor at CT sets the soft-start
ramp period to 6ms. The timing diagram is
shown in Figure 2.
After the MPQ1530 is enabled, the power-on
reset spans three periods of the CT ramp. First
the step-up converter is powered up with
reference to the CT ramp and allowed one
period of the CT ramp to settle. Next the
negative linear regulator (GL) is soft-started by
ramping REF, which coincides with the CT
ramp, and also allowed one CT ramp period to
settle.
MPQ1530 Rev. 1.02
www.MonolithicPower.com
7/14/2017
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
8
MPQ1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS, AEC-Q100 QUALIFIED
The positive linear regulator (GH) is then softstarted and allowed to settle in one period of CT
ramp. Nine periods of the CT ramp have
occurred since the chip enabled. If all outputs
are in regulation (>80%), the CT will stop
ramping and be held at ground.
The RDY pin will be pulled down to an active
low. If any output remains below regulation
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