NB685
28V, 12A, Low Iq, High-Current,
Synchronous Buck Converter
with +/- 1A LDO and Buffered Reference
DESCRIPTION
FEATURES
The NB685 provides a complete power supply
with the highest density for DDR3, DDR3L,
LPDDR3, and DDR4 memory. It integrates a
high-frequency, synchronous, rectified, stepdown, switch-mode converter (VDDQ) with a
1A sink/source LDO (VTT) and buffered low
noise reference (VTTREF).
The NB685 operates at high efficiency over a
wide output current load range based on MPS
proprietary switching loss reduction technology
and internal low Ron power MOSFETs.
Adaptive constant-on-time (COT) control mode
provides fast transient response and eases loop
stabilization. The DC auto-tune loop provides
good load and line regulation.
The VTT LDO provides 1A sink/source current
capability and requires only 22μF ceramic
capacitors. The VTTREF tracks VDDQ/2 with
excellent 1% accuracy.
Wide 4.5V to 28V Operating Input Range
Compatible for IMVP8
135μA Low Quiescent Current
12A Continuous Output Current
13A Peak Output Current
Selectable Ultrasonic Mode
Selectable 500k/700k Switching Frequency
Built-In +/- 1A VTTLDO
1% Buffered VTTREF Output
Adaptive COT for Fast Transient
DC Auto-Tune Loop
Stable with POSCAP and Ceramic Output
Capacitors
Over-Temperature Warning
Internal Soft Start
Output Discharge
OCL, OVP, UVP, and Thermal Shutdown
Latch-Off Re-Set via EN or Power Cycle
QFN 3mm x 3mm Package
APPLICATIONS
Full protection features include OC limit, OVP,
UVP, thermal shutdown, and over-temperature
warning (OTW).
The converter requires a minimum number of
external components and is available in a QFN
3mm x 3mm package.
Laptop Computer
Networking Systems
Server
Distributed Power Systems
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS” and “The Future of Analog IC Technology” are
registered trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
VIN
VDDQ
1.35 V/10 A
220 nF
0.68 μH
4.5 V-24 V
VIN
OTW
BST
SW
22 μF x 1
28 kΩ
DDR_VTT_CONTROL
FB
EN 1
EN2
EN 2
22 μF x 3
22.1 kΩ
NB685
PG
VDDQ
100 kΩ
3V3
3.3 V
(Need external 3.3 V
power supply)
1 μF
VTTS
AGND
PGND
MODE
0Ω
NB685 Rev. 1.02
7/26/2017
VTT
0.675 V/1 A
VTT
22 μF
VTTREF
220 nF
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1
NB685–28 V, 12 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH +/-1 A LDO
ORDERING INFORMATION
Part Number*
Package
Top Marking
NB685GQ
QFN-16 (3mm x 3mm)
See Below
* For Tape & Reel, add suffix –Z (e.g. NB685GQ–Z)
TOP MARKING
AKU: Product code of NB685GQ
Y: Year code
LLL: Lot number
PACKAGE REFERENCE
TOP VIEW
VIN
PGND
NB685 Rev. 1.02
7/26/2017
EN1
EN2
MODE
FB
PG
OTW
16
15
14
13
12
11
1
10
BST
9
SW
2
3
4
5
3V3
AGND
VTT
6
7
8
VDDQ VTTREF VTTS
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2
NB685–28 V, 12 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH +/-1 A LDO
ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage (VIN) ....................................28 V
VSW(DC) ........................................... -1V to 26 V
VSW (25 ns) .................................. -3.6 V to 28 V
VBST .................................................VSW + 4.5 V
IEN1,IEN2.....................................................100 µA
All other pins ............................. -0.3 V to +4.5 V
(2)
Continuous power dissipation (TA = +25°C)
QFN-16 (3mm x 3mm) .............................. 2.3 W
Junction temperature ............................... 150C
Lead temperature .................................... 260C
Storage temperature ................ -65C to +150C
Recommended Operating Conditions
(3)
Supply voltage (VIN) ...................... 4.5 V to 24 V
Supply voltage (VCC) ...................3.15 V to 3.5 V
(5)
Output voltage (VDDQ)................ 0.6 V to 3.3 V
IEN1,IEN2.............. .......................... ............. 50 μA
Operating junction temp. (TJ). .. -40°C to +125°C
NB685 Rev. 1.02
7/26/2017
Thermal Resistance
(4)
θJA
θJC
QFN-16 (3mm x 3mm) ........... 55 ...... 13 ... C/W
NOTES:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation
produces an excessive die temperature, causing the regulator
to go into thermal shutdown. Internal thermal shutdown
circuitry protects the device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
5) For applications that need 3.3 V < Vout < 5.5 V, special
design requirements are needed. Please refer to the
application information section. VDDQ still requires voltage
≤ 3.3 V.
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3
NB685–28 V, 12 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH +/-1 A LDO
ELECTRICAL CHARACTERISTICS
VIN = 12 V, 3V3 = 3.3 V, TJ = 25C, RMODE = 0, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
Supply current
3V3 supply current in normal
mode
I3V3
VEN1 = VEN2 = 3 V, no load
185
µA
3V3 supply current in S3 mode
I3V3_S3
VEN1 = 0 V,VEN2 = 3 V,
no load
135
µA
3V3 shutdown current
I3V3_SDN
VEN1 = VEN2 = 0 V, no load
High-side switch on resistance
HSRDS-ON
TJ = 25C
19.5
mΩ
Low-side switch on resistance
LSRDS-ON
TJ = 25C
6.6
mΩ
Switch leakage
SW LKG
VEN = 0 V, VSW = 0 V
1
µA
MOSFET
0
1
μA
13
14
A
Current limit
Low-side valley current limit
ILIMIT
12
Switching frequency and minimum off time
Switching frequency
FS
Constant on timer
TON
(6)
Minimum on time
(6)
Minimum off time
RMODE = 0
700
kHz
RMODE =150 k
Vin = 6 V, VOUT = 3 V,
RMODE = 150 k
500
kHz
1100
TON_MIN
TOFF_MIN
1200
1300
ns
70
300
ns
ns
32
µs
Ultrasonic mode
Ultrasonic mode operation period
TUSM
VFB = 0.62 V
Protection
OVP threshold
UVP-1 threshold
(6)
UVP-1 foldback timer
UVP-2 threshold
VOVP
VUVP-1
TUVP-1
VUVP-2
125
70%
VREF
IFB
TSStart
TSStop
594
45%
130
75%
30
50%
135
80%
600
10
2.2
2
606
50
2.6
55%
%VREF
VREF
µs
VREF
Reference and soft start/soft stop
Reference voltage
Feedback current
Soft-start time
Soft-stop time
NB685 Rev. 1.02
7/26/2017
VFB = 0.62 V
EN to PG up
1.8
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mV
nA
ms
ms
4
NB685–28 V, 12 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH +/-1 A LDO
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12 V, 3V3 = 3.3 V, TJ = 25C, RMODE = 0, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
0.54
0.59
0.64
V
Enable and UVLO
En1 rising threshold
VEN1_TH
En1 hysteresis
VEN1-HYS
En2 rising threshold
VEN2_TH
En2 hysteresis
VEN2-HYS
Enable input current
VCC under-voltage lockout
threshold rising
VCC under-voltage lockout
threshold hysteresis
VIN under-voltage lockout
threshold rising
VIN under-voltage lockout
threshold hysteresis
NB685 Rev. 1.02
7/26/2017
125
1.12
1.22
mV
1.32
125
mV
VEN1/2 = 2 V
5
VEN1/2 = 0 V
1
IEN1/2
VCCVth
2.9
3.0
VCCHYS
220
VINVTH
4.2
VINHYS
360
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V
3.1
μA
V
mV
4.4
V
mV
5
NB685–28 V, 12 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH +/-1 A LDO
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12 V, TJ = 25C, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
Power good
PG when FB rising (good)
PG_Rising(GOOD)
PG when FB falling (fault)
PG_Falling(Fault)
PG when FB rising (fault)
PG_Rising(Fault)
PG when FB falling (good)
PG_Falling(GOOD)
PG low to high delay
EN low to PG low delay
Power good sink current
capability
VFB rising,
percentage of VFB
VFB falling,
percentage of VFB
VFB rising,
percentage of VFB
VFB falling,
percentage of VFB
95
90
%
115
105
PGTd
PGTd_EN low
VPG
1
μs
μs
0.4
V
3
Sink 4 mA
VTTREF output
VTTREF output voltage
Output
VDDQ
voltage
VTTREF
tolerance
Current limit
to
VTTREF/ VDDQ
VDDQ/2
IVTTREF < 0.1 mA,
1 V < VDDQ < 1.5 V
IVTTREF < 10 mA,
1 V < VDDQ < 1.5 V
ILIMIT_VTTREF
49.2%
50%
50.8%
49%
50%
51%
13
15
mA
VTT LDO
VTT output voltage
VTT
VDDQ/2
-10 mA < IVTT < 10 mA,
VTT tolerance to VTTREF
VTT-VTTREF
Source current limit
Sink current limit
OTW#
Over-temperature warning
(6)
OTW# hysteresis
ILIMIT_SOURCE
ILIMIT_SINK
(6)
OTW# sink current capability
OTW# leakage current
(6)
OTW# assertion time
Thermal protection
(6)
VDDQ = [1 V-1.5 V]
-0.6 A < IVTT < 0.6 A,
VDDQ= [1 V-1.5 V]
-1A < IVTT < 1 A,
VDDQ = [1 V-1.5 V]
Thermal shutdown
Thermal shutdown hysteresis
TSD
TSD_HYS
15
mV
-20
20
mV
-25
25
mV
1.2
1.2
TOTW#
TOTW#_HYS
VOTW#
IOTW#
TOTW#
-15
1.5
1.5
A
A
130
25
°C
°C
Sink 4 mA
VOTW# = 3.3 V
0.4
1
32
V
μA
ms
145
25
°C
°C
NOTE:
6) Guaranteed by design.
NB685 Rev. 1.02
7/26/2017
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6
NB685–28 V, 12 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH +/-1 A LDO
PIN FUNCTIONS
PIN #
Name
1
VIN
2
PGND
3
3V3
4
AGND
5
VTT
6
VDDQ
7
VTTREF
8
VTTS
9
SW
10
BST
11
OTW#
12
PG
13
FB
14
MODE
15/16
EN2/EN1
NB685 Rev. 1.02
7/26/2017
Description
Supply voltage. VIN supplies the power for the internal MOSFET and regulator. The
NB685 operates from a +4.5 V to +24 V input rail. An input capacitor is needed to
decouple the input rail. Use wide PCB traces and multiple vias to make the connection.
Power ground. Use wide PCB traces and multiple vias to make the connection.
External 3V3 VCC input for control and driver. Place a 1 µF decoupling capacitor
close to 3V3 and AGND. It is recommended to form an RC filter.
Analog ground. The internal reference is referred to AGND. Connect the GND of the
FB resistor divider to AGND for better load regulation.
VTT LDO output. Decouple with a minimum 22 µF ceramic capacitor as close to VTT
as possible. X7R or X5R dielectric ceramic capacitors are recommended for their
stable temperature characteristics.
Input of VTTLDO and used for Vout sense. Connect VDDQ to the output capacitor of
the regulator directly with a thick (>100 mil) trace. Do NOT float VDDQ.
Buffered VTT reference output. Decouple with a minimum 0.22 µF ceramic capacitor
as close to VTTREF as possible. X7R or X5R grade dielectric ceramic capacitors are
recommended for their stable temperature characteristics.
VTT output sense. Connect VTTS to the output capacitor of the VTT regulator directly.
Switch output. Connect SW to the inductor and bootstrap capacitor. SW is connected
to VIN when the HS-FET is on, and it is connected to PGND when the LS-FET is on.
Use wide and short PCB traces to make the connection. SW is noisy, so keep sensitive
traces away from SW.
Bootstrap. A capacitor connected between SW and BST is required to form a floating
supply across the high-side switch driver.
Over-temperature status. OTW# indicates that the part is close to the OTP. It is
pulled low once the junction temperature is higher than the over-temperature warning
point. OTW# can be left open if not used.
Power good output. PG is an open-drain signal. It is high if the output voltage is within
a proper range.
Feedback. An external resistor divider from the output to GND (tapped to the FB) sets
the output voltage. Place the resistor divider as close to FB as possible. Avoid vias on
the FB traces.
MODE to select the switching frequency and ultrasonic mode. A 1 percent pulldown resistor is needed.
Enable. EN1 and EN2 are digital inputs, which are used to enable or disable the
internal regulators. Once EN1 = EN2 = 1, the VDDQ regulator, VTT LDO, and VTTREF
output are turned on; when EN1 = 0 and EN2 = 1, all the regulators are on except the
VTT LDO; all the regulators are turned off when EN2 = 0 or EN1 = EN2 = 0.
Do NOT float EN1 at any time. If the VTT LDO function is not used, tie EN1 to GND.
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7
NB685–28 V, 12 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH +/-1 A LDO
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 20 V, VDDQ = 1.35 V, L = 0.68 µH/3.1 mΩ, FSW = 700 kHz, unless otherwise noted.
NB685 Rev. 1.02
7/26/2017
www.MonolithicPower.com
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© 2017 MPS. All Rights Reserved.
8
NB685–28 V, 12 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH +/-1 A LDO
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 20 V, VDDQ = 1.35 V, L = 0.68 µH/3.1 mΩ, FSW = 700 kHz, unless otherwise noted.
NB685 Rev. 1.02
7/26/2017
www.MonolithicPower.com
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9
NB685–28 V, 12 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH +/-1 A LDO
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 20 V, VDDQ = 1.35 V, L = 0.68 µH/3.1 mΩ, FSW = 700 kHz, unless otherwise noted.
NB685 Rev. 1.02
7/26/2017
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10
NB685–28 V, 12 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH +/-1 A LDO
FUNCTIONAL BLOCK DIAGRAM
AGND
MODE
3V3
OTW
EN2
EN1
VIN
BST
BSTREG
3V3
VIN
POR &
Reference
Soft Start
FB
FB
On Time
One Shot
REF
Min off time
Control
Logic
SW
VDDQ
DC Error
Correction
+
+
Output
Discharge
PGND
Vref
SW
OC Limit
130% Vref
OVP
PG
FB
95% Vref
POK
50% Vref
UVP-2
75% Vref
UVP-1
Fault
logic
VDDQ
EN1/EN2
Control
VTTREF
VTT
VTTS
Figure 1—Functional block diagram
NB685 Rev. 1.02
7/26/2017
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11
NB685–28 V, 12 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH +/-1 A LDO
OPERATION
PWM Operation
The NB685 is a fully integrated, synchronous,
rectified, step-down, switch-mode converter with
+/-1 A LDO current. Constant-on-time (COT)
control provides fast transient response and
eases loop stabilization. At the beginning of each
cycle, the high-side MOSFET (HS-FET) is turned
on when the feedback voltage (VFB) is below the
reference voltage (VREF), which indicates
insufficient output voltage. The on period is
determined by both the output voltage and the
input voltage to make the switching frequency
fairly constant over the input voltage range.
After the on period elapses, the HS-FET is turned
off or enters an off state. It is turned on again
when VFB drops below VREF. By repeating
operation this way, the converter regulates the
output voltage. The integrated low-side MOSFET
(LS-FET) is turned on when the HS-FET is in its
off state to minimize the conduction loss. A dead
short between the input and GND occurs if both
the HS-FET and the LS-FET are turned on at the
same time (shoot-through). In order to avoid
shoot-through, a dead time (DT) is generated
internally between the HS-FET off and the LSFET on period or the LS-FET off and the HS-FET
on period.
Internal compensation is applied for COT control
for stable operation even when ceramic
capacitors are used as output capacitors. This
internal compensation improves the jitter
performance without affecting the line or load
regulation.
CCM Operation
Figure 2—CCM Operation
NB685 Rev. 1.02
7/26/2017
Continuous conduction mode (CCM) occurs if the
output current is high, and the inductor current is
always above zero amps (see Figure 2).
When VFB is below VREF, the HS-FET is turned on
for a fixed interval, which is determined by the
one-shot on timer. See Equation (1). When the
HS-FET is turned off, the LS-FET is turned on
until the next period.
In CCM operation, the switching frequency is
fairly constant (PWM mode).
DCM Operation
When the load decreases, the inductor current
will decrease as well. Once the inductor current
reaches zero, the part transitions from CCM to
discontinuous conduction mode (DCM).
DCM operation is shown in Figure 3. When VFB is
below VREF, the HS-FET turns on for a fixed
interval, which is determined by the one-shot on
timer. See Equation (1). When the HS-FET is
turned off, the LS-FET is turned on until the
inductor current reaches zero. In DCM operation,
the VFB does not reach VREF when the inductor
current is approaching zero. The LS-FET driver
turns into tri-state (high Z) when the inductor
current reaches zero. A current modulator takes
over the control of the LS-FET and limits the
inductor current to less than -1 mA. Hence, the
output capacitors discharge slowly to GND
through the LS-FET. As a result, the efficiency
during the light-load condition is
improved
greatly. The HS-FET is not turned on as
frequently during a light-load condition as it is
during a heavy-load condition (skip mode).
At a light-load or no-load condition, the output
drops very slowly, and the NB685 reduces the
switching frequency naturally, achieving high
efficiency at light load.
Figure 3—DCM Operation
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12
NB685–28 V, 12 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH +/-1 A LDO
As the output current increases from the lightload condition, the time period within which the
current modulator regulates becomes shorter.
The HS-FET is turned on more frequently; the
switching frequency increases accordingly. The
output current reaches the critical level when the
current modulator time is zero. The critical level
of the output current is determined with Equation
(1):
IOUT _ Critical
( VIN VOUT ) VOUT
2 L FS VIN
(1)
The part enters PWM mode once the output
current exceeds the critical level. After that, the
switching frequency stays fairly constant over the
output current range.
Jitter and FB Ramp
Jitter occurs in both PWM and skip mode when
noise in the VFB ripple propagates a delay to the
HS-FET driver (see Figure 4 and Figure 5). Jitter
can affect system stability with noise immunity
proportional to the steepness of VFB’s downward
slope, so the jitter in DCM is usually larger than
in CCM. However, VFB ripple does not directly
affect noise immunity.
Figure 4—Jitter in PWM mode
Usually, ceramic capacitors cannot be used
directly as output capacitors.
The NB685 has built-in internal ramp
compensation to ensure the system is stable
even without the help of an output capacitor’s
ESR. Thus the pure ceramic capacitor solution
applies. The pure ceramic capacitor solution
reduces significantly the output ripple, the total
BOM cost, and the board area.
Figure 6 shows a typical output circuit in PWM
mode without an external ramp circuit. Refer to
the application information section for design
steps without external compensation.
L
Vo
SW
C4
FB
R1
R2
CAP
Figure 6—Simplified output circuit
When using a large capacitor (e.g., OSCON) on
the output, add a ceramic capacitor with a
value >10 µF in parallel to minimize the effect of
ESL.
Operating with External Ramp Compensation
Usually, the NB685 supports ceramic output
capacitors without external ramp. However, in
some cases, the internal ramp may not be
enough to stabilize the system, or the jitter is too
big, which will require external ramp
compensation. Refer to the application
information section for design steps with external
ramp compensation.
VTT and VTTREF
Figure 5—Jitter in skip mode
Operation—No External Ramp Compensation
The traditional constant-on-time control scheme
is intrinsically unstable if the output capacitor’s
ESR is not large enough to act as an effective
current-sense resistor.
NB685 Rev. 1.02
7/26/2017
NB685 integrates high performance, low drop-out
linear regulators (VTT and VTTREF) to provide
complete DDR3/DDR3L power solutions. The
VTTREF has a 10 mA sink/source current
capability and always tracks 1/2 of VDDQ with
+/-1 percent accuracy using an on-chip divider. A
minimum 0.22 μF ceramic capacitor must be
connected close to the VTTREF terminal for
stable operation.
VTT responds quickly to track VTTREF with
+/-30 mV in all conditions. The current capability
of the VTT regulator is up to 1 A for
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13
NB685–28 V, 12 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH +/-1 A LDO
both sink and source modes. A minimum 22 μF
ceramic capacitor must be connected close to
the VTT terminal. The VTTS should be
connected to the positive node of the remote VTT
output capacitor as a separate trace from the
high-current line to VTT.
Configuring the EN Control
The NB685 has two enable pins to control the
on/off states of the internal regulators. VDDQ,
VTTREF, and VTT are turned on at S0 (EN1 =
EN2 = high). In S3 (EN1 = low, EN2 = high),
VDDQ and VTTREF voltages remain on while
VTT is turned off and left at a high-impedance
state (high Z). The VTT output floats and does
not sink/source current in this state. In S4/S5
(EN1 = EN2 = low), all of the regulators remain
off and discharge to GND through a soft
shutdown. See EN1/EN2 logic details in Table 1.
Table 1—EN1/EN2 control
State
EN1
EN2
VDDQ VTTREF
VTT
S0
High
High
ON
ON
ON
S3
Low
High
ON
ON
OFF(High-Z)
S4/S5
Low
Low
OFF
OFF
OFF
Others
High
Low
OFF
OFF
OFF
Ultrasonic Mode (USM)
Ultrasonic mode (USM) keeps the switching
frequency above an audible frequency area
during light-load or no-load conditions. Once the
part detects that both the HS-FET and the LSFET are off (for about 32 µs), it forces PWM to
initiate Ton, so the switching frequency is out of
audio range. To avoid Vout becoming too high,
NB685 will then shrink Ton to control the Vout. If
the part’s FB is still too high after shrinking Ton to
its minimum value, the output discharge function
is activated and keeps the Vout within a
reasonable range. USM is selected by MODE.
Table 2—Mode selection
State
USM
Fs
Resistor to GND
M1
No
700 KHz
0
M2
Yes
700 KHz
90 K
M3
No
500 KHz
150 K
M4
Yes
500 KHz
> 230 K or float
VDDQ Power Good (PG)
The NB685 has power good (PG) output, which
indicates whether the output voltage of the
VDDQ regulator is ready. PG is the open drain of
a MOSFET. PG should be connected to VCC or
another voltage source through a resistor (e.g.
100 k). After the input voltage is applied, the
MOSFET is turned on so that PG is pulled to
GND before SS is ready. After the FB voltage
reaches 95 percent of the REF voltage, PG is
pulled high (after a delay time within 10 µs).
When the FB voltage drops to 90 percent of the
REF voltage, PG is pulled low.
Soft Start (SS)
The NB685 employs a soft-start (SS) mechanism
to ensure smooth output during power-up. When
EN becomes high, the internal reference voltage
ramps up gradually; this causes the output
voltage to ramp up smoothly as well. Once the
reference voltage reaches the target value, the
soft start finishes, and the part enters steadystate operation.
The start-up sequence is shown in Figure 7.
VIN
VIN UVLO
0
EXT
3V3
VCC UVLO
0
EN2
EN2 Rising
Threshold
0
EN1
MODE Select
EN1 Rising
Threshold
0
NB685
implements
MODE
for
multiple
applications for USM and switching frequency
selection. USM and the switching frequency can
be selected by a different resistor on the 3V3
logic mode pin. There are four modes that can be
selected for normal application with external
resistors (see Table 2); it is recommended to use
a 1 percent accuracy resistor.
NB685 Rev. 1.02
7/26/2017
VDDQ
0
Soft Start
VTTREF
/VTT
0
PG
0
Figure 7—Start-up power sequence
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14
NB685–28 V, 12 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH +/-1 A LDO
If the output is pre-biased to a certain voltage
during start-up, the IC disables the switching of
both the high-side and low-side switches until the
voltage on the internal reference exceeds the
sensed output voltage at the FB node.
Soft Shutdown
The NB685 employs a soft-shutdown mechanism
for DDR to ensure VTTREF and VTT follow
exactly half of the VDDQ. When EN2 is low, the
internal reference ramps down gradually, so the
output voltage falls linearly. Figure 8 shows the
soft-shutdown sequence.
EN2
0
Since the comparison is done during the LS-FET
on state, the OC trip level sets the valley level of
the inductor current. The maximum load current
at the over-current threshold (Ioc) is calculated
with Equation (2):
IOC I _ limit
Iinductor
2
(2)
The OCL limits the inductor current and does not
latch off. In an over-current condition, the current
to the load exceeds the current to the output
capacitor; thus the output voltage tends to fall off.
Eventually, it ends up with crossing the undervoltage protection (UVP) threshold and latches
off. Fault latching can be re-set by EN going low
or the power cycling of VIN.
VTT/VTTREF Over-Current Protection (OCP)
PG
The VTT LDO has an internally non-latch fixed
current limit of 1.5 A for both sink and source
operation. Once the current limit is reached, it
adjusts the gate of the sink/source MOSFET to
limit the current. Also, VTTREF has an internal
non-latch 15 mA current limit.
0
VDDQ
0
VTTREF
/VTT
0
VDDQ Over/Under-Voltage Protection
Soft
Shutdown
Figure 8—Soft-shutdown sequence
VDDQ Over-Current Limit (OCL)
NB685 has cycle-by-cycle over-current limiting
control. The current-limit circuit employs a
"valley" current-sensing algorithm. The part uses
the Rds(on) of the LS-FET as a current-sensing
element. If the magnitude of the current-sense
signal is above the current-limit threshold, the
PWM is not allowed to initiate a new cycle even if
FB is lower than REF. Figure 9 shows the
detailed operation of the valley current limit
Valley_ILim
FB
REF
PWM
FB 13 A.
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18
NB685–28 V, 12 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH +/-1 A LDO
RECOMMENDED PCB LAYOUT
5. Place the external feedback resistors next to
FB. Make sure that there is no via on the FB
trace.
6. Keep the BST voltage path (BST, C3, and
SW) as short as possible.
7. Keep the IN and GND pads connected with a
large copper plane to achieve better thermal
performance. Add several vias with a 10 mil
drill/18 mil copper width close to the IN and
GND pads to help thermal dissipation.
8. A 4-layer layout is strongly recommended to
achieve better thermal performance.
PCB Layout Guidelines
Efficient PCB layout is critical for optimal
performance of the IC. For best results, refer to
Figure 13 and follow the guidelines below. For
more information, refer to AN087.
1. Keep the VDDQ trace width >100 mil to avoid
a voltage drop on the input of the VTTLDO.
2. Place the high-current paths (GND, IN, and
SW) very close to the device with short, direct,
and wide traces. A thick PGND trace under
the IC is the number one priority.
3. Place the input capacitors as close to IN and
GND as possible on the same layer as the IC.
4. Place the decoupling capacitor as close to
VCC and GND as possible. Keep the
switching node (SW) short and away from the
feedback network.
To Vout
To AGND
VCC
0402
PG
EN1
EN2
MODE
FB
PG
OTW
16
15
14
13
12
11
OTW
0603
VIN
SW
VIN
1
10
BST
9
SW
2 PGND
3
4
5
3V3
AGND
VTT
6
7
8
VDDQ VTTREF VTTS
L
7mm*6.6mm
>100Mil
AGND–PGND KELVIN
CONNECTION
PGND
VOUT
0805
VOUT
Figure 13—Recommended PCB layout
NB685 Rev. 1.02
7/26/2017
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19
NB685–28 V, 12 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH +/-1 A LDO
Recommend Design Example
Table 3.2—Design example for 700 KHz Fsw
For applications that need current over 10 A, it is
recommended to apply a 500 KHz fsw part for
better thermal performance and efficiency (see
Table 3.1). Otherwise, a 700 kHz fsw operation
will make the system more compact with faster
transient.
There is a resistor from the external 3.3 V power
supply to 3V3 acting as a ripple noise filter of the
3.3 V power supply. It is recommended to have a
resistor value from 0 Ω-5.1Ω depending on the
noise level. A 0402 size resistor will suffice if the
3.3 V voltage rises up with SS > 100 µs.
Otherwise, a larger sized resistor (e.g.,
0603/0805) is needed.
For applications when Vin is 5 V or lower, it is
recommended to apply the SCH shown in Figure
15 with a proper external ramp.
NB685 also supports non-DDR application with
very compact external components (see Figure
16).
Design examples are provided in Table 3.1 and
Table 3.2 when ceramic capacitors are applied.
Table 3.1—Design example for 500 kHz Fsw
VOUT
(V)
Cout
(F)
L
(μH)
RMode
(Ω)
C4
(pF)
R1
(kΩ)
R2
(kΩ)
1.0
22 μx 4
1.0
150 K
220
13.3
20
1.2
22 μ x 4
1.0
150 K
220
20
20
1.35
22 μ x 4
1.0
150 K
220
28
22.1
1.5
22 μ x 4
1.2
150 K
220
30.1
20
1.8
22 μ x 4
1.5
150 K
220
40.2
20
NB685 Rev. 1.02
7/26/2017
VOUT
(V)
Cout
(F)
L
(μH)
RMode
(Ω)
C4
(pF)
R1
(kΩ)
R2
(kΩ)
1
22 μ x 3
0.68
0
220
13.3
20
1.2
22 μ x 3
0.68
0
220
20
20
1.35
22 μ x 3
0.68
0
220
28
22.1
1.5
22 μ x 3
0.68
0
220
30.1
20
1.8
22 μ x 3
0.68
0
220
40.2
20
Other Design Examples with higher Vout
NB685 supports designs that need Vout in the
range of 3.3 V to 5.5 V. Figure 17 shows a SCH
with a 5 V Vout with proper external settings.
Please pay attention to the red components, and
please note that USM is not allowed for this
application.
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20
NB685–28 V, 12 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH +/-1 A LDO
TYPICAL APPLICATION
DDR Application for Vin >6 V
2.2 Ω
VIN
6 V-24 V
VDDQ
1.35 V/10 A
220 nF
0.68 μH
VIN
OTW
BST
SW
22 μF x 1
NS
499 Ω
DDR_VTT_CONTROL
22 μF x 3
28 kΩ
220 pF
EN 1
FB
NB685
EN 2
EN 2
22.1 kΩ
PG
VDDQ
100 kΩ
5.1 Ω
3.3 V
(Need external 3.3 V
power supply)
3V3
1 μF
VTT
0.675 V/1 A
VTT
22 μF
VTTSEN
AGND
PGND
VTTREF
MODE
0Ω
220 nF
Figure 14 — Typical DDR application circuit, VIN = 6 V-24 V, VOUT = 1.35 V, IOUT = 10 A, with VTT
Fs = 700 kHz
DDR Application Cover 5 V Vin
2.2 Ω
VIN
VDDQ
1.35 V/10 A
220 nF
0.68 μH
4.5 V-24 V
VIN
22 μF x 2
OTW
BST
SW
499 kΩ
1M
499 Ω
220 pF
26.1 kΩ
22 μF x 4
EN 1
EN 2
NB685
FB
20 kΩ
PG
100 kΩ
VDDQ
5.1 Ω
3.3 V
(Need external 3.3 V
power supply)
3V3
1 μF
VTTSEN
AGND
PGND
VTT
0.675 V/1 A
VTT
MODE
0Ω
22 μF
VTTREF
220 nF
Figure 15— Typical DDR application circuit, VIN = 4.5 V-24 V, VOUT = 1.35 V, IOUT = 10 A, with VTT
Fs = 700 kHz
NB685 Rev. 1.02
7/26/2017
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21
NB685–28 V, 12 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH +/-1 A LDO
Non-DDR Application
2.2 Ω
VIN
VDDQ
1 V/10 A
220 nF
0.68 μH
4.5 V-24 V
OTW
VIN
BST
SW
NS
22 μF x 1
13.3 kΩ
FB
EN 1
EN2
220 pF
499 Ω
NB685
EN 2
22 μF x 3
20 kΩ
PG
VDDQ
100 kΩ
5.1 Ω
3.3 V
(Need external 3.3 V
power supply)
3V3
1 μF
VTT
VTTS
AGND
PGND
VTTREF
MODE
0Ω
Figure 16 — Normal single buck application circuit, VIN = 4.5 V-24 V, VOUT = 1 V, IOUT = 10 A, without
VTT Fs = 700 kHz.
SPECIAL APPLICATION—WITH 3.3 V < VOUT < 5.5 V
2.2 Ω
VIN
7 V-24 V
220 nF
1.5 μH
VIN
OTW
BST
5 V/10 A
SW
22 μF x 1
VDDQ
330 kΩ
220 pF
93.1 kΩ
22 μF x 4
EN 1
EN2
EN 2
499 Ω
NB685
FB
PG
2k
VDDQ
100 kΩ
5.1 Ω
3.3 V
(Need external 3.3 V
power supply)
3k
3V3
1 μF
10 kΩ
VTT
VTTSEN
AGND
PGND
MODE
VTTREF
150 kΩ
NOTE1: Ultrasonic mode is not effective if applied in this SCH.
NOTE 2: The maximum load is 10 A in this application. Fs is set with a 500 kHz mode, but actually is 700
kHz.
NOTE 3: It is recommended to avoid VDDQ voltage over 3.3 V by using the external resistor setting.
Figure 17 — Special application circuit, VIN = 7 V-24 V, VOUT = 5 V, IOUT = 10 A, Fs = 700 kHz.
NB685 Rev. 1.02
7/26/2017
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22
NB685–28 V, 12 A, HIGH-CURRENT SYNCHRONOUS BUCK CONVERTER WITH +/-1 A LDO
PACKAGE INFORMATION
QFN-16 (3mm x 3mm)
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTE:
1) ALL DIMENSIONS ARE IN
MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT
INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
NB685 Rev. 1.02
7/26/2017
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