MP38872
6A, 21V, 600kHz Step-Down Converter
with Synchronizable Gate Driver
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP38872 is a monolithic step-down switch
mode converter with a built in high-side internal
power MOSFET and a gate driver for a low-side
external MOSFET. It achieves 6A continuous
output current over a wide input supply range
with excellent load and line regulation.
•
•
•
•
•
Current mode operation provides fast transient
response and reliable over-current protection.
•
•
•
•
•
•
The MP38872 requires a minimum number of
readily available standard external components
and is available in a 14-pin QFN 3x4 package
with exposed pad.
•
Wide 4.5V to 21V Operating Input Range
6A Output Current
45mΩ Internal Power MOSFET Switch
Power Good Indicator
Synchronizable Gate Driver Delivers up to
95% Efficiency
Fixed 600kHz Frequency
Synchronizable to >1MHz External Clock
Cycle-by-Cycle Over Current Protection
Thermal Shutdown
Output Adjustable from 0.8V
Stable with Low ESR Output Ceramic
Capacitors
Available in a Thermally Enhanced 14-Pin
QFN 3x4 Package
APPLICATIONS
•
•
•
•
•
Point of Load Regulator in Distributed
Power System
Digital Set Top Boxes
Personal Video Recorders
Broadband Communications
Flat Panel Television and Monitors
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“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
C1
22uF
25V
Power Good
OFF ON
BST
SW
12
C3
1uF
16V
IN
R3
100kΩ
2
3
8, 9, 10
VCC
MP38872 BG
Efficiency vs
Output Current
11
13
C4
1uF
16V
L1
2.2uH
100
VOUT
3.3V
M2
R1
40.2kΩ
C2
100uF
6.3V
PG
EN/SYNC
FB
GND
14
1
R2
13kΩ
95
90
EFFICIENCY (%)
VIN
4, 5, 6
85
VIN=12V
80
75
VIN=20V
70
65
60
VOUT=3.3V
55
50
0
1
2
3
4
5
OUTPUT CURRENT (A)
MP38872 Rev.1.11
www.MonolithicPower.com
9/21/2011
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© 2011 MPS. All Rights Reserved.
6
1
MP38872 – 6A, 21V, 600kHz STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER
ORDERING INFORMATION
Part Number*
MP38872DL
Package
QFN14 (3x4)
Top Marking
38872
Free Air Temperature (TA)
–40°C to +85°C
* For Tape & Reel, add suffix –Z (e.g. MP38872DL–Z);
For RoHS Compliant Packaging, add suffix –LF (e.g. MP38872DL–LF–Z)
PACKAGE REFERENCE
TOP VIEW
PIN 1 ID
FB
1
14
GND
PG
2
13
BG
EN/SYNC
3
12
VCC
IN
4
11
BST
IN
5
10
SW
IN
6
9
SW
N/C
7
8
SW
EXPOSED PAD
ON BACKSIDE
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance
Supply Voltage VIN ....................................... 23V
VSW ........................-0.3V (-5V for < 10ns) to 24V
VBS - VSW ......................................................... 6V
All Other Pins .................................–0.3V to +6V
Continuous Power Dissipation
(TA = +25°C)(2)
QFN14L (3mm x 4mm) .............................. 2.6W
Junction Temperature ...............................150°C
Lead Temperature ....................................260°C
Storage Temperature.............. –65°C to +150°C
QFN14L (3mm x 4mm) ........... 48 ...... 11... °C/W
Recommended Operating Conditions
(3)
Supply Voltage VIN ...........................4.5V to 21V
Output Voltage VOUT .........................0.8V to 15V
Maximum Junction Temp. (TJ). ...............+125°C
(4)
θJA
θJC
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/ θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD5 1-7, 4-layer PCB.
MP38872 Rev.1.11
www.MonolithicPower.com
9/21/2011
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
2
MP38872 – 6A, 21V, 600kHz STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = +25°C, unless otherwise noted.
Parameters
Feedback Voltage
Feedback Current
Switch On Resistance (5)
Switch Leakage
Current Limit (5)
Oscillator Frequency
Fold-back Frequency
Maximum Duty Cycle
Minimum On Time (5)
Under Voltage Lockout Threshold Rising
Under Voltage Lockout Threshold Hysteresis
EN Input Low Voltage
EN Input High Voltage
Symbol Condition
VFB
4.5V ≤ VIN ≤ 23V
IFB
VFB = 0.8V
RDS(ON)
VEN = 0V, VSW = 0V
7.5
fSW
VFB = 0.6V
VFB = 0V
VFB = 0.6V
85
tON
VCC_UVLO
3.9
Typ
0.808
10
45
0
8.0
600
150
90
100
4.1
880
Max
0.821
10
4.3
0.4
1.2
VEN = 2V
VEN = 0V
EN Input Current
Sync Frequency Range (Low)
Sync Frequency Range (High)
Enable Turnoff Delay
Supply Current (Shutdown)
Supply Current (Quiescent)
Thermal Shutdown
Thermal Shutdown Hysteresis
BG Driver Bias Supply Voltage
Gate Driver Sink Impedance (5)
Gate Driver Source Impedance (5)
Gate Drive Current Sense Trip Threshold
Power Good Control
Power Good Threshold Rising
Power Good Threshold Hysteresis
PG Pin Level
Min
0.795
FSYNCL
FSYNCH
TOFF
VEN = 0V
VEN = 2V, VFB = 1V
TJ
VCC
RSINK
RSOURCE
4.5
0.69
VPG
2
0
300
1.5
5.0
1
0.9
150
10
5
1
4
20
0.74
40
PG Sink 4mA
Units
V
nA
mΩ
μA
A
KHz
KHz
%
ns
V
mV
V
V
μA
10
0.79
0.4
KHz
MHz
us
μA
mA
°C
°C
V
Ω
Ω
mV
V
mV
V
Note:
5) Guaranteed by design.
MP38872 Rev.1.11
www.MonolithicPower.com
9/21/2011
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
3
MP38872 – 6A, 21V, 600kHz STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER
PIN FUNCTIONS
Pin #
Name
Description
Feedback. An external resistor divider from the output to GND, tapped to the FB pin sets
the output voltage. To prevent current limit run away during a short circuit fault condition the
1
FB
frequency foldback comparator lowers the oscillator frequency when the FB voltage is
below 250mV.
Power Good Indicator. The output of this pin is low if the output voltage is 10% less than the
2
PG
nominal voltage; otherwise it is an open drain.
3
EN/SYNC On/Off Control and External Frequency Synchronization Input.
Supply Voltage. The MP38872 operates from a +4.5V to +21V unregulated input. C1 is
4, 5, 6
IN
needed to prevent large voltage spikes from appearing at the input.
7
N/C
No Connect
8, 9, 10
SW
Switch Output.
Bootstrap. This capacitor is needed to drive the power switch’s gate above the supply
11
BST
voltage. It is connected between SW and BS pins to form a floating supply across the power
switch driver. A 1µF capacitor is recommended for use.
BG Driver Bias Supply. Decouple with a 1µF ceramic capacitor. X7R or X5R grade dielectric
12
VCC
ceramic capacitors are recommended for their stable temperature characteristics.
13
BG
Gate Driver Output. Connect this pin to the gate of the synchronous MOSFET.
Ground. This pin is the voltage reference for the regulated output voltage. For this reason
14
GND
care must be taken in its layout. This node should be placed outside of the M2 to C1 ground
path to prevent switching current spikes from inducing voltage noise into the part.
MP38872 Rev.1.11
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9/21/2011
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© 2011 MPS. All Rights Reserved.
4
MP38872 – 6A, 21V, 600kHz STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 2.5V, L = 2.2µH, TA = +25ºC, unless otherwise noted.
MP38872 Rev.1.11
www.MonolithicPower.com
9/21/2011
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
5
MP38872 – 6A, 21V, 600kHz STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 2.5V, L = 2.2µH, TA = +25ºC, unless otherwise noted.
1100
Enabled Supply Current
vs. Input Voltage
1.0
VCC Regulator Line
Regulation (ICC = 10mA)
Disabled Supply Current
vs. Input Voltage
4.9
0.9
1050
0.8
4.7
0.7
4.5
1000
VCC (V)
0.6
0.5
0.4
0.3
950
3.7
Case Temperature vs.
Output Current
40
35
2
3
4
5
OUTPUT CURRENT (A)
1.4MHz
1MHz
1
VFB_MIN
10
1.001
PEAK CURRENT(A)
NORMALIZED OUTPUT VOLTAGE
4
1.000
0.999
0.998
0.997
0
600KHz
5
10
15
20
INPUT VOLTAGE (V)
4.5
5
5.5
6
6.5
INPUT VOLTAGE (V)
7
Load Regulation
10
0.1
6
1.002
0.995
3.5
25
DMAX Limit
Line Regulation
0.996
5
10
15
20
INPUT VOLTAGE (V)
100
45
1
0
Operating Range
50
30
0
25
NORMALIZED OUTPUT VOLTAGE(V)
5
10
15
20
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
CASE TEMPERATURE (OC)
55
0
4.1
3.9
0.2
0.1
900
4.3
25
1.002
VIN=12V
1.001
1
0.999
VIN=20V
0.998
0.997
0.996
0.995
0
1
2
3
4
5
LOAD CURRENT (A)
6
Peak Current
vs. Duty Cycle
8
6
4
2
ILOAD=6A
5
7
9 11 13 15 17 19 21
INPUT VOLTAGE(V)
0
10
30
50
70
Duty Cycle (%)
90
MP38872 Rev.1.11
www.MonolithicPower.com
9/21/2011
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
6
MP38872 – 6A, 21V, 600kHz STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER
OPERATION
IN
CURRENT SENSE
AMPLIFIER
D
+
-REGULATOR
BST
EN/SYNC
REGULATOR
OSCILLATOR
600KHz
S
+
--
VCC
REFERENCE
FB
DRIVER
R
CURRENT
LIMIT
COMPARATOR
1pF
Q
R
SW
Q
VCC
54pF
+
--
ERROR
AMPLIFIER
VCC
COMP
+
--
DRIVER
PWM
COMPARATOR
BG
GND
0.74V
PG
POWER
GOOD
Figure 1—Functional Block Diagram
The MP38872 is a fixed frequency,
synchronous, step-down switching regulator
with an integrated high-side power MOSFET
and a gate driver for a low-side external
MOSFET. It achieves 6A continuous output
current over a wide input supply range with
excellent load and line regulation. It provides a
single highly efficient solution with current mode
control for fast loop response and easy
compensation.
The MP38872 operates in a fixed frequency,
peak current control mode to regulate the
output voltage. A PWM cycle is initiated by the
internal clock. The integrated high-side power
MOSFET is turned on and remains on until its
current reaches the value set by the COMP
voltage. When the power switch is off, it
remains off until the next clock cycle starts. If, in
90% of one PWM period, the current in the
power MOSFET does not reach the COMP set
current value, the power MOSFET will be
forced to turn off.
Error Amplifier
The error amplifier compares the FB pin voltage
with the internal 0.8V reference (REF) and outputs a
current proportional to the difference between the
two. This output current is then used to charge or
discharge the internal compensation network to
form the COMP voltage, which is used to control the
power MOSFET current. The optimized internal
compensation network minimizes the external
component counts and simplifies the control loop
design.
Internal Regulator
Most of the internal circuitries are powered from the
5V internal regulator. This regulator takes the VIN
input and operates in the full VIN range. When VIN
is greater than 5.0V, the output of the regulator is in
full regulation. When VIN is lower than 5.0V, the
output decreases. Since this internal regulator
provides the bias current for the bottom gate driver
that requires significant amount of current
depending upon the external MOSFET selection, a
1uF ceramic capacitor for decoupling purpose is
required.
MP38872 Rev.1.11
www.MonolithicPower.com
9/21/2011
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
7
MP38872 – 6A, 21V, 600kHz STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER
Enable/Synch Control
The MP38872 has a dedicated Enable/Synch
control pin (EN/SYNC). By pulling it high or low,
the IC can be enabled and disabled by EN. Tie
EN to VIN for automatic start up. To disable the
part, EN must be pulled low for at least 5µs.
The MP38872 can be synchronized to external
clock range from 300KHz up to 1.4MHz through
the EN/SYNC pin. The internal clock rising
edge is synchronized to the external clock rising
edge.
Under-Voltage Lockout (UVLO)
Under-voltage lockout (UVLO) is implemented
to protect the chip from operating at insufficient
supply
voltage.
The
MP38872
UVLO
comparator monitors the output voltage of the
internal regulator, VCC. The UVLO rising
threshold is about 4.0V while its falling
threshold is a consistent 3.6V.
Internal Soft-Start
The soft-start is implemented to prevent the
converter output voltage from overshooting
during startup. When the chip starts, the
internal circuitry generates a soft-start voltage
(SS) ramping up from 0V to 1.2V. When it is
lower than the internal reference (REF), SS
overrides REF so the error amplifier uses SS as
the reference. When SS is higher than REF,
REF regains control.
Over-Current-Protection and Hiccup
The MP38872 has cycle-by-cycle over current
limit when the inductor current peak value
exceeds the set current limit threshold.
Meanwhile, output voltage starts to drop until
FB is below the Under-Voltage(UV) threshold,
typically 30% below the reference. Once a UV
is triggered, the MP38872 enters hiccup mode
to periodically restart the part. This protection
mode is especially useful when the output is
dead-short to ground. The average short circuit
current is greatly reduced to alleviate the
thermal issue and to protect the regulator. The
MP38872 exits the hiccup mode once the over
current condition is removed.
Thermal Shutdown
Thermal shutdown is implemented to prevent
the chip from operating at exceedingly high
temperatures. When the silicon die temperature
is higher than 150°C, it shuts down the whole
chip. When the temperature is lower than its
lower threshold, typically 140°C, the chip is
enabled again.
Floating Driver and Bootstrap Charging
The floating power MOSFET driver is powered
by an external bootstrap capacitor. This floating
driver has its own UVLO protection. This
UVLO’s rising threshold is 2.2V with a
hysteresis of 150mV. The bootstrap capacitor
voltage is regulated internally (Figure 2). Even
at no load condition, as long as VIN is 3V higher
than VOUT, C4 will have enough voltage
provided by VIN through D1, M1, C4, L1 and C2.
If (VIN-VSW) is more than 5V, U2 will regulate M1
to maintain a 5V BST voltage across C1.
D1
VIN
M1
+
5V
+
--
BST
U2
--
C4
VOUT
SW
L1
C2
Figure 2—Internal Bootstrap Charging
Circuit
Startup and Shutdown
If both VIN and EN are higher than their
appropriate thresholds, the chip starts. The
reference block starts first, generating stable
reference voltage and currents, and then the
internal regulator is enabled. The regulator
provides stable supply for the remaining
circuitries.
Three events can shut down the chip: EN low,
VIN low and thermal shutdown. In the shutdown
procedure, the signaling path is first blocked to
avoid any fault triggering. The COMP voltage
and the internal supply rail are then pulled down.
The floating driver is not subject to this
shutdown command.
MP38872 Rev.1.11
www.MonolithicPower.com
9/21/2011
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
8
MP38872 – 6A, 21V, 600kHz STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER
APPLICATION INFORMATION
The schematic on the front page shows a typical
MP38872 application. The IC can provide up to
6A output current at a nominal output voltage of
3.3V. For proper thermal performance, the
exposed pad of the device must be soldered
down to the printed circuit board.
Synchronous MOSFET
The external synchronous MOSFET is used to
supply current to the inductor when the internal
high-side switch is off. It significantly reduces
the power loss when compared against a
Schottky rectifier.
Setting the Output Voltage
The external resistor divider is used to set the
output voltage (see the schematic on front
page). The feedback resistor R1 also sets the
feedback loop bandwidth with the internal
compensation capacitor (see Figure 1). Choose
R1 to be around 40.2kΩ for optimal transient
response. R2 is then given by:
Table 2 lists example synchronous MOSFETs
and manufacturers.
R2 =
R1
VOUT
−1
0 .8 V
Table 1—Resistor Selection for Common
Output Voltages
VOUT (V)
1.8
2.5
3.3
5
R1 (kΩ)
40.2 (1%)
40.2 (1%)
40.2 (1%)
40.2 (1%)
R2 (kΩ)
32.4 (1%)
19.1 (1%)
13 (1%)
7.68 (1%)
Selecting the Inductor
A 1µH to 10µH inductor with a DC current rating
of at least 25% percent higher than the
maximum load current is recommended for
most applications. For highest efficiency, the
inductor DC resistance should be less than
15mΩ. For most designs, the inductance value
can be derived from the following equation.
L=
VOUT × ( VIN − VOUT )
VIN × ΔIL × f OSC
Where ΔIL is the inductor ripple current.
Choose inductor current to be approximately
30% of the maximum load current, 6A. The
maximum inductor peak current is:
IL(MAX ) = ILOAD +
ΔI L
2
Under light load conditions below 100mA, larger
inductance is recommended for improved
efficiency.
Table 2—Synchronous MOSFET Selection
Guide
Part No.
Manufacture
FDS6670AS
IRF7821
AM4874
Fairchild
International Rectifier
Analog Power
Selecting the Input Capacitor
The input capacitor (C1) reduces the surge
current drawn from the input and the switching
noise from the device. The input capacitor
impedance at the switching frequency should
be less than the input source impedance to
prevent high frequency switching current from
passing to the input. Ceramic capacitors with
X5R
or
X7R
dielectrics
are
highly
recommended because of their low ESR and
small temperature coefficients. For 6A output
applications, a 22µF capacitor is sufficient.
Selecting the Output Capacitor
The output capacitor (C2) keeps output voltage
small and ensures regulation loop stability. The
output capacitor impedance should be low at
the switching frequency. Ceramic capacitors
with X5R or X7R dielectrics are recommended.
PC Board Layout
The high current paths (GND, IN and SW)
should be placed very close to the device with
short, direct and wide traces. The input
capacitor needs to be as close as possible to
the IN and GND pins. The external feedback
resistors should be placed next to the FB pin.
Keep the switching node SW short and away
from the feedback network. Keep the EN trace
away from the feedback network, and also an
isolation with ground trace between the EN and
FB pins (highly recommended).
MP38872 Rev.1.11
www.MonolithicPower.com
9/21/2011
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
9
MP38872 – 6A, 21V, 600kHz STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER
External Bootstrap Diode
An external bootstrap diode may enhance the
efficiency of the regulator, the applicable
conditions of external BST diode is:
z
Duty cycle is high: D=
VOUT
>65%
VIN
In these cases, an external BST diode is
recommended from the output of the voltage
regulator to BST pin, as shown in Fig.3
BST
MP38872
SW
External BST Diode
IN4148
VCC
CBST
L
COUT
Figure 3—Add Optional External Bootstrap
Diode to Enhance Efficiency
The recommended external BST diode is
IN4148, and the BST cap is 0.1~1µF.
MP38872 Rev.1.11
www.MonolithicPower.com
9/21/2011
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
10
MP38872 – 6A, 21V, 600kHz STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER
PACKAGE INFORMATION
QFN14L w/EXPOSED PAD (3mm x 4mm)
2.90
3.10
1.60
1.80
0.30
0.50
PIN 1 ID
MARKING
PIN 1 ID
SEE DETAIL A
1
14
0.18
0.30
3.20
3.40
3.90
4.10
PIN 1 ID
INDEX AREA
0.50
BSC
7
8
TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION A
0.30x45º TYP.
0.80
1.00
0.20 REF
PIN 1 ID OPTION B
R0.20 TYP.
0.00
0.05
SIDE VIEW
DETAIL A
2.90
0.70
NOTE:
1.70
1)
2)
3)
4)
5)
0.25
ALL DIMENSIONS ARE IN MILLIMETERS.
EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
DRAWING CONFORMS TO JEDEC MO-229, VARIATION VEED-5.
DRAWING IS NOT TO SCALE.
3.30
0.50
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP38872 Rev.1.11
www.MonolithicPower.com
9/21/2011
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2011 MPS. All Rights Reserved.
11
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