MP38891DL-LF-Z

MP38891 6A, 30V, 420kHz Step-Down Converter with Synchronizable Gate Driver The Future of Analog IC Technology DESCRIPTION FEATURES The MP38891 is a monolithic step-down switch mode converter with a built in internal power MOSFET. It achieves 6A continuous output current over a wide input supply range with excellent load and line regulation. • • • • Current mode operation provides fast transient response and eases loop stabilization. • • • • • • Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. The MP38891 requires a minimum number of readily available standard external components and is available in a space saving 3mm x 4mm 14-pin QFN package. • Wide 4.5V to 30V Operating Input Range 6A Output Current 50mΩ Internal Power MOSFET Switch Synchronizable Gate Driver Delivers up to 95% Efficiency Fixed 420kHz Frequency Synchronizable up to 1.4MHz Cycle-by-Cycle Over Current Protection Thermal Shutdown Output Adjustable from 0.8V to 15V Stable with Low ESR Output Ceramic Capacitors Available in a Thermally Enhanced 3mm x 4mm 14-Pin QFN Package APPLICATIONS • • • • Digital Set Top Boxes Personal Video Recorders Broadband Communications Flat Panel Television and Monitors “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION VIN 4,5,6 IN BST 11 MP38891 SW 12 VCC BG OFF ON 3 2 8,9,10 EN/SYNC PG FB 13 1 GND 14 MP38891 Rev.1.1 9/21/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 1 MP38891 – 6A, 30V, 420kHz STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER ORDERING INFORMATION Part Number* MP38891DL Package 3x4 QFN14 Top Marking Free Air Temperature (TA) 38891 -40°C to +85°C * For Tape & Reel, add suffix –Z (g. MP38891DL–Z). For RoHS compliant packaging, add suffix –LF (e.g. MP38891DL–LF–Z) PACKAGE REFERENCE TOP VIEW PIN 1 ID FB 1 14 GND PG 2 13 BG EN/SYNC 3 12 VCC IN 4 11 BST IN 5 10 SW IN 6 9 SW N/C 7 8 SW ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance Supply Voltage VIN ....................................... 32V VSW ..........................-0.3V(-5V for 65% VIN In these cases, an external BST diode is recommended from the output of the voltage regulator to BST pin, as shown in Fig.3 External BST Diode IN4148 BST MP38891 SW CBST L + COUT 5V or 3.3V Figure 3—Add Optional External Bootstrap Diode to Enhance Efficiency The recommended external BST diode is IN4148, and the BST cap is 0.1~1µF. In the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. The output voltage ripple is mainly caused by the capacitance. For simplification, the output voltage ripple can be estimated by: ΔVOUT = ⎞ ⎛ V × ⎜⎜1 − OUT ⎟⎟ V × L × C2 ⎝ IN ⎠ VOUT 8 × fS 2 In the case of tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated to: ΔVOUT = VOUT ⎛ V × ⎜⎜1 − OUT fS × L ⎝ VIN ⎞ ⎟⎟ × R ESR ⎠ The characteristics of the output capacitor also affect the stability of the regulation system. The MP38891 can be optimized for a wide range of capacitance and ESR values. MP38891 Rev.1.1 9/21/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 11 MP38891 – 6A, 30V, 420kHz STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER PCB Layout Guide PCB layout is very important to achieve stable operation. Please follow these guidelines and take Figure 4 for references. 4 layers PCB layout is recommended. 1) Keep the path of switching current short and minimize the loop area formed by Input cap, high-side and low-side MOSFETs. 2) Keep the connection of low-side MOSFET between SW pin and input power ground as short and wide as possible. Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close to the chip as possible. 4) Route SW away from sensitive analog areas such as FB. 5) Connect IN, SW, and especially GND respectively to a large copper area to cool the chip to improve thermal performance and long-term reliability. For single layer, do not solder exposed pad of the IC. SGND R1 R2 FB 1 14 GND R4 PG 2 13 BG EN 3 12 VCC IN 4 IN 5 10 SW Cb IN 6 9 SW N/ C 7 8 SW R3 C1 3) C3 2 11 BST Rb 2 C2 L1 8 1 SGND 7 2 PGND 6 3 5 4 Top Layer Inner Layer 1 2 2 SGND SGND Inner Layer 2 Bottom Layer Figure 4—PCB Layout MP38891 Rev.1.1 9/21/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 12 MP38891 – 6A, 30V, 420kHz STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER PACKAGE INFORMATION 3mm x 4mm QFN14 2.90 3.10 1.60 1.80 0.30 0.50 PIN 1 ID MARKING PIN 1 ID SEE DETAIL A 1 14 0.18 0.30 3.20 3.40 3.90 4.10 PIN 1 ID INDEX AREA 0.50 BSC 8 TOP VIEW 7 BOTTOM VIEW 0.80 1.00 0.20 REF PIN 1 ID OPTION A 0.30x45º TYP. PIN 1 ID OPTION B R0.20 TYP. 0.00 0.05 SIDE VIEW DETAIL A 2.90 0.70 NOTE: 1.70 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE0.10 MILLIMETER MAX. 4) JEDEC REFERENCE IS MO-229, VARIATION VGED-3. 5) DRAWING IS NOT TO SCALE. 0.25 3.30 0.50 RECOMMENDED LAND PATTERN NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP38891 Rev.1.1 9/21/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 13