MP2930
4-Phase PWM Controller
With 8-Bit DAC code for VR10 and VR11
DESCRIPTION
The MP2930 is a 4-phase, synchronous buck
switching regulator controller for regulating
microprocessor core voltage. MP2930 also uses
dual edge PWM mode to realize fast load
transient with fewer capacitors.
For meeting the requirement of microprocessor
output voltage drops tightly as load current
increases, output current is sensed to realize
voltage droop function. Accurate current
balancing is included in MP2930 to provide
current balance for each channel.
8-bit ID input with selectable VR11 code and
extended VR10 code can set output voltage
dynamically.
The MP2930 also provides accurate and reliable
over current protection and over voltage
protection.
FEATURES
2-, 3- or 4-phase Operation
Channel-Current Balancing
Voltage Droop vs. Load Current
Precision Resistor or DCR Current Sensing
8-Bit ID Input with Selectable Between VR11
and VR10 Code at 6.25mV Per Bit
Adjustable Switching Frequency
Over Current Protection
Over Voltage Protection
Available in a 40-pin QFN6x6 Package
APPLICATIONS
Power Modules
Desktop, Server, Core Voltage
POLs (Memory)
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Quality Assurance. “MPS” and “The
Future of Analog IC Technology” are Registered Trademarks of Monolithic
Power Systems, Inc.
TYPICAL APPLICATION (4-PHASE BUCK CONVERTER)
MP2930 Rev. 1.01
10/30/2013
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1
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
ORDERING INFORMATION
Part Number*
Package
Top Marking
Free Air Temperature (TJ)
MP2930GQK
QFN (6 x 6mm)
MP2930GQK
-40C to +125C
* For Tape & Reel, add suffix –Z (e.g. MP2930GQK–Z);
For RoHS compliant packaging, add suffix –LF; (e.g. MP2930GQK –LF–Z).
PACKAGE REFERENCE
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VCC .....................................6V
All Other Pins ..................... -0.3V to VCC + 0.3V
Continuous Power Dissipation (TA = +25°C) (2)
............................................................3.9W
Junction Temperature .............................. 150C
Storage Temperature ............... -65C to +150C
ESD Rating
Human Body Model .................................... 2kV
Machine Model ..........................................200V
Charged Device Model ............................. 1.5kV
Recommended Operating Conditions (3)
Supply Voltage VCC .......................... +5V ±5%
Operating Junction Temp. (TJ). -40°C to +125°C
MP2930 Rev. 1.01
10/30/2013
Thermal Resistance
(4)
θJA
θJC
QFN40 (6mm x 6mm)............. 32 ...... 3.5 .. C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ (MAX)TA) /θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will
go into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
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© 2013 MPS. All Rights Reserved.
2
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
ELECTRICAL CHARACTERISTICS
Operating conditions: VCC = 5V, unless otherwise noted.
Parameter
Test conditions
Min
Typ
Max
Units
18
26
mA
14
21
mA
4.3
3.7
0.850
0.71
0.850
0.71
4.5
3.9
0.88
130
0.745
0.88
130
0.745
4.7
4.2
0.910
0.78
0.910
0.78
V
V
V
mV
V
V
mV
V
-0.5
-
0.5
℅ID
0.9
℅ID
VCC Supply Current
Nominal Supply
Shutdown Supply
VCC=5VDC;
EN_PWR=5VDC;
RT=100kΩ,
ISEN1=ISEN2=ISEN3=ISEN4=-70uA
VCC=5VDC; EN_PWR=0VDC;
RT=100 kΩ
Power-on Reset and Enable
POR Threshold
EN_PWR Threshold
EN_VTT Threshold
VCC Rising
VCC Falling
Rising
Hysteresis
Falling
Rising
Hysteresis
Falling
Reference Voltage and DAC
System Accuracy of MP2930
(ID =1V to 1.6V, TJ=0C to +70C)
System Accuracy of MP2930
(ID =0.5V to 1V, TJ=0C to +70C)
ID Pull-Up
ID Input Low Level
ID Input High Level
VRSEL Input Low Level
VRSEL Input High Level
DAC Source Current
DAC Sink Current
Pin-adjustable Offset
Voltage at OFS Pin
Oscillators
Accuracy of Switching Frequency
setting
Adjustment Range of Switching
Frequency
Soft-Start Ramp Rate
Adjustment Range of Soft-Start
Ramp Rage
Error Amplifier
Maximum Output Voltage
Output High Voltage @ 2mA
Output Low Voltage @ 2mA
MP2930 Rev. 1.01
10/30/2013
-0.9
Offset resistor connected to ground
Voltage below VCC, offset resistor
connected to VCC
RT=100kΩ
RS=150kΩ
-60
0.8
0.8
-
-40
4
-
-20
0.4
0.4
7
320
μA
V
V
V
V
mA
μA
380
400
420
mV
1.55
1.600
1.65
V
225
250
275
kHz
0.08
-
1.0
MHz
-
1.563
-
mV/μs
0.625
-
6.25
mV/μs
3.8
3.6
-
4.2
-
4.6
1.8
V
V
V
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3
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
ELECTRICAL CHARACTERISTICS (continued)
Operating conditions: VCC = 5V, unless otherwise noted.
Parameter
Test conditions
Remote-sense Amplifier
Bandwidth
Output High Current
VSEN-RGND=2.5V
Output High Current
VSEN-RGND=0.6
PWM Output
PWM Output Voltage Low
ILOAD=±500μA
Threshold
PWM Output Voltage High
ILOAD=±500μA
Threshold
Current Sense and Over-current Protection
Sensed
Current
ISEN1=ISEN2=ISEN3=ISEN4=50μA
Tolerance(IDROOP)
Overcurrent
Trip
level
for
Average Current
Peak Current Limit for Individual
Channel
Thermal Monitoring and Fan Control
TM Input Voltage for VR_FAN
TRIP
TM Input Voltage for VR_FAN
Reset
TM Input Voltage for VR_HOT
Trip
TM Input Voltage for VR_HOT
Reset
With externally pull-up resistor
Leakage current of VR_FAN
connected to VCC
VR_RAN Low Voltage
IVR_FAN=4mA
With externally pull-up resistor
Leakage Current of VR_HOT
connected to VCC
VR_HOT Low Voltage
IVR_HOT=4mA
VR Ready and Protection Monitors
With externally pull-up resistor
Leakage Current of VR_RDY
connected to VCC
VR_RDY Low Voltage
IVR_RDY=4mA
Undervoltage Threshold
VDIFF Falling
VR_RDY Reset Voltage
VDIFF Rising
Overvoltage
Protection Before Valid ID
Threshold
After valid ID, the voltage above ID
Overvoltage Protection Reset
Hysteresis
MP2930 Rev. 1.01
10/30/2013
Min
Typ
Max
Units
-100
-100
20
-
100
100
MHz
μA
μA
-
-
0.5
V
4.3
-
-
V
47
50
53
μA
72
85
98
μA
μA
120
1.55
1.65
1.75
V
1.85
1.95
2.05
V
1.3
1.4
1.5
V
1.55
1.65
1.75
V
-
-
30
μA
-
-
0.4
V
-
-
30
μA
-
-
0.4
V
-
-
30
μA
48
58
1.250
150
50
60
1.275
175
0.4
52
62
1.300
200
V
℅ID
℅ID
V
Mv
-
100
-
mV
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4
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
PIN FUNCTIONS
Pin #
Name
1
2
3
ID6
ID5
ID4
4
5
6
7
ID3
ID2
ID1
ID0
8
VRSEL
9
OFS
10
DAC
11
REF
12
13
14
15
COMP
FB
IDROOP
VDIFF
16
17
RGND
VSEN
18
SD
19
20
21
22
VCC
PWM1
ISEN1+
ISEN1-
23
24
25
26
27
28
29
ISEN4+
ISEN4PWM4
PWM2
ISEN2+
ISEN2ISEN3-
30
31
ISEN3+
PWM3
32
EN_PWR
33
EN_VTT
MP2930 Rev. 1.01
10/30/2013
Description
ID inputs from microprocessor. These codes determine output regulation voltage.
Select internal ID code. When it is tied to GND, the extended VR10 is selected. When
it’s floated or tied to high, VR11 code is selected.
Offset between REF and DAC program pin. The OFS pin can be used to program a DC
offset current which will generate a DC offset voltage between the REF and DAC pins.
The polarity of the offset is selected by connecting the resistor to GND or VCC. For no
offset, the OFS pin should be left unconnected.
Internal DAC reference output determined by ID codes
Error amplifier input. A capacitor 0.1uF is used between REF and GND to smooth the
voltage transition during Dynamic ID operations.
Error amplifier output pin. Tie to compensation network
Output voltage feedback pin.
Current proportional to load current is flowed out through this pin
Remote sense amplifier output. VDIFF-GND=VSEN-RGND
Remote sense amplifier input. Remote output GND
Remote sense amplifier input. Remote output.
Shutdown Intelli-phase @ Hiz state. MP2930 cooperates with MPS Intelli-phase
MP86961 and SD pin is connected to the EN of MP86961.
Power supply. Connect this pin directly to a +5V supply.
Phase 1 PWM output.
Phase 1 current sense amplifier differential input
Phase 4 current sense amplifier differential input
Phase 4 PWM output. Connect PWM4 to VCC to configure for 3-phase operation.
Phase 2 PWM output.
Phase 1 current sense amplifier differential input
Phase 3 current sense amplifier differential input
Phase 3 PWM output. Connect PWM3 to VCC to configure for 2-phase operation.
Enable pin. It is used to synchronize power-up of the controller and MOSFET driver
ICs.
Enable pin. It is controlled by output of VTT voltage regulator in the mother board.
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5
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
PIN FUNCTIONS (continued)
Pin #
Name
34
FS
35
SS
36
VR_RDY
37
38
VR_FAN
VR_HOT
39
TM
40
ID7
MP2930 Rev. 1.01
10/30/2013
Description
PWM frequency set pin. A resistor from FS to GND will set the switching frequency.
Soft start oscillator frequency set pin. A resistor from SS to GND will set up the softstart ramp rate.
Open drain logic output. When soft start completed and output voltage is regulated in
the value determined by ID setting, VR_RDY is logic high.
Open drain logic output. It is open when VR temperature reaches certain value
Open drain logic output. It is open when VR temperature reaches certain value
NTC resistor in this pin is used to monitor inductor temperature. Connect this pin
through an NTC thermistor to GND and a resistor to VCC of the controller. The voltage
at this pin is reverse proportional to the VR temperature.
ID input
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6
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
TYPICAL PERFORMANCE CHARACTERISTICS
VIN=12V, VID =1.2V, L=0.3µH, Fsw=600kHz, Inductor DCR Sensing, 4-Phase Operation, TA=+25°C,
unless otherwise noted.
MP2930 Rev. 1.01
10/30/2013
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7
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=12V, VID =1.2V, L=0.3µH, Fsw=600kHz, Inductor DCR Sensing, 4-Phase Operation, TA=+25°C,
unless otherwise noted.
MP2930 Rev. 1.01
10/30/2013
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8
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
BLOCK DIAGRAM
VDIFF
VR_RDY
RGND
FS
VCC
CLOCK AND
RAMP GENETATOR
POWER-ON
RESET (POR)
0.875
X1
EN_VTT
VSEN
N
0.875
OVP
EN_PWR
SOFT-START
AND
FAULT LOGIC
+175mV
PWM
MODULATOR
PWM1
SS
VRSEL
PWM
MODULATOR
ID7
PWM2
ID6
ID5
ID4
ID3
DYNAMIC
VID
D/A
PWM
MODULATOR
ID2
PWM3
ID1
ID0
DAC
PWM
MODULATOR
OFS
PWM4
OFFSET
REF
CHANNEL
CURRENT
BALANCE
AND PEAK
CURRENT LIMIT
E/A
FB
COMP
CHANNEL
DETECT
N
I_TRIP
ISEN1+
ISEN1-
OCP
ISEN2+
CHANNEL
CURRENT
SENSE
IDROOP
1
N
Σ
ISEN2ISEN3+
ISEN3ISEN4+
ISEN4-
VR_HOT
THERMAL
MONITOR
SHUTDOWN
DRIVER MOS @
Hiz STATE
TM
SD
VR_FAN
GND
Figure 1—Function Block Diagram
MP2930 Rev. 1.01
10/30/2013
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9
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
OPERATION
Multiphase Power Conversion
The MP2930 is a multiphase regulators and it
can be programmed for 2-, 3- or 4-channel
operation for microprocessor core. The
switching of each channel in a multiphase
converter is timed to be symmetrically out-ofphase with each of the other channels. The
interleaving work of each phase can help to
reduce of ripple current amplitude and to
reduce input ripple current.
PWM Operation
Under steady state conditions the operation of
the MP2930 appears to be that of a
conventional
trailing
edge
modulator.
Conventional analysis and design methods can
be used for steady state and small signal
operation.
RT
2.5 1010
FSW
(1)
Where FSW is the switching frequency of each
phase.
Current Sensing
MP2930 has cycle by cycle current sense for
fast response. MP2930 adopts inductor DCR
sensing, or resistive sensing techniques. The
sense current, ISEN, is proportional to the
inductor current. The sensed current is used for
current balance, load-line regulation, and
overcurrent protection.
Inductor DCR Sensing
The MP2930 can adopt a lossless current
sensing scheme, commonly referred to as
inductor DCR sensing, as shown in Figure 2.
Under load transition condition, the MP2930
can turn on all phase together to improve the
load transient. It can achieve excellent transient
performance and reduce the demand on the
output capacitors.
The default channel setting for the MP2930 is
four and the timing of each channel is set by the
number of active channels. The cycle time of
the pulse signal is the inverse of the switching
frequency set by the resistor between the FS
pin and GND.
For 4-channel operation, the channel firing
order is 4-3-2-1: PWM3 pulse happens 1/4 of a
cycle after PWM4, PWM2 output follows
another 1/4 of a cycle after PWM3, and PWM1
delays another 1/4 of a cycle after PWM2. For
3-channel operation, the channel firing order is
3-2-1.
Connecting PWM4 to VCC selects 3-phase
operation and the pulse times are spaced in 1/3
cycle increments. If PWM3 is connected to VCC,
2-phase operation is selected and the PWM2
pulse happens 1/2 of a cycle after PWM pulse.
Switching Frequency
The MP2930 switching frequency is set by the
external resistor RT between the FS pin and
GND. The resistor RT can be estimated by:
Equation (1).
MP2930 Rev. 1.01
10/30/2013
Figure 2—DCR Sensing Configuration
Equation (2) shows the s-domain equivalent
voltage across the inductor VL.
V I s L DCR
L L
(2)
A simple RC network across the inductor
extracts the DCR voltage, as shown in Figure 2.
The voltage on the capacitor VC is proportional
to the channel current IL, see Equation (3).
L
1 DCR I
s
L
DCR
V
C
s RC 1
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(3)
10
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
If the RC network components are selected
such that the RC time constant (=R*C) matches
the inductor time constant (=L/DCR), the
voltage across the capacitor VC is equal to the
voltage drop across the DCR, i.e., proportional
to the channel current.
Therefore, the current out of ISEN+ pin (ISEN), is
proportional to the inductor current and it can
be seen form Equation (4).
DCR
I
I
SEN L R
ISEN
(4)
Resistive Sensing
For accurate current sense, a current-sense
resistor RSENSE in series with each output
inductor can serve as the current sense
element (see Figure 3). This technique is more
accurate, but reduces overall converter
efficiency due to the additional power loss on
the current sense resistor RSENSE.
Channel-Current Balance
The sensed current In from each active channel
is summed together and divided by the number
of active channels. The resulting average
current (IAVG) provides a measure of the total
load current. Channel current balance is
achieved by comparing the sensed current of
each channel to the average current to make an
appropriate adjustment to the PWM duty cycle
of each channel.
Channel current balance is essential in
achieving the thermal advantage of multiphase
operation. With good current balance, the
power loss is equally dissipated over multiple
devices and a greater area.
Equation (5) shows the ratio of the channel
current to the sensed current ISEN.
Voltage Regulation
The compensation network shown in Figure 4
assures that the steady-state error in the output
voltage is limited only to the error in the
reference voltage (output of the DAC) and
offset errors in the OFS current source, remotesense and error amplifiers.
R
I
I SENSE
SEN L R
ISEN
The typical open-loop gain of error amplifier is
no less than 80dB, and the typical open-loop
bandwidth is no less than 20MHz.
(5)
IL
L
RSENSE
EXTERNAL CIRCUIT
VOUT
MP2930 INTERNAL CIRCUIT
COMP
COUT
RC
CC
DAC
MP2930 INTERNAL CIRCUIT
RREF
REF
RISEN(n)
In
CREF
VCOMP
FB
CURRENT
SENSE
ISEN-(n)
IDROOP
R FB
ISEN+(n)
IAVG
ERROR AMPLIFIER
VDROOP
VDIFF
CT
I SEN=I L
RSENSE
RISEN
Figure 3—Sense Resistor in Series with
Inductors
The inductor DCR value will increase as the
temperature increases. Therefore the sensed
current will increase as the temperature of the
current sense element increases. In order to
compensate the temperature effect on the
sensed current signal, a Positive Temperature
Coefficient (PTC) resistor can be selected for
the sense resistor RISEN.
MP2930 Rev. 1.01
10/30/2013
VOUT+
VSEN
VOUT-
RGND
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
Figure 4—Output Voltage and Load-line
Regulation with Offset Adjustment
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11
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
The output of the error amplifier (VCOMP) is
compared to sawtooth waveforms to generate
the PWM signals. The PWM signals control the
timing of the MP86961 and regulate the
converter output to the specified reference
voltage. The internal and external circuitry,
which control voltage regulation are shown in
Figure 4.
The MP2930 incorporates an internal
differential remote-sense amplifier in the
feedback path, which results in a more accurate
means of sensing output voltage. Connect the
microprocessor sense pins to the non-inverting
input (VSEN) and inverting input (RGND) of the
remote-sense amplifier. The remote-sense
output (VDIFF) is connected to the inverting
input of the error amplifier through an external
resistor.
Each ID input offers a 45µA pull-up to an
internal 2.5V source for use with open-drain
outputs. The pull-up current diminishes to zero
above the logic threshold to protect voltagesensitive output devices. External pull-up
resistors can augment the pull-up current
sources if case leakage into the driving device
is greater than 45µA.
I
RX
RFB
VOUT VREF VOFS OUT
N R
ISEN
Where VREF is the reference voltage, VOFS is the
programmed offset voltage, IOUT is the total
output current of the converter, RISEN is the
sense resistor connected to the ISEN+ pin, and
RFB is the feedback resistor, N is the active
channel number, and RX is the DCR, or RSENSE
depending on the sensing method.
Therefore the equivalent load-line impedance
(Droop impedance), can be derived from
Equation (8):
RLL
As shown in Figure 4, a current proportional to
the average current of all active channels (IAVG)
flows from FB through a load-line regulation
resistor RFB. The voltage drop across RFB is
proportional to the output current. It can be
derived from Equation (6):
V
I
R
DROOP AVG FB
(6)
The regulated output voltage is reduced by the
droop voltage VDROOP. The output voltage is a
function a load current, it’s derived by
combining Equation (6) with the appropriate
sensing current expression defined by the
current sense method employed in Equation (7).
MP2930 Rev. 1.01
10/30/2013
RFB
RX
N
RISEN
(8)
Output Voltage Offset Programming
In Figure 5, OFS pin is used to generate noload offset. A resistor RREF between DAC and
REF is selected, and the product (IOFS x ROFS) is
equal to the desired offset voltage.
FB
DYNAMIC
ID D/A
DAC
RREF
Load-Line Regulation
As the load current increases from zero, the
output voltage will drop from the ID table value
by an amount proportional to load current to
achieve the load-line.
Adding a Droop can help to reduce the output
voltage spike that result from fast load-current
demand changes.
(7)
REF
E/A
CREF
VCC
OR
GND
ROFS
1.6V
0.4V
MP2930
VCC
OFS
GND
Figure 5—Output Voltage Offset
Programming
Connect a resistor ROFS between OFS to VCC
to generate a positive offset. The voltage
across it is regulated to 1.6V. This causes a
proportional current (IOFS) to flow into OFS. The
positive offset is:
V
OFFSET
1.6 R
R
REF
(9)
OFS
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12
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
Connect a resistor ROFS between OFS to GND
to generate a negative offset. The voltage
across it is regulated to 0.4V, and IOFS flows out
of OFS. The negative offset is:
V
OFFSET
0.4 R
REF
R
OFS
(10)
some time, MP2930 reads the ID code at ID
input pins. If the ID code is valid, MP2930 will
regulate the output to the final ID setting. If the
ID code is OFF code, MP2930 will shutdown,
and cycling VCC, EN_PWR or EN_VTT is
needed to restart.
Soft-Start
The maximum Negative Offset for MP2930 is
150mV.
Enable and Disable
While in shutdown mode, the PWM outputs are
held in a Hi-Z state, and the SD signal is pulled
low to assure the Intelli-phase remain off. The
following input conditions must be met to start
MP2932.
1. VCC must reach the internal power-on reset
(POR) rising threshold.
2. EN_PWR is used to coordinate the power
sequencing between VCC and another
voltage rail. The enable comparator holds
the MP2932 in shutdown until the voltage at
EN_PWR rises above 0.875V.
3. The voltage on EN_VTT must be higher than
0.875V to enable the controller. This pin is
typically connected to the output of VTT VR.
MP2930 based VR has 4 periods during softstart as shown in Figure 7. After VCC, EN_VTT
and EN_PWR reach their POR/enable
thresholds, the controller will have fixed delay
period td1. After this delay period, the VR will
begin first soft-start ramp until the output
voltage reaches 1.1V voltage. Then, the
controller will regulate the VR voltage at 1.1V
for another fixed period td3. At the end of td3
period, MP2930 reads the ID signals. If the ID
code is valid, MP2930 will initiate the second
soft-start ramp until the voltage reaches the ID
voltage minus offset voltage.
1.1V
VOUT
td1
MP2930 INTERNAL CIRCUIT
VCC
POR
CIRCUIT
td2
td3
td4
td5
EXTERNAL CIRCUIT
+12V
ENABLE
COMPARATOR
10kΩ
EN_PWR
EN_VTT
VR_RDY
500us/DIV
910Ω
0.875V
EN_VTT
Figure 7—Soft-Start Waveforms
The soft-start time is the sum of the 4 periods,
as shown in Equation (12):
tSS td1 td2 td3 td4
0.875V
SOFT-START
AND
FAULT LOGIC
Figure 6—Power Sequencing Using
Threshold Sensitive Enable (EN) Function
When all conditions are satisfied, MP2930
begins the soft-start and ramps the output
voltage to 1.1V first. After remaining at 1.1V for
MP2930 Rev. 1.01
10/30/2013
(12)
td1 is a fixed delay with the typical value as
1.36ms. td3 is determined by the fixed 85µs plus
the time to obtain valid ID voltage. If the ID is
valid before the output reaches the 1.1V, the
minimum time to validate the ID input is 500ns.
Therefore the minimum td3 is about 86µs.
During td2 and td4, MP2930 digitally controls the
DAC voltage change at 6.25mV per step. The
time for each step is determined by the
frequency of the soft-start oscillator which is
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13
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
defined by the resistor RSS from SS pin to GND.
The second soft-start ramp time td2 and td4 can
be calculated based on Equations (13) and (14):
2 1.1 RSS
t
(us)
d2 3 6.25 25
t
d4
2 VVID 1.1 RSS
(us)
3
6.25 25
(13)
input, the OVP trip point will be changed to
DAC + 175mV.
Two actions are taken by the MP2930 to protect
the microprocessor load when an over-voltage
condition occurs.
VR_RDY
(14)
For example, when ID is set to 1.5V and the
RSS is set at 100kΩ, the first soft-start ramp time
td2 will be 469µs and the second soft-start ramp
time td4 will be 171µs.
After the DAC voltage reaches the final ID
setting, VR_RDY will be set to high with the
fixed delay td5. The typical value for td5 is 85µs.
Fault Monitoring and Protection
The MP2930 actively monitors output voltage
and current to detect fault conditions. One
common power good indicator is provided for
linking to external system monitors. The
schematic in Figure 8 outlines the interaction
between the fault monitors and the VR_RDY
signal.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output
to indicate that the soft-start period has
completed and the output voltage is within the
regulated range. VR_RDY is pulled low during
shutdown and releases high after a successful
soft-start and a fixed delay td5. VR_RDY will be
pulled low when an under-voltage or overvoltage condition is detected, or the controller is
disabled by a reset from EN_PWR, EN_VTT,
POR, or ID OFF-code.
Under-voltage Detection
The undervoltage threshold is set at 50% of the
ID code. When the output voltage at VSEN is
below the undervoltage threshold, VR_RDY is
pulled low.
Over-voltage Protection
Regardless of the VR being enabled or not, the
MP2930 over-voltage protection (OVP) circuit
will be active after its POR. The OVP thresholds
are different at different operation conditions.
When VR is not enabled and during the softstart intervals td1, td2 and td3, the OVP threshold
is 1.275V. Once the controller detects valid ID
MP2930 Rev. 1.01
10/30/2013
UV
50%
SOFT-START, FAULT
AND CONTROL LOGIC
DAC
85uA
OC
IAVG
VDIFF
OV
VID + 0.175V
Figure 8—VR_RDY and Protection Circuitry
At the beginning of an over-voltage event, all
PWM outputs are commanded low instantly
(>20ns). This causes the MP86961 to turn on
the lower MOSFETs and pull the output voltage
below a level to avoid damaging the load. When
the VDIFF voltage falls below the DAC + 75mV,
PWM signals enter a high-impedance state,
and the SD pin is pulled low to turn off the
MP86961.
Once an over-voltage condition is detected,
normal PWM operation ceases until the
MP2930 is reset. Cycling the voltage on
EN_PWR, EN_VTT or VCC below the PORfalling threshold will reset the controller. Cycling
the ID codes will not reset the controller.
Over-current Protection
MP2930 has two levels of over-current
protection. Each phase is protected from a
sustained over-current condition by limiting its
peak current, while the combined phase
currents are protected on an instantaneous
basis.
In instantaneous protection mode, the MP2930
utilizes the sensed average current IAVG to
detect an over-current condition. The average
current is continually compared with a constant
85µA reference current, as shown in Figure 8.
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14
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
Once the average current exceeds the
reference current, a comparator triggers the
converter to shutdown.
At the beginning of over-current shutdown, the
controller places all PWM signals in a highimpedance state within 20ns to turn off the
MP86961. The system remains in this state
about 12ms. If the controller is still enabled at
the end of this wait period, it will attempt a softstart. If the fault remains, the hiccup mode will
continue indefinitely until either controller is
disabled or the fault is cleared. Note that the
energy delivered during hiccup mode is much
less than during full-load operation, so there is
no thermal hazard during this kind of operation.
OUTPUT CURRENT
The VR_FAN signal indicates that the
temperature of the voltage regulator is high and
more cooling airflow is needed. The VR_HOT
signal can be used to inform the system that the
temperature of the voltage regulator is too high
and the CPU should reduce its power
consumption.
VCC
VR_FAN
R TM1
0.33VCC
VR_HOT
TM
RREF
°C
0.28VCC
Figure 10—Block Diagram of Thermal
Monitoring Function
0A
OUTPUT VOLTAGE
0V
Figure 9—Over-current Behavior in HICCUP
Mode. FSW = 600kHz
For the individual channel over-current
protection, the MP2930 continuously compares
the sensed current signal of each channel with
the 120µA reference current. If one channel
current exceeds the reference current, MP2930
will pull PWM signal of this channel to low for
the rest of the switching cycle. This PWM signal
can be turned on next cycle if the sensed
channel current is less than the 120µA
reference current. The peak current limit of
individual channel will not trigger the converter
to shutdown.
Thermal Monitoring (VR_HOT/VR_FAN)
There are two thermal signals to indicate the
temperature status of the voltage regulator:
VR_HOT and VR_FAN. Both VR_FAN and
VR_HOT pins are open-drain outputs, and
external pull-up resistors are required. Those
signals are valid after the controller is enabled.
MP2930 Rev. 1.01
10/30/2013
The diagram of thermal monitoring function
block is shown in Figure 10. One NTC resistor
should be placed close to the power stage of
the voltage regulator to sense the operational
temperature, and one pull-up resistor is needed
to form the voltage divider for the TM pin. As
the temperature of the power stage increases,
the resistance of the NTC will reduce, resulting
in the reduced voltage at the TM pin.
TM
0.39*VCC
0.33*VCC
0.28*VCC
VR_FAN
VR_HOT
TEMPERATURE
T1
T2
T3
Figure 11—VR_HOT and VR_FAN Signal vs.
TM Voltage
There are two comparators with hysteresis to
compare the TM pin voltage to the fixed
thresholds for VR_FAN and VR_HOT signals
respectively. The VR_FAN signal is set to high
when the TM voltage is lower than 33% of VCC
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15
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
voltage, and is pulled to GND when the TM
voltage increases to above 39% of VCC voltage.
The VR_FAN signal is set to high when the TM
voltage goes below 28% of VCC voltage, and is
pulled to GND when the TM voltage goes back
to above 33% of VCC voltage. Figure 11 shows
the operation of those signals.
Current Sense Output
The current from the IDROOP pin is the sensed
average current. In typical application, the
IDROOP pin is connected to the FB pin for the
application where load line is required.
When load line function is not needed, the
IDROOP pin can be used to obtain the load
current information: with one resistor from the
IDROOP pin to GND, the voltage at the
IDROOP pin will be proportional to the load
current in Equation (15):
R
R
X I
V
IDROOP
LOAD
IDROOP
N
R
ISEN
(15)
Where VIDROOP is the voltage at the IDROOP pin,
RIDROOP is the resistor between the IDROOP pin
and GND, ILOAD is the total output current of the
converter, RISEN is the sense resistor connected
to the ISEN+ pin, N is the active channel
number, and RX is the resistance of the current
sense element, either the DCR of the inductor
or RSENSE depending on the sensing method.
RIDROOP should be chosen to ensure that the
voltage at the IDROOP pin is less than 2V
under the maximum load current.
If the IDROOP pin is not used, tie it to GND.
MP2930 Rev. 1.01
10/30/2013
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16
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
APPLICATION INFORMATION
Current Sensing Resistor
The resistors connected to the ISEN+ pins
determine the gains in the load-line regulation
loop and the channel-current balance loop as
well as setting the over-current trip point. Select
values for these resistors by using Equation
(16):
R
ISEN
I
OCP
X
6
N
85 10
R
(16)
Where RISEN is the sense resistor connected to
the ISEN+ pin, N is the active channel number,
RX is the resistance of the current sense
element, either the DCR of the inductor or
RSENSE depending on the sensing method, and
IOCP is the desired over-current trip point.
Typically, IOCP can be chosen to be 1.3x the
maximum load current of the specific
application.
Compensation
There are two distinct methods for achieving
the compensation.
Compensating Load-Line Regulated
Converter
The load-line regulated converter behaves in a
similar manner to a peak-current mode
controller because the two poles at the outputfilter L-C resonant frequency split with the
introduction of current information into the
control loop. The final location of these poles is
determined by the system function, the gain of
the current signal, and the value of the
compensation components, RC and CC.
Treating the system as though it were a
voltage-mode regulator by compensating the LC poles and the ESR zero of the voltage-mode.
C2 (OPTIONAL)
Load-Line Regulation Resistor
The load-line regulation resistor is labeled RFB
in Figure 4. Its value depends on the desired
load-line requirement of the application.
The desired load-line can be calculated by
using Equation (17):
V
R DROOP
LL
I
FL
(17)
Where IFL is the full load current of the specific
application, and VRDROOP is the desired voltage
droop under the full load condition.
Based on the desired load-line RLL, the load-line
regulation resistor can be calculated by using
Equation (18):
R
FB
NR
R
ISEN LL
R
X
(18)
Where N is the active channel number, RISEN is
the sense resistor connected to the ISEN+ pin,
and RX is the resistance of the current sense,
either the DCR of the inductor or RSENSE
depending on the sensing method.
MP2930 Rev. 1.01
10/30/2013
RC
CC
COMP
FB
R FB
VDROOP
MP2930
IDROOP
VDIFF
Figure 12— Compensation Circuit for
MP2930 with Load-line Regulation
The feedback resistor, RFB, has already been
chosen as outlined in “Load-Line Regulation
Resistor”. Select a target bandwidth for the
compensated system, f0. The target bandwidth
must be large enough to assure adequate
transient performance, but smaller than 1/3 of
the per-channel switching frequency. The
values of the compensation components
depend on the relationships of f0 to the L-C pole
frequency and the ESR zero frequency.
The optional capacitor C2, (22pF to 150pF) is
sometimes needed to bypass noise away from
the PWM comparator (see Figure 12).
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17
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
Compensation without Load-Line
Regulation
The non load-line regulated converter is
accurately modeled as a voltage-mode
regulator with two poles at the L-C resonant
frequency and a zero at the ESR frequency. A
type-III controller, as shown in Figure 13,
provides the necessary compensation.
C2
RC
CC
COMP
FB
MP2930
C1
RFB
characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the
output capacitors supply all of the transient
current. The output voltage will initially deviate
by an amount approximated by the voltage drop
across the ESL. As the load current increases,
the voltage drop across the ESR increases
linearly until the load current reaches its final
value. The capacitors selected must have
sufficiently low ESL and ESR so that the total
output voltage deviation is less than the
allowable maximum. Neglecting the contribution
of inductor current and regulator response, the
output voltage initially deviates by an amount in
Equation (19):
IDROOP
ΔV ESL
R1
VDIFF
Figure 13—Compensation Circuit for
MP2930 without Load-line Regulation
The first step is to choose the desired
bandwidth, f0, of the compensated system.
Choose a frequency high enough to assure
adequate transient performance but not higher
than 1/3 of the switching frequency. The type-III
compensator has an extra high-frequency pole,
fHF. A good general rule is to choose fHF=10f0,
but it can be higher if desired. Choosing fHF to
be lower than 10f0 can cause problems with too
much phase shift below the system bandwidth.
di
ESRΔI
dt
(19)
The filter capacitor must have sufficiently low
ESL and ESR so that ΔV < ΔVMAX.
The ESR of the bulk capacitors also creates the
majority of the output voltage ripple. As the bulk
capacitors sink and source the inductor AC
ripple current, a voltage develops across the
bulk-capacitor ESR. Thus, once the output
capacitors are selected, the maximum
allowable ripple voltage, VP-P(MAX) determines
the lower limit on the inductance.
V - NV
V
OUT OUT
L ESR IN
f V V
s IN P - PMAX
(20)
Designing the Output Filter
The output inductors and the output capacitor
bank together to form a low-pass filter
responsible for smoothing the pulsating voltage
at the phase nodes. The output filter also must
provide the transient energy until the regulator
can respond.
Since the capacitors are supplying a decreasing
portion of the load current while the regulator
recovers from the transient, the capacitor
voltage becomes slightly depleted. The output
inductors must be capable of assuming the
entire load current before the output voltage
decreases more than ΔVMAX. This places an
upper limit on inductance.
In high-speed converters, the output capacitor
bank is usually the most costly (and often the
largest) part of the circuit. The critical load
parameters in choosing the output capacitors
are the maximum size of the load step, ΔI; the
load-current slew rate, di/dt; and the maximum
allowable output voltage deviation under
transient loading, ΔVMAX. Capacitors are
Selecting the Switching Frequency
There are a number of variables to consider
when choosing the switching frequency, as
there are considerable effects on the upperMOSFET loss calculation. The lower limit is
established by the requirement for fast transient
response and small output voltage ripple as
outlined in “Output Filter Design”. Choose the
MP2930 Rev. 1.01
10/30/2013
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18
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
lowest switching frequency that allows the
regulator to meet the transient-response
requirements.
PC Board Layout
For best performance of the MP2930, the
following guidelines should be strictly followed:
Selecting the Input Capacitor
The input capacitors are responsible for
sourcing the AC component of the input current
flowing into the upper MOSFETs. Their RMS
current capacity must be sufficient to handle the
AC component of the current drawn by the
upper MOSFETs which is related to duty cycle
and the number of active phases.
Within the allotted implementation area, place
the switching components first. Switching
component placement should take into account
power dissipation. Align the output inductors
and MOSFETs such that space between the
components is minimized while creating the
PHASE plane. If possible, duplicate the same
placement of these components for each phase.
Low capacitance, high-frequency ceramic
capacitors are needed in addition to the bulk
capacitors to suppress leading and falling edge
voltage spikes. Select low ESL ceramic
capacitors and place one as close as possible
to each upper MOSFET drain to minimize board
parasitic
impedances
and
maximize
suppression.
Next, place the input and output capacitors.
Position one high frequency ceramic input
capacitor next to each upper MOSFET drain.
Place the input capacitors as close to the upper
MOSFET drains as dictated by the component
size and dimensions. Locate the output
capacitors between the inductors and the load,
while keeping them in close proximity to the
microprocessor socket.
MP2930 Rev. 1.01
10/30/2013
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19
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
Table 1—VR10 ID Table (with 6.25mV
Extension)
Table 1—VR10 ID Table (with 6.25mV
Extension) (continued)
ID4
ID3
ID2
ID1
ID0
ID5
ID6 VOLTAGE
400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV
(V)
ID4
ID3
ID2
ID1 ID0
ID5
ID6 VOLTAGE
400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV
(V)
0
1
0
1
0
1
1
1.60000
1
0
1
0
0
0
0
1.35625
0
1
0
1
0
1
0
1.59375
1
0
1
0
0
1
1
1.35000
0
1
0
1
1
0
1
1.58750
1
0
1
0
0
1
0
1.34375
0
1
0
1
0
1
1.33750
0
1
0
1
1
0
0
1.58125
1
0
1
0
1
1
1
1
1.57500
1
0
1
0
1
0
0
1.33125
0
1
0
1
1
1
0
1.56875
1
0
1
0
1
1
1
1.32500
0
1
0
1
1
0
1.31875
0
1
1
0
0
0
1
1.56250
1
0
1
1
0
0
0
0
1.55625
1
0
1
1
0
0
1
1.31250
0
1
1
0
0
0
1.30625
0
1
1
0
0
1
1
1.55000
1
0
1
1
0
0
1
0
1.54375
1
0
1
1
0
1
1
1.30000
0
1
1
0
1
0
1
1.53750
1
0
1
1
0
1
0
1.29375
0
1
1
1
0
1
1.28750
0
1
1
0
1
0
0
1.53125
1
0
1
1
0
1
1
1
1.52500
1
0
1
1
1
0
0
1.28125
0
1
1
1
1
1
1.27500
0
1
1
0
1
1
0
1.51875
1
0
1
1
1
0
0
1
1.51250
1
0
1
1
1
1
0
1.26875
0
1
1
1
0
0
0
1.50625
1
1
0
0
0
0
1
1.26250
1
0
0
0
0
0
1.25625
0
1
1
1
0
1
1
1.50000
1
0
1
1
1
0
1
0
1.49375
1
1
0
0
0
1
1
1.25000
1
0
0
0
1
0
1.24375
0
1
1
1
1
0
1
1.4875
1
0
1
1
1
1
0
0
1.48125
1
1
0
0
1
0
1
1.23750
0
1
1
1
1
1
1
1.47500
1
1
0
0
1
0
0
1.23125
1
0
0
1
1
1
1.22500
0
1
1
1
1
1
0
1.46875
1
1
0
0
0
0
0
1
1.46250
1
1
0
0
1
1
0
1.21875
1
0
0
0
0
0
0
1.45625
1
1
0
1
0
0
1
1.21250
1
0
1
0
0
0
1.20625
1
0
0
0
0
1
1
1.45000
1
1
0
0
0
0
1
0
1.44375
1
1
0
1
0
1
1
1.20000
1
0
1
0
1
0
1.19375
1
0
0
0
1
0
1
1.43750
1
1
0
0
0
1
0
0
1.43125
1
1
0
1
1
0
1
1.18750
1
0
0
0
1
1
1
1.42500
1
1
0
1
1
0
0
1.18125
1
0
1
1
1
1
1.17500
1
0
0
0
1
1
0
1.41875
1
1
0
0
1
0
0
1
1.41250
1
1
0
1
1
1
0
1.16875
1
1
0
0
0
1
1.16250
1
0
0
1
0
0
0
1.40625
1
1
0
0
1
0
1
1
1.40000
1
1
1
0
0
0
0
1.15625
1
0
0
1
0
1
0
1.39375
1
1
1
0
0
1
1
1.15000
1
1
0
0
1
0
1.14375
1
0
0
1
1
0
1
1.38750
1
1
0
0
1
1
0
0
1.38125
1
1
1
0
1
0
1
1.13750
1
0
0
1
1
1
1
1.37500
1
1
1
0
1
0
0
1.13125
1
1
0
1
1
1
1.12500
1
1
0
1
1
0
1.11875
1
0
0
1
1
1
0
1.36875
1
1
0
1
0
0
0
1
1.36250
1
MP2930 Rev. 1.01
10/30/2013
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20
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
Table 1—VR10 ID Table (with 6.25mV
Extension) continued
ID4
ID3
ID2
ID1
400mV 200mV 100mV 50mV
1
1
1
1
ID4
ID3
ID2
ID1
ID0
ID5
ID6 VOLTAGE
400mV 200mV 100mV 50mV 25mV 12.5mV 6.25mV
(V)
0
0
1
1
1
1
0
0.89375
0
1
0
0
0
0
1
0.88750
1.11250
0
1
0
0
0
0
0
0.88125
1
0
0
0
1
1
0.87500
ID0
ID5
ID6 VOLTAGE
25mV 12.5mV 6.25mV
(V)
0
0
1
1
1
1
1
0
0
0
1.10625
0
1
1
1
1
0
1
1
1.10000
0
1
0
0
0
1
0
0.86875
1
0
0
1
0
1
0.86250
1
1
1
1
0
1
0
1.09375
0
1
1
1
1
1
0
1
OFF
0
1
0
0
1
0
0
0.85625
1
1
1
1
1
0
0
OFF
0
1
0
0
1
1
1
0.85000
1
0
0
1
1
0
0.84375
1
1
1
1
1
1
1
OFF
0
1
1
1
1
1
1
0
OFF
0
1
0
1
0
0
1
0.83750
0
1
0
1
0
0
0
0.83125
0
0
0
0
0
0
1
1.08750
0
0
0
0
0
0
0
1.08125
0
0
0
0
0
1
1
1.07500
0
0
0
0
0
1
0
1.06875
0
0
0
0
1
0
1
1.06250
0
0
0
0
1
0
0
1.05625
0
0
0
0
0
0
0
1
1
1
1.05000
0
0
0
0
0
0
1
1
0
1.04375
0
0
0
0
0
1
0
0
1
1.03750
0
0
0
0
1
0
0
0
1.03125
0
0
0
0
1
0
1
1
1.02500
0
0
0
1
0
1
0
1.01875
0
0
0
1
1
0
1
1.01250
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
0
0
0
1
0
0
0
Table 2—VR11 ID 8-BIT
ID7 ID6 ID5 ID4
ID3
ID2
ID1
ID0 VOLTAGE
0
0
0
0
0
0
0
0
0
0
1
OFF
0
0
0
0
1
0
1.60000
0
0
0
0
0
1
1
1.59375
0
0
0
0
1
0
0
1.58750
0
0
0
0
0
1
0
1
1.58125
0
0
0
0
0
1
1
0
1.57500
0
0
0
0
0
1
1
1
1.56875
1.00625
0
0
0
0
1
0
0
0
1.56250
1
1.00000
0
0
0
0
1
0
0
1
1.55625
1
0
0.99375
0
0
0
0
1
0
1
0
1.55000
0
0
1
0.9875
0
0
0
0
1
0
1
1
1.54375
0
0
0
0
0.98125
0
0
0
0
1
1
0
0
1.53750
1
0
0
1
1
0.97500
0
0
0
0
1
1
0
1
1.53125
0
1
0
0
1
0
0.96875
0
0
0
0
1
1
1
0
1.52500
0
0
1
0
1
0
1
0.9625
0
0
0
0
1
1
1
1
1.51875
0
0
1
0
1
0
0
0.95625
0
0
1
0
1
1
1
0.95000
0
0
0
1
0
0
0
0
1.51250
0
0
1
0
1
1
0
0.94375
0
0
0
1
0
0
0
1
1.50625
0
0
1
1
0
0
1
0.93750
0
0
0
1
0
0
1
0
1.50000
0
0
1
1
0
0
0
0.93125
0
0
0
1
0
0
1
1
1.49375
0
0
1
1
0
1
1
0.92500
0
0
0
1
0
1
0
0
1.48750
0
0
1
1
0
1
0
0.91875
0
0
0
1
0
1
0
1
1.48125
0
0
1
1
1
0
1
0.91250
0
0
0
1
0
1
1
0
1.47500
0
0
1
1
1
0
0
0.90625
0
0
1
1
1
1
1
0.90000
OFF
Table 1—VR10 ID Table (with 6.25mV
Extension) continued
MP2930 Rev. 1.01
10/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
21
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
Table 2—VR11 ID 8-BIT continued
ID5 ID4 ID3 ID2
ID7
ID6
ID2
ID1
0
0
0
1
0
1
1
1
1.46875
0
0
1
1
1
1
1
1
1.21875
0
0
0
1
1
0
0
0
1.46250
0
1
0
0
0
0
1
1
0
0
1
1.45625
0
1
0
0
0
0
0
0
1.21250
0
0
0
0
1
1.20625
0
0
0
1
1
0
1
0
1.45000
0
1
0
0
0
0
1
0
1.20000
0
0
0
1
1
0
1
1
1.44375
0
0
0
0
1
1
1
0
0
1.43750
0
1
0
0
0
0
1
1
1.19375
1
0
0
0
1
0
0
1.18750
0
0
0
1
1
1
0
1
1.43125
0
1
0
0
0
1
0
1
1.18125
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1.42500
0
1
0
0
0
1
1
0
1.17500
1.41875
0
0
1
0
0
0
0
0
1
0
0
0
1
1
1
1.16875
0
1.41250
0
1
0
0
1
0
0
0
1.16250
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1.40625
0
1
0
0
1
0
0
1
1.15625
1
0
1.40000
0
0
1
0
0
0
1
0
0
1
0
1
0
1.15000
0
1
1
1.39375
0
1
0
0
1
0
1
1
1.14375
0
0
1
0
0
1
0
0
1.38750
0
1
0
0
1
1
0
0
1.13750
0
0
1
0
0
1
0
0
1
0
1
1.38125
0
1
0
0
1
1
0
1
1.13125
0
0
1
1
0
1.37500
0
1
0
0
1
1
1
0
1.12500
0
0
1
0
0
1
1
1
1.36875
0
1
0
0
1
1
1
1
1.11875
0
0
0
1
0
1
0
0
0
1.36250
0
1
0
1
0
0
0
0
1.11250
0
1
0
1
0
0
1
1.35625
0
1
0
1
0
0
0
1
1.10625
0
0
1
0
1
0
1
0
1.35000
0
1
0
1
0
0
1
0
1.10000
0
0
1
0
1
0
1
1
1.34375
0
1
0
1
0
0
1
1
1.09375
0
0
1
0
1
1
0
0
1.33750
0
1
0
1
0
1
0
0
1.08750
0
0
1
0
1
1
0
1
1.33125
0
1
0
1
0
1
0
1
1.08125
0
0
1
0
1
1
1
0
1.32500
0
1
0
1
0
1
1
0
1.07500
0
0
1
0
1
1
1
1
1.31875
0
1
0
1
0
1
1
1
1.06875
0
0
1
1
0
0
0
0
1.31250
0
1
0
1
1
0
0
0
1.06250
0
0
1
1
0
0
0
1
1.30625
0
1
0
1
1
0
0
1
1.05625
0
0
1
1
0
0
1
0
1.30000
0
1
0
1
1
0
1
0
1.05000
0
0
1
1
0
0
1
1
1.29375
0
1
0
1
1
0
1
1
1.04375
0
0
1
1
0
1
0
0
1.28750
0
1
0
1
1
1
0
0
1.03750
0
0
1
1
0
1
0
1
1.28125
0
1
0
1
1
1
0
1
1.03125
0
0
1
1
0
1
1
0
1.27500
0
1
0
1
1
1
1
0
1.02500
0
0
1
1
0
1
1
1
1.26875
0
1
0
1
1
1
1
1
1.01875
0
0
1
1
1
0
0
0
1.26250
0
1
1
0
0
0
0
0
1.01250
0
0
1
1
1
0
0
1
1.25625
0
1
1
0
0
0
0
1
1.00625
0
0
1
1
1
0
1
0
1.25000
0
1
1
0
0
0
1
0
1.00000
0
0
1
1
1
0
1
1
1.24375
0
1
1
0
0
0
1
1
0.99375
0
0
1
1
1
1
0
0
1.23750
0
1
1
0
0
1
0
0
0.98750
0
0
1
1
1
1
0
1
1.23125
0
1
1
0
0
1
0
1
0.98125
0
0
1
1
1
1
1
0
1.22500
MP2930 Rev. 1.01
10/30/2013
ID1
ID0 VOLTAGE
Table 2—VR11 ID 8-BIT continued
ID7 ID6 ID5 ID4 ID3
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
ID0 VOLTAGE
22
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
Table 2—VR11 ID 8-BIT continued
ID3 ID2 ID1
ID7 ID6
ID5
ID4 ID3
ID2
ID1
ID0 VOLTAGE
1
0
0
0
1
1
1
0
0.72500
0.97500
1
0
0
0
1
1
1
1
0.71875
1
0.96875
1
0
0
1
0
0
0
0
0.71250
0
0.96250
1
0
0
1
0
0
0
1
0.70625
0
0
1
0
0
1
0
0.70000
ID7
ID6
ID5
ID4
ID0 VOLTAGE
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
1
1
0
1
0
0
1
0.95625
1
0
1
1
0
1
0
1
0
0.95000
1
0
0
1
0
0
1
1
0.69375
0
1
1
0
1
0
1
1
0.94375
1
0
0
1
0
1
0
0
0.68750
0
1
1
0
1
1
0
0
0.93750
1
0
0
1
0
1
0
1
0.68125
0
0
1
0
1
1
0
0.67500
0
1
1
0
1
1
0
1
0.93125
1
0
1
1
0
1
1
1
0
0.92500
1
0
0
1
0
1
1
1
0.66875
0
1
1
0
1
1
1
1
0.91875
1
0
0
1
1
0
0
0
0.66250
0
0
1
1
0
0
1
0.65625
0
1
1
1
0
0
0
0
0.91250
1
0
1
1
1
0
0
0
1
0.90625
1
0
0
1
1
0
1
0
0.65000
0
1
1
1
0
0
1
0
0.90000
1
0
0
1
1
0
1
1
0.64375
0
1
1
1
0
0
1
1
0.89375
1
0
0
1
1
1
0
0
0.63750
0
0
1
1
1
0
1
0.63125
0
1
1
1
0
1
0
0
0.88750
1
0
1
1
1
0
1
0
1
0.88125
1
0
0
1
1
1
1
0
0.62500
0
1
1
1
0
1
1
0
0.87500
1
0
0
1
1
1
1
1
0.61875
0
1
1
1
0
1
1
1
0.86875
1
0
1
0
0
0
0
0
0.61250
0
1
0
0
0
0
1
0.60625
0
1
1
1
1
0
0
0
0.86250
1
0
1
1
1
1
0
0
1
0.85625
1
0
1
0
0
0
1
0
0.60000
0
1
1
1
1
0
1
0
0.85000
1
0
1
0
0
0
1
1
0.59375
0
1
0
0
1
0
0
0.58750
0
1
1
1
1
0
1
1
0.84375
1
0
1
1
1
1
1
0
0
0.83750
1
0
1
0
0
1
0
1
0.58125
0
1
1
1
1
1
0
1
0.83125
1
0
1
0
0
1
1
0
0.57500
0
1
1
1
1
1
1
0
0.82500
1
0
1
0
0
1
1
1
0.56875
0
1
0
1
0
0
0
0.56250
0
1
1
1
1
1
1
1
0.81875
1
1
0
0
0
0
0
0
0
0.81250
1
0
1
0
1
0
0
1
0.55625
1
0
0
0
0
0
0
1
0.80625
1
0
1
0
1
0
1
0
0.55000
0
1
0
1
0
1
1
0.54375
1
0
0
0
0
0
1
0
0.80000
1
1
0
0
0
0
0
1
1
0.79375
1
0
1
0
1
1
0
0
0.53750
1
0
0
0
0
1
0
0
0.78750
1
0
1
0
1
1
0
1
0.53125
1
0
0
0
0
1
0
1
0.78125
1
0
1
0
1
1
1
0
0.52500
0
1
0
1
1
1
1
0.51875
1
0
0
0
0
1
1
0
0.77500
1
1
0
0
0
0
1
1
1
0.76875
1
0
1
1
0
0
0
0
0.51250
1
0
0
0
1
0
0
0
0.76250
1
0
1
1
0
0
0
1
0.50625
1
0
0
0
1
0
0
1
0.75625
1
0
1
1
0
0
1
0
0.50000
1
1
1
1
1
1
0
OFF
1
1
1
1
1
1
1
OFF
1
0
0
0
1
0
1
0
0.75000
1
1
0
0
0
1
0
1
1
0.74375
1
1
0
0
0
1
1
0
0
0.73750
1
0
0
0
1
1
0
1
0.73125
Table 2—VR11 ID 8-BIT continued
MP2930 Rev. 1.01
10/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
23
MP2930 - 4-PHASE PWM CONTROLLER WITH 8-BIT DAC CODE
PACKAGE INFORMATION
QFN40 (6mm x 6mm)
5.90
6.10
4.50
4.80
31
PIN 1 ID
MARKING
PIN 1 ID
SEE DETAIL A
40
30
1
0.50
BSC
5.90
6.10
PIN 1 ID
INDEX AREA
4.50
4.80
0.18
0.30
10
21
TOP VIEW
11
20
0.35
0.45
BOTTOM VIEW
PIN 1 ID OPTION A
0.30x45º TYP.
PIN 1 ID OPTION B
R0.25 TYP.
0.80
1.00
0.20 REF
0.00
0.05
DETAIL A
SIDE VIEW
5.90
NOTE:
4.70
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
4) DRAWING CONFORMS TO JEDEC MO-220, VARIATION VJJD-5.
5) DRAWING IS NOT TO SCALE.
0.70
0.90
0.50
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP2930 Rev. 1.01
10/30/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
24
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