MP38900/MP38900-B
High Efficiency, Fast Transient, 10A, 16V
Synchronous Step-down Converter
In a Tiny QFN20 (3x4mm) Package
END OF LIFE
DESCRIPTION
FEATURES
The MP38900/MP38900-B is a fully integrated,
high frequency synchronous rectified step-down
switch mode converter. It offers a very compact
solution to achieve 10A continuous output current
over a wide input supply range with excellent
load and line regulation. The
MP38900/
MP38900-B operates at high efficiency over a
wide output current load range.
The table below summarizes the variations
among the MP38900 and the MP38900-B.
MP38900
External
VCC
MP38900-B
Built-in VCC
OCP
Latch Off
OCP
Hiccup
Soft SHDN
Hi-Z SHDN
To futher optimize efficiency at light load, the VCC
supply of MP38900 is designed to be biased
externally.
Constant-On-Time (COT) control mode provides
fast transient response and eases loop
stabilization.
Full protection features include SCP, OCP, OVP,
UVP and thermal shutdown.
The MP38900/MP38900-B requires a minimum
number of readily available standard external
components and is available in a space-saving
QFN20 (3x4mm) package.
Wide 4.5V to 16V Operating Input Range
10A Output Current
Internal 27mΩ High-Side, 10mΩ Low-Side
Power MOSFETs
Proprietary Switching Loss Reduction
Technique
1% Reference Voltage
Programmable Soft Start Time
Soft Shutdown (MP38900,)
High-Z Shutdown (MP38900-B)
Programmable Switching Frequency
SCP, OCP, OVP, UVP Protection and
Thermal Shutdown
Output Adjustable from 0.8V to 13V
Available in a QFN20 (3x4mm) Package
APPLICATIONS
Notebook Systems and I/O Power
Networking Systems
Optical Communication Systems
Distributed Power POL Systems
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Quality Assurance. “MPS” and “The
Future of Analog IC Technology” are Registered Trademarks of Monolithic
Power Systems, Inc.
MP38900/MP38900-B Rev. 1.1
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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
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TYPICAL APPLICATION
MP38900/MP38900-B Rev. 1.1
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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
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ORDERING INFORMATION
Part Number
Package
Top Marking
MP38900DL*
MP38900DL-B***
QFN20 (3x4mm)
QFN20 (3x4mm)
38900
38900B
* For Tape & Reel, add suffix –Z (e.g. MP38900DL–Z)
For RoHS compliant packaging, add suffix –LF (e.g. MP38900DL–LF–Z)
***For Tape & Reel, add suffix –Z (e.g. MP38900DL-B–Z)
For RoHS compliant packaging, add suffix –LF (e.g. MP38900DL-B–LF–Z)
PACKAGE REFERENCE
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance (4)
Supply Voltage VIN ....................................... 18V
Supply Voltage VCC ........................................ 6V
VSW ........................................ -0.3V to VIN + 0.3V
VBST ...................................................... VSW + 6V
IVIN (RMS) ........................................................ 3.5A
VPGOOD ................................... -0.3V to VCC +0.6V
All Other Pins ..................................-0.3V to +6V
Continuous Power Dissipation (TA = +25°C) (2)
………………………………………………….2.6W
Junction Temperature ...............................150C
Lead Temperature ....................................260C
Storage Temperature ............... -65C to +150C
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
θJA
θJC
QFN20 (3x4mm) ...................... 48 ...... 10 ... C/W
Recommended Operating Conditions (3)
Supply Voltage VIN ........................... 4.5V to 16V
Supply Voltage VCC ........................................ 5V
Output Voltage VOUT ......................... 0.8V to 13V
Operating Junction Temp. (TJ). -40°C to +125°C
MP38900/MP38900-B Rev. 1.1
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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
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ELECTRICAL CHARACTERISTICS
VIN = 12V, VCC=5V, TA = +25C, unless otherwise noted.
Parameters
Input Supply Current
(Shutdown)
Input Supply Current
(Quiescent)
Input Supply Current
(Quiescent)
VCC Supply Current
(Quiescent)
HS Switch On Resistance (5)
LS Switch On Resistance (5)
Switch Leakage
Symbol
Condition
IIN
VEN = 0V
IIN
IIN
Ivcc
VEN = 2V, VFB = 0.95V,
MP38900-B (6)
VEN = 2V, VFB = 0.95V
MP38900 (6)
VEN = 2V, VFB = 1V
MP38900
HSRDS-ON
LSRDS-ON
SWLKG
Current Limit
ILIMIT
One-Shot On Time
TON
Minimum Off Time(5)
Fold-back Off Time(5)
OCP hold-off time(5)
Feedback Voltage
Feedback Current
Soft Start Charging Current
Soft Stop Discharging Current
Power Good Rising Threshold
Power Good Falling Threshold
Power Good Rising Delay
Power Good Rising Delay
EN Rising Threshold
EN Threshold Hysteresis
EN Input Current
VCC Under-Voltage Lockout
Threshold Rising
VCC Under-Voltage Lockout
Threshold Hysteresis
VIN Under-Voltage Lockout
Threshold Rising
VIN Under-Voltage Lockout
Threshold Hysteresis
VCC Regulator Output Voltage
VCC Regulator Load Regulation
VOUT Over-Voltage Protection
Threshold
Min
TOFF
TFB
TOC
VFB
IFB
+ISS
-ISS
PGOODVth-Hi
PGOODVth-Lo
TPGOOD
TPGOOD
ENVth-Hi
ENVth-Hys
IEN
VEN = 0V, VSW = 0V or
12V
ILIM=1 (HIGH)
ILIM=1 (HIGH)
807
VFB = 815mV
VSS=0V
VSS=0.815V
Tss = 2ms, MP38900
MP38900-B
1.05
VEN = 2V
MP38900
VCCUVHYS
MP38900
VINUVVth
MP38900-B
VINUVHYS
MP38900-B
VCC
VOVP
MP38900-B
MP38900-B, ICC=5mA
Max
Units
0
1
μA
420
μA
40
μA
350
μA
27
10
mΩ
mΩ
0
R7=250kΩ,
VOUT=1.05V
VCCUVVth
Typ
3.8
1
16.5
A
300
ns
100
7.5
50
815
10
8.5
8.5
0.9
0.85
1.5
1.5
1.35
420
1.5
ns
μs
μs
mV
nA
μA
μA
VFB
VFB
ms
ms
V
mV
μA
4.0
823
50
1.60
4.2
880
3.8
μA
4.0
mV
4.2
880
5
MP38900/MP38900-B Rev. 1.1
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V
mV
5
1.25
V
V
%
VFB
4
MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
END OF LIFE
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, VCC=5V, TA = +25C, unless otherwise noted.
Parameters
VOUT Under-Voltage Detection
Threshold
Thermal Shutdown
Thermal Shutdown Hysteresis
Symbol
Condition
Min
Typ
Max
Units
VUVP
0.7
VFB
TSD
150
25
°C
°C
TSD-HYS
Notes:
5) Guaranteed by design.
6) If the test condition is marked with MP38900 or MP38900-B, the characteristic applies to MP38900 or MP38900-B respectively.
MP38900/MP38900-B Rev. 1.1
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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
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PIN FUNCTIONS
Pin #
Name
Description
1
AGND
2
FREQ
3
FB
4
SS
5
EN
6
PGOOD
7
BST
8, 19
IN
9, 10, 17, 18
SW
11-16
PGND
20
VCC
Analog Ground.
Frequency Set during CCM operation. The ON period is determined by the input
voltage and the frequency-set resistor connected to FREQ pin. Connect a resistor
to IN for line feed-forward. Decouple with a 1nF capacitor.
Feedback. An external resistor divider from the output to GND, tapped to the FB
pin, sets the output voltage.
Soft Start. Connect an external SS capacitor to program the soft start time for the
switch mode regulator. When the EN pin becomes high, an internal current source
(8.5μA) charges up the SS capacitor and the SS voltage slowly ramps up from 0 to
VFB smoothly. For MP38900, when the EN pin becomes low, an internal current
source (8.5μA) discharges the SS capacitor and the SS voltage slowly ramps
down. For MP38900-B, SS will pull low as soon as EN goes low.
EN=1 to enable the MP38900/MP38900-B. For automatic start-up, connect EN pin
to IN with a 100kΩ resistor. It includes an internal 1MΩ pull-down resistor.
Power Good Output. The output of this pin is an open drain and is high if the
output voltage is higher than 90% of the nominal voltage. There is delay from FB ≥
90% to PGOOD high, which is 50% of SS time plus 0.5ms. For MP38900-B, the
delay is fixed as 1.5ms.
Bootstrap. A capacitor connected between SW and BS pins is required to form a
floating supply across the high-side switch driver.
Supply Voltage. The MP38900/MP38900-B operates from a +4.5V to +16V input
rail. C1 is needed to decouple the input rail. Use wide PCB traces and multiple vias
to make the connection.
Switch Output. Use wide PCB traces and multiple vias to make the connection.
System Ground. This pin is the reference ground of the regulated output voltage.
For this reason care must be taken in PCB layout.
MP38900: External 5V Supply. This 5V supply has to be applied in order to bias
the device. Decouple with a 1µF capacitor as close to this pin as possible.
MP38900-B: Internal 5V supply. Decouple with a 1μF capacitor as close to this pin
as possible.
MP38900/MP38900-B Rev. 1.1
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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
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TYPICAL PERFORMANCE CHARACTERISTICS
VIN=12V, VOUT =1.2V, L=1.0µH, TA=+25°C, unless otherwise noted.
MP38900/MP38900-B Rev. 1.1
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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=12V, VOUT =1.2V, L=1.0µH, TA=+25°C, unless otherwise noted.
MP38900/MP38900-B Rev. 1.1
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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
END OF LIFE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=12V, VOUT =1.2V, L=1.0µH, TA=+25°C, unless otherwise noted.
MP38900/MP38900-B Rev. 1.1
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6/25/2012
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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
END OF LIFE
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=12V, VOUT =1.2V, L=1.0µH, TA=+25°C, unless otherwise noted.
MP38900/MP38900-B Rev. 1.1
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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
END OF LIFE
BLOCK DIAGRAM
Figure 2: Functional Block Diagram
MP38900/MP38900-B Rev. 1.1
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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
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OPERATION
PWM Operation
The MP38900/MP38900-B is a fully integrated
synchronous rectified step-down switch mode
converter. Constant-on-time (COT) control is
employed to provide fast transient response and
easy loop stabilization. At the beginning of each
cycle, the high-side MOSFET (HS-FET) is turned
on when the feedback voltage (VFB) is below the
reference voltage (VREF) which indicates
insufficient output voltage. The ON period is
determined by the input voltage and the
frequency-set resistor as follows:
t on (ns)
12 R7k
tDELAY1 (ns)
VIN (V) 0.45
(1)
Where R7 is the resistor to set switching
frequency, tDELAY1 is the 20ns delay of a
comparator in the tON module.
After the ON period elapses, the HS-FET is
turned off, or becomes OFF state. It is turned ON
again when VFB drops below VREF. By repeating
operation this way, the converter regulates the
output voltage. The integrated low-side MOSFET
(LS-FET) is turned on when the HS-FET is in its
OFF state to minimize the conduction loss. There
will be a dead short between input and GND if
both HS-FET and LS-FET are turned on at the
same time. It’s called shoot-through. In order to
avoid shoot-through, a dead-time (DT) is
internally generated between HS-FET off and LSFET on, or LS-FET off and HS-FET on.
As Figure 3 shows, when the output current is
high, the HS-FET and LS-FET repeat on/off as
described above. In this operation, the inductor
current will never go to zero. It’s called
continuous-conduction-mode (CCM) operation. In
CCM operation, the switching frequency (fSW) is
fairly constant.
Light-Load Operation
When the load current decreases, The
MP38900/MP38900-B reduces the switching
frequency automatically to maintain high
efficiency. The light load operation is shown in
Figure 4. The VFB does not reach VREF when the
inductor current is approaching zero. As the
output current reduces from heavy-load
condition, the inductor current also decreases,
and eventually comes close to zero. The LS-FET
driver turns into tri-state (high Z) whenever the
inductor current reaches zero level. A current
modulator takes over the control of LS-FET and
limits the inductor current to less than 600μA.
Hence, the output capacitors discharge slowly to
GND through LS-FET as well as R1 and R2. As a
result, the efficiency at light load condition is
greatly improved. At light load condition, the HSFET is not turned ON as frequently as at heavy
load condition. This is called skip mode.
Heavy-Load Operation
Figure 4: Light Load Operation
As the output current increases from the light
load condition, the time period within which the
current modulator regulates becomes shorter.
The HS-FET is turned on more frequently. Hence,
the
switching
frequency
increases
correspondingly. The output current reaches the
critical level when the current modulator time is
zero. The critical level of the output current is
determined as follows:
Figure 3: Heavy Load Operation
MP38900/MP38900-B Rev. 1.1
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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
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IOUT
(VIN VOUT) VOUT
2 L FSW VIN
(2)
the VFB ripple dominates in noise immunity. The
magnitude of the VFB ripple doesn’t affect the
noise immunity directly.
It turns into PWM mode once the output current
exceeds the critical level. After that, the switching
frequency stays fairly constant over the output
current range.
Switching Frequency
Constant-on-time (COT) control is used in the
MP38900/MP38900-B and there is no dedicated
oscillator in the IC. The input voltage is feedforwarded to the on-time one-shot timer through
the resistor R7. The duty ratio is kept as VOUT/VIN.
Hence, the switching frequency is fairly constant
over the input voltage range. The switching
frequency can be set as follows:
106
(3)
f (kHz )
SW
Figure 5: Jitter in PWM Mode
12 R7(k) VIN (V)
t DELAY2 (ns)
VIN (V) 0.45 VOUT (V)
Where tDELAY2 is the comparator delay. It’s about
40ns.
Figure 6: Jitter in Skip Mode
Ramp with Large ESR Cap
In the case of POSCAP or other types of
capacitor with larger ESR is applied as output
capacitor. The ESR ripple dominates the output
ripple, and the slope on the FB is quite ESR
related. Figure 7 shows an equivalent circuit in
PWM mode with the HS-FET off and without an
external ramp circuit. Turn to application
information section for design steps with large
ESR caps.
SW
L
MP38900/MP38900-B is optimized to operate at
high switching frequency with high efficiency.
High switching frequency makes it possible to
utilize small sized LC filter components to save
system PCB space.
Jitter and FB Ramp Slope
Figure 5 and Figure 6 show jitter occurring in
both PWM mode and skip mode. When there is
noise in the VFB downward slope, the ON time of
the HS-FET driver deviates from its intended
location and produces jitter. It is necessary to
understand that there is a relationship between a
system’s stability and the steepness of the VFB
ripple’s downward slope. The slope steepness of
FB
Vo
R1
R2
ESR
POSCAP
Figure 7: Simplified Circuit in PWM Mode
without External Ramp Compensation
To realize the stability when no external ramp is
used, usually the ESR value should be chosen
as follow:
MP38900/MP38900-B Rev. 1.1
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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
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RESR
t SW
t
ON
0.7 2
COUT
(4)
tSW is the switching period.
When using a large-ESR capacitor on the output,
add a ceramic capacitor with a value of 10uF or
less to in parallel to minimize the effect of ESL.
Ramp with Small ESR Cap
When the output capacitors are ceramic ones,
the ESR ripple is not high enough to stabilize the
system, and external ramp compensation is
needed. Skip to application information section
for design steps with small ESR caps.
L
SW
Vout
As can be seen from equation 8, if there is
instability in PWM mode, we can reduce either
R4 or C4. If C4 can not be reduced further due to
limitation from equation 5, then we can only
reduce R4. For a stable PWM operation, the
Vslope1 should be design follow equation 9.
t SW
t
+ ON -RESRCOUT
Io 10-3
(9)
-Vslope1 0.7 π 2
VOUT +
2 L COUT
t SW -t on
Where Io is the load current.
In skip mode, the downward slope of the VFB
ripple is the same whether the external ramp is
used or not. Figure 9 shows the simplified circuit
of the skip mode when both the HS-FET and LSFET are off.
Vout
C4
R4
R1
IR4
IC4
R9
IFB
FB
R1
ESR
Ceramic
FB
Ro
R2
R2
Cout
.
Figure 8: Simplified Circuit in PWM Mode with
External Ramp Compensation
Figure 8 shows a simplified external ramp
compensation (R4 and C4) for PWM mode, with
HS-FET off. Chose R1, R2, R9 and C4 of the
external ramp to meet the following condition:
1
2 FSW
1 R R2
1
R9
C4 5 R1 R 2
(5)
(6)
And the Vramp on the VFB can then be estimated
as:
VRAMP
VIN VOUT
R1 //R2
t ON
R4 C4
R1 //R2 R9
The downward slope of the VFB ripple in skip
mode can be determined as follow:
VSLOPE2
VREF
(R1 R2 // Ro) COUT
(10)
Where Ro is the equivalent load resistor.
Where:
IR4 IC4 IFB IC4
Figure 9: Simplified Circuit in skip Mode
As described in Figure 6, VSLOPE2 in the skip
mode is lower than that is in the PWM mode, so
it is reasonable that the jitter in the skip mode is
larger. If one wants a system with less jitter
during ultra light load condition, the values of the
VFB resistors should not be too big, however, that
will decrease the light load efficiency.
(7)
The downward slope of the VFB ripple then
follows
VSLOPE1
VOUT
VRAMP
t off
R 4 C4
(8)
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Bootstrap Charging
The floating power MOSFET driver is powered by
an external VCC through D2 as shown in Figure 2.
This floating driver has its own UVLO protection.
This UVLO’s rising threshold is 2.2V with a
hysteresis of 150mV. The recommended BST
cap C4 is 1μF.
The PGOOD delay time is determined as follows:
Soft Start/Stop
The MP38900 employ soft start/stop (SS)
mechanism to ensure smooth output during
power-up and power shutdown. When the EN pin
becomes high, an internal current source (8.5μA)
charges up the SS CAP. The SS CAP voltage
takes over the VREF voltage to the PWM
comparator. The output voltage smoothly ramps
up with the SS voltage. Once the SS voltage
reaches the same level as the REF voltage, it
keeps ramping up while REF takes over the
PWM comparator. At this point, the soft start
finishes and it enters into steady state operation.
When the FB voltage drops to 85% of the REF
voltage, the PGOOD pin will be pulled low.
When the EN pin becomes low, the SS CAP
voltage is discharged through an 8.5μA internal
current source. Once the SS voltage reaches
REF voltage, it takes over the PWM comparator.
The output voltage will decrease smoothly with
SS voltage until zero level. The SS CAP value
can be determined as follows:
CSS (nF)
t SS (ms) ISS (A)
VREF (V)
(11)
If the output capacitors have large capacitance
value, it’s not recommended to set the SS time
too small. A minimal value of 4.7nF should be
used if the output capacitance value is larger
than 330μF.
MP38900-B has the same soft start mechanism,
however, the soft shut-down feature is disabled
to support output prebias applications.
Power Good (PGOOD)
The
MP38900/MP38900-B has power-good
(PGOOD) output. The PGOOD pin is the open
drain of a MOSFET. It should be connected to
VCC or other voltage source through a resistor
(e.g. 100k). After the input voltage is applied, the
MOSFET is turned on, so that the PGOOD pin is
pulled to GND before SS ready. After FB voltage
reaches 90% of REF voltage, the PGOOD pin is
pulled high after a delay.
MP38900:
tPGOOD (ms) 0.5 t SS (ms) 0.5
MP38900-B:
t PGOOD (ms) 1.5ms
(12)
Over-Current Protection (OCP) and ShortCircuit Protection (SCP)
The MP38900/MP38900-B has cycle-by-cycle
over-current limit control. The inductor current is
monitored during the ON state. Once it detects
that the inductor current is higher than the current
limit, the HS-FET is turned off. At the same time,
the OCP timer is started. The OCP timer is set as
40μs. If in the following 40μs, the current limit is
hit for every cycle, then it’ll trigger OCP.
When the current limit is hit and the FB voltage is
lower than 50% of the REF voltage, the device
considers this as a dead short on the output and
triggers OCP immediately. This is short circuit
protection (SCP).
Under OCP/SCP condition, MP38900 will latch
off. The converter needs power cycle to restart.
MP38900-B will enter hiccup mode, and restart
by itself once the OCP/SCP condition is removed.
Over/Under-voltage Protection (OVP/UVP)
The MP38900/MP38900-B monitors the output
voltage through a resistor divider feedback (FB)
voltage to detect overvoltage and undervoltage
on the output. When the FB voltage is higher
than 125% of the REF voltage, it’ll trigger OVP.
Once it triggers OVP, the LS-FET is always on
while the HS-FET is always off. It needs power
cycle to power up again. When the FB voltage is
below 70% of the REF voltage (0.815V), UVP will
be triggered. Usually, UVP accompanies a hit in
current limit and this results in SCP.
UVLO protection
The MP38900/MP38900-B has under-voltage
lock-out protection (UVLO). When VCC is higher
than the UVLO rising threshold voltage, the
MP38900/MP38900-B will be powered up. It
shuts off when VCC is lower than the UVLO falling
threshold voltage. This is non-latch protection.
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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
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Thermal Shutdown
Thermal shutdown is employed in the MP38900/
MP38900-B. The junction temperature of the IC
is internally monitored. If the junction temperature
exceeds the threshold value (typically 150ºC), the
converter shuts off. This is non-latch protection.
There is about 25ºC hysteresis. Once the
junction temperature drops to around 125ºC, it
initiates a soft start.
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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
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APPLICATION INFORMATION
Setting the Output Voltage-Large ESR Caps
For applications that electrolytic capacitor or POS
capacitor with a controlled output of ESR is set
as output capacitors. The output voltage is set by
feedback resistors R1 and R2. As Figure 10
shows.
SW
Vout
L
R1=
ESR
R1
FB
POSCAP
R2
Figure10: Simplified Circuit of POS Capacitor
First, choose a value for R2. R2 should be
chosen reasonably, a small R2 will lead to
considerable quiescent current loss while too
large R2 makes the FB noise sensitive. It is
recommended to choose a value within 5kΩ50kΩ for R2, using a comparatively larger R2
when Vout is low, etc.,1.05V, and a smaller R2
when Vout is high. Then R1 is determined as
follow with the output ripple considered:
1
VOUT VOUT VREF
2
(13)
R1
R2
VREF
VOUT is the output ripple determined by equation
21.
Setting the Output Voltage-Small ESR Caps
SW
L
FB
R4
Vout
C4
C4.The output voltage is influenced by ramp
voltage VRAMP besides R divider as shown in
Figure 11. The VRAMP can be calculated as shown
in equation 7. R2 should be chosen reasonably,
a small R2 will lead to considerable quiescent
current loss while too large R2 makes the FB
noise sensitive. It is recommended to choose a
value within 5kΩ-50kΩ for R2, using a
comparatively larger R2 when Vo is low,
etc.,1.05V, and a smaller R2 when Vo is high.
And the value of R1 then is determined as follow:
R1
R9
Ceramic
R2
Figure11: Simplified Circuit of Ceramic
Capacitor
When low ESR ceramic capacitor is used in the
output, an external voltage ramp should be
added to FB through resistor R4 and capacitor
R2
VFB(AVG)
R2
(VOUT -VFB(AVG) ) R4 +R9
(14)
The VFB(AVG) is the average value on the FB,
VFB(AVG) varies with the Vin, Vo, and load
condition, etc., its value on the skip mode would
be lower than that of the PWM mode, which
means the load regulation is strictly related to the
VFB(AVG). Also the line regulation is related to the
VFB(AVG). If one wants to gets a better load or line
regulation, a lower Vramp is suggested, as long
as the criterion shown in equation 8 can be met.
For PWM operation, VFB(AVG) value can be
deduced from the equation below.
R1 //R2
1
VFB(AVG) VREF VRAMP
2
R1 //R2 R9
(15)
Usually, R9 is set to 0Ω, and it can also be set
following equation 16 for a better noise immunity.
It should also set to be 5 timers smaller than
R1//R2 to minimize its influence on Vramp.
R9
1
2 C4 2FSW
(16)
Using equation 14 to calculate the R1 can be
complicated. To simplify the calculation, a DCblocking capacitor Cdc can be added to filter the
DC influence from R4 and R9. Figure 12 shows
a simplified circuit with external ramp
compensation and a DC-blocking capacitor. With
this capacitor, R1 can easily be obtained by
using the simplified equation for PWM mode
operation:
1
(VOUT VREF VRAMP )
2
R1
R2
1
VREF VRAMP
2
(17)
Cdc is suggested to be at least 10 times larger
than C4 for better DC blocking performance, and
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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
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should also not larger than 0.47uF considering
start up performance. In case one wants to use
larger Cdc for a better FB noise immunity,
combined with reduced R1 and R2 to limit the
Cdc in a reasonable value without affecting the
system start up. Be noted that even when the
Cdc is applied, the load and line regulation are
still Vramp related.
FB
R4
Vout
Cdc
IOUT
V
V
OUT (1 OUT )
FSW CIN VIN
VIN
(20)
The worst-case condition occurs at VIN = 2VOUT,
where:
R1
C4
The input voltage ripple can be estimated as
follows:
VIN
SW
L
The input capacitance value determines the input
voltage ripple of the converter. If there is input
voltage ripple requirement in the system design,
choose the input capacitor that meets the
specification.
VIN
Ceramic
IOUT
1
4 FSW CIN
(21)
R2
Figure12: Simplified Circuit of Ceramic
Capacitor with DC blocking capacitor
Input Capacitor
The input current to the step-down converter is
discontinuous. Therefore, a capacitor is required
to supply the AC current to the step-down
converter while maintaining the DC input voltage.
Ceramic capacitors are recommended for best
performance. In the layout, it’s recommended to
put the input capacitors as close to the IN pin as
possible.
The capacitance varies significantly over
temperature. Capacitors with X5R and X7R
ceramic dielectrics are recommended because
they are fairly stable over temperature.
The capacitors must also have a ripple current
rating greater than the maximum input ripple
current of the converter. The input ripple current
can be estimated as follows:
ICIN IOUT
VOUT
V
(1 OUT )
VIN
VIN
(18)
The worst-case condition occurs at:
ICIN
IOUT
2
(19)
For simplification, choose the input capacitor
whose RMS current rating is greater than half of
the maximum load current.
Output Capacitor
The output capacitor is required to maintain the
DC output voltage. Ceramic or POSCAP
capacitors are recommended. The output voltage
ripple can be estimated as:
VOUT
VOUT
V
1
(1 OUT ) (RESR
) (22)
FSW L
VIN
8 FSW COUT
Where RESR is the equivalent series resistance
(ESR) of the output capacitor.
In the case of ceramic capacitors, the impedance
at the switching frequency is dominated by the
capacitance. The output voltage ripple is mainly
caused by the capacitance. For simplification, the
output voltage ripple can be estimated as:
VOUT
VOUT
V
(1 OUT )
2
VIN
8 FSW L COUT
(23)
The output voltage ripple caused by ESR is very
small. Therefore, an external ramp is needed to
stabilize the system. The external ramp can be
generated through resistor R4 and capacitor C4
using the following equation 5, 8 and 9.
In the case of POSCAP capacitors, the ESR
dominates the impedance at the switching
frequency. The ramp voltage generated from the
ESR is high enough to stabilize the system.
Therefore, an external ramp is not needed. A
minimum ESR value of 12mΩ is required to
ensure stable operation of the converter. For
simplification, the output ripple can be
approximated as:
VOUT
VOUT
V
(1 OUT ) RESR
FSW L
VIN
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(24)
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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
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Inductor
The inductor is required to supply constant
current to the output load while being driven by
the switching input voltage. A larger value
inductor will result in less ripple current that will
result in lower output ripple voltage. However, a
larger value inductor will have a larger physical
size, higher series resistance, and/or lower
saturation current. A good rule for determining
the inductor value is to allow the peak-to-peak
ripple current in the inductor to be approximately
30~40% of the maximum switch current limit.
Also, make sure that the peak inductor current is
below the maximum switch current limit. The
inductance value can be calculated as:
L
VOUT
V
(1 OUT )
FSW IL
VIN
(25)
Where ΔIL is the peak-to-peak inductor ripple
current.
Choose an inductor that will not saturate under
the maximum inductor peak current. The peak
inductor current can be calculated as:
ILP IOUT
VOUT
V
(1 OUT )
2FSW L
VIN
(26)
The inductors listed in Table 1 are highly
recommended for the high efficiency they can
provide.
Table 1: Inductor Selection Guide
Part Number
Manufacturer
Inductance
(µH)
DCR
(mΩ)
Current
Rating (A)
Dimensions
L x W x H (mm3)
Switching
Frequency
(kHz)
PCMC-135T-R68MF
Cyntec
0.68
1.7
34
13.5 x 12.6 x 4.8
600
FDA1254-1R0M
TOKO
1
2
25.2
13.5 x 12.6 x 5.4
300~600
FDA1254-1R2M
TOKO
1.2
2.05
20.2
13.5 x 12.6 x 5.4
300~600
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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
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Typical Design Parameter Tables
The following tables include recommended
component values for typical output voltages
(1.05V, 1.2V, 1.8V, 2.5V, 3.3V) and switching
frequencies (300kHz, and 600kHz). Refer to
Tables 2-3 for design cases without external
ramp compensation and Tables 4-5 for design
cases with external ramp compensation.
External ramp is not needed when high-ESR
capacitors, such as electrolytic or POSCAPs are
used. External ramp is needed when low-ESR
capacitors, such as ceramic capacitors are used.
For cases not listed in this datasheet, a calculator
in excel spreadsheet can also be requested
through a local sales representative to assist with
the calculation.
Table 2: 300kHz, 12VIN, w/o External Ramp,
COUT=220μF, 15mΩ
VOUT
(V)
1.05
1.2
1.8
2.5
3.3
L
(μH)
1
1
2.0
2.0
2.0
R1
(kΩ)
5.49
9.1
12
20.5
30.1
R2
(kΩ)
20
20
10
10
10
R7
(kΩ)
324
357
475
680
866
Table 3: 600kHz, 12VIN, w/o External Ramp,
COUT =220μF, 15mΩ
VOUT
(V)
1.05
1.2
1.8
2.5
3.3
L
(μH)
0.68
0.68
1.2
1.2
1.2
R1
(kΩ)
5.6
9.1
12.1
21
30.9
R2
(kΩ)
20
20
10
10
10
R7
(kΩ)
147
165
240
330
442
Table 4: 300kHz, 12VIN, with External Ramp
VOUT
(V)
1.05
1.2
1.8
2.5
3.3
L
(μH)
1
1
2.0
2.0
2.0
R1
(kΩ)
5.11
8.87
12
20.5
30.9
R2
(kΩ)
20
20
10
10
10
R4
(kΩ)
300
300
590
590
590
C4
(pF)
220
220
220
220
220
R7
(kΩ)
324
357
475
680
866
Table 5: 600kHz, 12VIN, with External Ramp
VOUT
(V)
1.05
1.2
1.8
2.5
3.3
L
(μH)
0.68
0.68
1.2
1.2
1.2
R1
(kΩ)
5.6
9.1
12.1
21.5
33
R2
(kΩ)
20
20
10
10
10
R4
(kΩ)
205
205
300
300
300
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C4
(pF)
180
180
180
180
180
R7
(kΩ)
154
169
240
330
453
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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
END OF LIFE
TYPICAL APPLICATION
Figure 13 : Typical Application Circuit with Low ESR Ceramic Capacitor
Figure 14 : Typical Application Circuit with No External Ramp
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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
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LAYOUT RECOMMENDATION
1. The high current paths (GND, IN, and SW)
should be placed very close to the device
with short, direct and wide traces.
2. Put the input capacitors as close to the IN
and GND pins as possible.(
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