MP3924
Quad-Port, IEEE 802.3af/at
PSE Controller for Power over Ethernet
DESCRIPTION
FEATURES
The MP3924 is a quad-port power source
equipment (PSE) power controller for IEEE
802.3af/at compliant power over Ethernet (PoE)
applications.
The device has all the functions of IEEE
802.3af/at, including detection, single-event and
two-event classification, current limiting, and
disconnected load detection. All of the functions
can be configured to work in automatic
operation mode or software program mode via
the I2C.
The MP3924 features a 9-bit analog-to-digital
converter (ADC) to monitor the current and
voltage, a special I2C interface for isolated
controller communication, adjustable current
limits, and configurable system functions.
These features provide flexibility for PoE
applications.
The MP3924 is available
(5mmx5mm) package.
in
a
QFN-32
IEEE802.3af/at Compliant
Quad-Port and 4-Bit Configurable I2C
Address
0.25Ω Current-Sense Resistor
Automatic Mode and I2C Command Control
Mode
Automatic Input Over-Power Shutdown
Internal VCC Power Supply
Three-Wire I2C Interface for Isolated
Applications
Two INT Pins for Interrupt Priority Selection
Disconnected DC Load Detection
Instantaneous Current/Voltage Readout
Thermal Protection
Available in a QFN-32 (5mmx5mm)
Package
APPLICATIONS
PSE Switches/Routers
PSE Midspan Power Injectors
Surveillance NVR and DVRs
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are
trademarks of Monolithic Power Systems, Inc. or its subsidiaries.
TYPICAL APPLICATION
C2
VIN = 54V
VIN
C1
D1
Start-Up for Class 4 PD
Output
Port x4
OUTn
VCC
C3
EN
GATEn
AUTO
MID
MP3924
PMAX
R2
A3
A2
A1
A0
CLS5
MP3924 Rev. 1.0
7/16/2021
Q1
SENSEn
R1
CH1: VOUTx VVIN
20V/div.
SGNDx
SCL
SDAO
SDAI
INT1
INT2
DGND PGND
Note: Only One Port
is Shown Here
100ms/div.
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© 2021 MPS. All Rights Reserved.
1
MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
ORDERING INFORMATION
Part Number
MP3924GU*
EVKT-MP3924
Package
QFN-32 (5mmx5mm)
Evaluation kit
Top Marking
See Below
-
MSL Rating
2
* For Tape & Reel, add suffix -Z (e.g. MP3924GU-Z).
TOP MARKING
MPS: MPS prefix
YY: Year code
WW: Week code
MP3924: Part number
LLLLLLL: Lot number
EVALUATION KIT EVKT-MP3924
EVKT-MP3924 kit contents (items listed below can be ordered separately, and the GUI installation file and
supplemental documents can be downloaded from the MPS website):
#
Part Number
Item
Quantity
1
EV3924-U-00A
2
EVKT-USBI2C-02
3
MP3924GU
MP3924 evaluation board
Includes one USB to I2C communication interface device, one USB
cable, and one ribbon cable
MP3924 controller IC
1
1
2
Order directly from MonolithicPower.com or our distributors.
Input Power Supply
Input
USB Cable
USB to PMBus
Communication
Interface
(EVKT-USBI2C-02)
Ribbon Cable
Evaluation Board
Output
Load
Figure 1: EVKT-MP3924 Evaluation Kit Set-Up
MP3924 Rev. 1.0
7/16/2021
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© 2021 MPS. All Rights Reserved.
2
MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
PACKAGE REFERENCE
TOP VIEW
SENSE1
32
OUT2
GATE2
31
30
SENSE2 OUT3
29
28
GATE3
27
SENSE3 OUT4
26
25
GATE1
1
24 GATE4
OUT1
2
23 SENSE4
INT2
3
22
VIN
SGND1 4
21
PMAX
CLS5
5
20
VCC
AUTO
6
19
PGND
MID
7
18
SGND2
INT1
8
17
DGND
9
10
11
12
13
14
15
16
SCL
SDAO
SDAI
EN
A0
A1
A2
A3
QFN-32 (5mmx5mm)
MP3924 Rev. 1.0
7/16/2021
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© 2021 MPS. All Rights Reserved.
3
MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
PIN FUNCTIONS
Pin #
Name
1
GATE1
2
OUT1
3
INT2
4
SGND1
5
CLS5
6
AUTO
7
MID
8
INT1
9
SCL
10
SDAO
11
SDAI
12
EN
13
A0
14
A1
MP3924 Rev. 1.0
7/16/2021
Description
MOSFET gate driver for port 1. Float the GATE1 pin if not used.
Output voltage sense pin for port 1. Connect OUT1 to the output interface return for
detecting, classifying, voltage sensing, and current limit foldback control. Float the OUT1
pin if not used.
High-priority interrupt request pin. INT2 pulls low when the selected high-priority
interrupt source register is set and the interrupt is enabled. INT2 is an open-drain output.
Connect INT2 to DGND if the interrupt function is not used.
Current sense negative input for port 1 and port 2. Connect SGND1 to the low-side
terminal of the sense resistor. For an accurate current sense, use a Kelvin connection
when connecting SGND1 to the PCB. Connect SGND1 to DGND if not used.
Class 5 enable input. CLS5 is internally pulled down to DGND through a 50kΩ resistor.
Leave CLS5 disconnected to disable the classification for Class 5 devices (IEEE 802.3atcompliant mode). Connect CLS5 to VCC to enable the classification of Class 5 devices.
CLS5’s status is latched when the device starts up, or after a reset condition. If CLS5’s
status changes after start-up, there is no effect.
Automatic mode setting pin. AUTO is internally pulled up to VCC through a 50kΩ resistor
(an external 10kΩ resistor can be added). Float the AUTO pin to make automatic mode the
default. Connect the AUTO pin to DGND to make shutdown mode the default. AUTO’s
status is latched when the device starts up, or after a reset condition. If AUTO’s status
changes after start-up, there is no effect.
Midspan mode setting. MID is internally pulled up to VCC through a 50kΩ resistor (an
external 10kΩ resistor can be added). Float the MID pin for midspan mode, then wait 2.8s
to reinitiate detection. Connect the MID pin to DGND to disable midspan mode. MID’s
status is latched when the device starts up, or after a reset condition. If MID’s status
changes after start-up, there is no effect.
Interrupt request pin for all interrupt source events. INT1 pulls low when the interrupt
register is set and the interrupt function is enabled. INT1 is an open-drain output. Connect
INT1 to DGND if the interrupt function is not used.
I2C clock input pin. Connect SCL to VCC using an external pull-up resistor (typically
4.7kΩ). Connect SCL to VCC if the I2C interface is not used.
I2C serial data output pin. SDAO is an open-drain output. Connect SDAO to VCC using
an external pull-up resistor (typically 4.7kΩ). Connect SDAO to SDAI for non-isolated
applications. Connect SDAO to DGND if the I2C interface is not used.
I2C serial data input pin. Connect SDAI to VCC using an external pull-up resistor
(typically 4.7kΩ). Connect SDAI to SDAO for non-isolated applications. Connect SDAI to
DGND if the I2C interface is not used.
Enable input. EN turns all internal circuits and four ports (except the VCC regulator) on
and off. To turn on the device automatically, externally connect EN to VCC.
MP3924 address setting pin. Connect A0 to VCC or DGND to set the lower 4-bit address
bits (address = 010 A3 A2 A1 A0). The address signal is latched when the device starts up
or is reset. A0 is internally pulled up to VCC through a 50kΩ resistor (an external 10kΩ
resistor can also be added).
MP3924 address setting pin. Connect A1 to VCC or DGND to set the lower 4-bit address
bits (Address = 010 A3 A2 A1 A0). The address signal is latched when the device starts up
or is reset A1 is internally pulled up to VCC through a 50kΩ resistor (an external 10kΩ
resistor can also be added).
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4
MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
PIN FUNCTIONS (continued)
Pin #
Name
15
A2
16
A3
17
DGND
18
SGND2
19
PGND
20
VCC
21
PMAX
22
VIN
23
SENSE4
24
GATE4
25
OUT4
26
SENSE3
27
GATE3
28
OUT3
29
SENSE2
30
GATE2
31
OUT2
32
SENSE1
MP3924 Rev. 1.0
7/16/2021
Description
MP3924 address setting pin. Connect A2 to VCC or DGND to set the lower 4-bit address
bits (Address = 010 A3 A2 A1 A0). The address signal is latched when the device starts up
or is reset. A2 is internally pulled up to VCC through a 50kΩ resistor (an external 10kΩ
resistor can be added).
MP3924 address setting pin. Connect A3 to VCC or DGND to set the lower 4-bit address
bits (Address = 010 A3 A2 A1 A0). The address signal is latched when the device starts up
or is reset. A3 is internally pulled up to VCC through a 50kΩ resistor (an external 10kΩ
resistor can also be added).
Ground of the internal digital and analog circuit.
Current sense negative input for port 3 and port 4. Connect SGND2 to the low-side
terminal of the sense resistor. For an accurate current sense, use a Kelvin connection
when connecting SGND2 to the PCB. Connect SGND2 to DGND if not used.
Ground of input power supply.
3.3V internal regulator output for analog and digital circuit supply. A minimum 1µF
ceramic capacitor must be placed between VCC and DGND.
Maximum loading power setting pin. Connect one resistor from the PMAX pin to DGND
to set the total power capability on all four output ports. The MP3924 limits the total power
on all four ports below this set limit. The PMAX setting signal is latched when the device
starts up or is reset.
Power supply input for both VCC and output ports. Bypass VIN with at least one
0.1µF/100V ceramic capacitor, placed between VIN and PGND.
Current-sense pin from the high-side sense resistor terminal for port 4. It is
recommended to use a 0.25Ω sense resistor for all applications. For an accurate current
sense, use a Kelvin connection when connecting SENSE4 during PCB layout. Connect
SENSE4 to DGND if not used.
MOSFET gate driver for port 4. Float the GATE4 pin if not used.
Output voltage sense pin for port 4. Connect OUT4 to the return of the output interface
for detecting, classifying, voltage sensing, and current limit foldback control. Float the
OUT4 pin if not used.
Current-sense pin from the high-side sense resistor terminal for port 3. It is
recommended to use a 0.25Ω sense resistor for all applications. For an accurate current
sense, use a Kelvin connection when connecting SENSE3 during PCB layout. Connect
SENSE3 to DGND if not used.
MOSFET gate driver for port 3. Float the GATE3 pin if not used.
Output voltage sense pin for port 3. Connect OUT3 to the return of the output interface
for detecting, classifying, voltage sensing, and current limit foldback control. Float the
OUT3 pin if it is not used.
Current-sense pin from the high-side sense resistor terminal for port 2. It is
recommended to use a 0.25Ω sense resistor for all applications. For an accurate current
sense, use a Kelvin connection when connecting SENSE1 during PCB layout. Connect
SENSE1 to DGND if not used.
MOSFET gate driver for port 2. Float the GATE2 pin if not used.
Output voltage sense pin for port 2. Connect OUT2 to the return of the output interface
for detecting, classifying, voltage sensing, and current limit foldback control. Float the
OUT2 pin if it is not used.
Current-sense pin from the high-side sense resistor terminal for port 1. It is
recommended to use a 0.25Ω sense resistor for all applications. For an accurate current
sense, use a Kelvin connection when connecting SENSE1 during PCB layout. Connect
SENSE1 to DGND if not used.
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5
MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
ABSOLUTE MAXIMUM RATINGS (1)
VIN .............................................. -0.3V to +80V
OUT1~4 ................................ -0.3V to VIN + 0.3V
GATE1~4, SENSE1~4 ................. -0.3V to +22V
DGND, SGND1, SGND2............. -0.3V to +0.3V
All other pins ............................... -0.3V to +6.5V
INT1, INT2, SDAO maximum sink current……...
………………………………………………..20mA
Continuous power dissipation (TA = 25°C)
…………………………………………...3.9W (2) (4)
Junction temperature ............................... 150°C
Lead temperature .................................... 260°C
Storage temperature ................ -65°C to +150°C
Recommended Operating Conditions (3)
Supply voltage (VIN) ......................... 44V to 57V
INT1, INT2, SDAO maximum sink current……...
…………………………………………………5mA
Operating junction temp (TJ). ... -40°C to +125°C
MP3924 Rev. 1.0
7/16/2021
Thermal Resistance
θJA
θJC
(4)
EV3924-U-00A
................. 32 ......... 2 .. °C/W
JESD51-7 (5) ......................... 36 ......... 8 .. °C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature, TJ (MAX), the junction-toambient thermal resistance, θJA, and the ambient
temperature, TA. The maximum allowable continuous power
dissipation at any ambient temperature is calculated by P D
(MAX) = (TJ (MAX) - TA) / θJA. Exceeding the maximum
allowable power dissipation can cause excessive die
temperature, and the regulator may go into thermal shutdown.
Internal thermal shutdown circuitry protects the device from
permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on EV3924-U-00A, 2-layer, 88mmx106mm PCB.
5) The value of θJA given in this table is only valid for comparison
with other packages and cannot be used for design purposes.
These values were calculated in accordance with JESD51-7,
and simulated on a specified JEDEC board. They do not
represent the performance obtained in an actual application.
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6
MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
ELECTRICAL CHARACTERISTICS
VIN = 54V, PGND, DGND, SGND1, and SGND2 are connected together, RSENSE = 0.25Ω,
TJ = -40°C to +125°C (6), typical value is tested at TJ = 25°C, unless otherwise noted.
Parameter
Power Supply
Input under-voltage lockout
(UVLO)
Input UVLO hysteresis
Input over-voltage lockout
(OVLO)
Symbol
Condition
VIN_UVLO
VIN rising
VIN_OVP
VIN_OVP_HYS
Input power okay threshold
VIN_OK
Input power okay hysteresis
VIN_OK_HYS
tEN_OFF
Supply current
IIN
Shutdown current
ISD
VCC regulation
VCC
VCC UVLO
VCC_UVLO
VCC UVLO hysteresis
VCC current limit
Power-on reset (POR) delay
Detection
Max
Units
28
29.5
31
V
2.7
VIN rising
62
VIN rising
38
Pull EN to 0V, 3.3V
EN pin high pulse duration
for start-up or low-pulse
duration for shutdown
Logic pin is floating, no
connection for all output
ports, AUTO = low
V
V
µA
150
µs
120
2
EN = 0V
Load = 0mA
Load = 15mA
VCC rising
V
V
0
4
150
3.3
3.2
2.3
First detection voltage
Second detection voltage
VDET1
VDET2
Test the VIN to OUTx pins
Test the VIN to OUTx pins
Detection voltage slew rate
Detection current limit
Short-circuit detection
threshold
Open-circuit current
threshold
VSLEW
CDET = 0.1µF
Short VIN to OUTx
1
First detection voltage
MP3924 Rev. 1.0
7/16/2021
42
0.4
VCC = DGND
From VCC on to detection
IOPEN
40
V
V
µs
2.5
tPOR
VSC
68
0.7
VCC_UV_HYS
IDET_LIMIT
65
V
2.8
100
VHI
VLI
tEN_ON
EN turn on/off delay
Typ
VIN_UVLO_HYS
Input OVLO hysteresis
Input OVP lockout delay (7)
EN logic high voltage
EN logic low voltage
EN input current
Min
3.6
7.2
2.5
mA
µA
V
2.7
V
170
17
0.5
mV
mA
ms
4
8
V
V
1.2
0.02
1.5
V/µs
mA
1
1.5
1.8
V
10
15
25
µA
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7
MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VIN = 54V, PGND, DGND, SGND1, and SGND2 are connected together, RSENSE = 0.25Ω,
TJ = -40°C to +125°C (6), typical value is tested at TJ = 25°C, unless otherwise noted.
Parameter
Symbol
Minimum valid detection
resistance
Maximum valid detection
resistance
Maximum valid capacitance
Detection time
Condition
Min
Typ
Max
Units
RGOODL
15
17
19
kΩ
RGOODH
26.5
30
33
kΩ
µF
ms
ms
CGOOD_MAX
tDET
Second detection phase
Detection reset time
tRESET
Port reset by internal
discharge between VIN and
OUTx before detection starts
Midspan mode detection
delay
tMIDDLY
Re-detection interval, MID = 1
tREMDLY
Re-detection after one power
removal event due to error
condition (ICUT, ILIM,
INRUSH), fault timer = 60ms
MID = 0, automatic and semiautomatic mode
Power removal detection
delay
1
280
9
310
80
100
2.8
sec
0.8
0.96
1.12
sec
16
18
20
V
8
7.6
6
6.5
70
15
8.8
10
9
22
9.8
14
11
mA
ms
V
mA
ms
5.5
13.5
21.5
31.5
6.5
14.5
23
33
7.5
15.5
24.5
34.5
mA
mA
mA
mA
45.5
48
50.5
mA
100
ms
3
ms
0.5
ms
Classification
Classification output voltage
Classification current limit
Class event time
Mark event voltage
Mark event current limit
Mark event time
Classification current
threshold
Port start-up delay
Port shutdown delay
Start-up sequence delay (9)
MP3924 Rev. 1.0
7/16/2021
VCLS
ICLS_ILIM
tCLE
VMARK
IMARK_ILIM
tME
ICLS
tPON
Test VIN to OUTx pins during
classification, load < 60mA
Short VIN to OUTx
Test VIN to OUTx pins
Short VIN to OUTx
Class 0 to 1
Class 1 to 2
Class 2 to 3
Class 3 to 4
Class 4 to over-current (OC)
condition (or Class 5 (8))
Automatic mode from
detection ending to power
port above 21V
Manual mode, from command
to output port above 21V
From command off to gate <
1V
From one channel detection
to the next channel detection
if the first channel powers up
in automatic mode
0.5
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sec
8
MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VIN = 54V, PGND, DGND, SGND1, and SGND2 are connected together, RSENSE = 0.25Ω,
TJ = -40°C to +125°C (6), typical value is tested at TJ = 25°C, unless otherwise noted.
Parameter
Gate Driver
Symbol
Condition
GATE source capability
ISOURCE
Port start-up, VGATE = GND
-43
µA
Port shutdown, VGATE = 10V
Port shutdown, VGATE < 1V
Trigger SCP,
VSENSE = 450mV,
VGATE = 5V (7)
Float GATE pin
60
9
µA
mA
100
mA
10
V
0.2
MΩ
-270
1
µA
µA
2.5
V
GATE sink capability
GATE clamp voltage
OUT Pin
ISINK
VGS_MAX
OUT pin resistance
ROUT
OUT pin bias current
IOUT
Min
Between VIN and OUTx, pull
OUTx high in idle state
(detection/classification off,
port shutdown)
OUTx = 0V, port start-up
OUTx = 54V, port shutdown
Typ
Max
Units
Protection
Output power good (PG)
rising threshold
Output PG hysteresis
VPG
Current limit threshold
VILIM
Over-current (OC) detection
threshold
VCUT
Foldback initial voltage
Foldback end voltage
Foldback minimum current
limit
MP3924 Rev. 1.0
7/16/2021
1.5
VPG_HYS
PG delay
Current limit timer
OC timer
Start inrush current limit
timer
OUTx pin voltage decrease
tILIM
tICUT
tINRUSH
VFOLD_ST
VFOLD_END
VLIM_MIN
2
400
mV
111.5
224
278.25
98.44
ms
µs
mV
mV
mV
mV
Low to high deglitch
High to low deglitch
Class 0~3, ILIMx bit = 0
Class 4, ILIMx bit = 1
Class 5, ILIMx bit = 1
Class 0~3 (ICUTx = 000)
101
201
251.75
89.06
3
10
106.25
212.5
265
93.75
Class 4 (ICUTx = 100)
Class 5 (ICUTx = 101)
TILIM = 11
TCUT = 10
154.38
218.5
50
50
162.5
230
60
60
170.63
241.5
70
70
mV
mV
ms
ms
50
60
70
ms
TINRUSH = 10
OUTx pin voltage when ILIM
decreases, ILIMx bit = 0
OUTx pin voltage when ILIM
decreases, ILIMx bit = 1
OUTx pin voltage when ILIM
decreases to minimum value
Short VIN to OUTx, FBLIMT
bit = 1, Class 4
Short VIN to OUTx, FBLIMT
bit = 0, Class 4
32
V
18
V
46
V
40
mV
22
mV
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9
MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VIN = 54V, PGND, DGND, SGND1, and SGND2 are connected together, RSENSE = 0.25Ω,
TJ = -40°C to +125°C (6), typical value is tested at TJ = 25°C, unless otherwise noted.
Parameter
Symbol
Short circuit fast-off
threshold
VSCP
Condition
ILIMx bit = 0
ILIMx bit = 1
Sense pin bias current
Thermal shutdown (7)
Thermal shutdown
hysteresis (7)
Total Load Power Limit
Typ
Max
212
425
PMAX
Maximum load capability on
all four ports
PMAX_LIMT
tMAX_DLY
Units
mV
mV
-1
Load power limit on all four
ports
Maximum load power
protection delay
Min
150
µA
°C
25
°C
RMAX = 49.9kΩ
RMAX = 120kΩ
49.9
120
W
W
Float the PMAX pin
204.8
W
60
ms
2
ms
TPMAX bit = 10
100% x PMAX < load < 150% x
PMAX
Load > 150% x PMAX
+1
DC Load Disconnection
DC disconnect hold
threshold
DC connect power time
VDCHOLD
tDCON
DC disconnect power
tDCOFF
remove time
Analog-to-Digital Converter (ADC)
Decrease output load until
output port power off
Load time to reset tDCOFF timer
Time from load < VDCHOLD to
gate off
1.25
1.875
2.5
mV
37.5
43.75
50
ms
300
350
400
ms
ADC resolution
Max ADC PMAX setting
range
ADC results = 1 1111 1111
(2.4mA/count)
ADC results = 1 1111 1111
(0.15V/count)
ADC results = 0 0000 0000 to
1 1111 1111
(0.4°C/count)
ADC results = 1 1111 1111
(0.4W/count)
Current conversion
Max ADC current range
Max ADC voltage range
ADC junction temperature
range
Voltage conversion
Temperature conversion (7)
PMAX setting conversion
MP3924 Rev. 1.0
7/16/2021
9
bits
1.216
A
76.65
V
-40
+164.4
°C
204.8
W
I = 600mA
254
count
V = 44V
V = 57V
TJ = 25°C
293
380
163
count
count
count
TJ = 125°C
RMAX = 49.9kΩ
RMAX = 120kΩ
413
125
300
count
count
count
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VIN = 54V, PGND, DGND, SGND1, and SGND2 are connected together, RSENSE = 0.25Ω,
TJ = -40°C to +125°C (6), typical value is tested at TJ = 25°C, unless otherwise noted.
Parameter
Symbol Condition
Min
Typ
Logic Interface (SCL, SDAI, SDAO, INT1, INT2, MID, A0, A1, A2, A3, AUTO, CLS5)
Max
Units
Input logic low voltage
VLI
0.4
V
Input logic high voltage
Logic input current
Open-drain output logic low
voltage
Open-drain output logic high
leakage
Internal pull-up/down
Resistance
VHI
+1
V
µA
0.4
V
1
µA
VLO
For SCL, SDAI
Sink current = 3mA,
SDAO, INT1, INT2
2
-1
Open drain to 3.3V
RUP
A0, A1, A2, A3, AUTO, MID
to VCC, CLS5 to DGND
50
kΩ
Notes:
6)
7)
8)
9)
Guaranteed by over-temperature correlation.
Guaranteed by engineering sample characterization.
If CLS5 is enabled, the MP3924 treats the classification current range from the upper of class 4 to the classification current limit as class 5.
Guaranteed by detection time, classification time, and start-up delay time.
MP3924 Rev. 1.0
7/16/2021
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
TYPICAL CHARACTERISTICS
VIN = 54V, TA = 25°C, unless otherwise noted.
200
180
160
140
120
100
80
60
40
20
0
SUPPLY CURRENT (mA)
SHUTDOWN CURRENT (μA)
VIN Shutdown Current vs. Input
Voltage
25
30
35
40
45
50
INPUT VOLTAGE (V)
55
VIN Supply Current vs. Input
Voltage
2.4
2.2
2
1.8
1.6
1.4
1.2
1
25
60
VIN SUPPLY CURRENT (mA)
SHUTDOWN CURRENT (μA)
VIN Shutdown Current vs.
Junction Temperature
250
200
150
100
50
0
-50
60
2.2
2
1.8
1.6
1.4
1.2
1
-50
0
50
100
150
JUNCTION TEMPERATURE (℃)
VIN OVP vs. Junction
Temperature
VIN OVP THRESHOLD (V)
32
30
VIN UVLO (V)
55
2.4
0
50
100
150
JUNCTION TEMPERATURE (℃)
28
26
24
Rising
22
Falling
20
0
50
100
JUNCTION TEMPERATURE (℃)
MP3924 Rev. 1.0
7/16/2021
35 40 45 50
INPUT VOLTAGE (V)
VIN Supply Current vs. Junction
Temperature
VIN UVLO vs. Junction
Temperature
-50
30
150
67
65
63
61
Rising
59
Falling
57
55
-50
0
50
100
150
JUNCTION TEMPERATURE (℃)
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
TYPICAL CHARACTERISTICS (continued)
VIN = 54V, TA = 25°C, unless otherwise noted.
VCC UVLO vs. Junction
Temperature
2.5
2.6
2
2.5
VCC UVLO (V)
EN UVLO (V)
EN UVLO vs. Junction
Temperature
Rising
1.5
Falling
1
0.5
2.4
2.3
Rising
2.2
Falling
2.1
0
2
-50
0
50
100
150
JUNCTION TEMPERATURE (℃)
-50
VCC Voltage vs. Junction
Temperature
Detection Voltage vs. Junction
Temperature
VCC load = 15mA
DETECTION VOLTAGE (V)
VCC VOLTAGE (V)
3.4
3.3
3.2
3.1
3
2.9
2.8
2.7
-50
0
50
100
JUNCTION TEMPERATURE ( C)
150
10
8
6
4
Second Detection
2
First Detection
0
-50
0
50
100
150
JUNCTION TEMPERATURE (℃)
Class Voltage vs. Junction
Temperature
Valid Detection Resistance vs.
Junction Temperature
35
20
30
CLASS VOLTAGE (V)
VALID DETECTION RESISTANCE
(kΩ)
0
50
100
150
JUNCTION TEMPERATURE (℃)
25
20
15
Maximum Resistance
10
Minmum Resistance
5
18
16
14
12
10
0
-50
MP3924 Rev. 1.0
7/16/2021
0
50
100
JUNCTION TEMPERATURE (℃)
150
-50
0
50
100
150
JUNCTION TEMPERATURE (℃)
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
TYPICAL CHARACTERISTICS (continued)
VIN = 54V, TA = 25°C, unless otherwise noted.
Mark Voltage vs. Junction
Temperature
Class Current vs. Junction
Temperature
80
CLASS CURRENT (mA)
MARK VOLTAGE (V)
11
10
9
8
7
6
70
60
-50
50
40
30
20
10
-50
0
50
100
150
JUNCTION TEMPERATURE (℃)
ICUT Limit vs. Junction
Temperature
250
250
200
200
150
Class 4
100
Class 0
50
0
50
100
150
JUNCTION TEMPERATURE (℃)
ILIM Limit vs. Junction
Temperature
ILIM LIMIT (mV)
ICUT LIMIT (mV)
Class 3 to 4
Class 1 to 2
0
5
150
100
Class 4
50
Class 0
0
0
DC Hold Threshold vs. Junction
Temperature
2.1
2
1.9
1.8
1.7
1.6
1.5
-50
MP3924 Rev. 1.0
7/16/2021
-50
0
50
100
150
JUNCTION TEMPERATURE (℃)
0
50
100
150
JUNCTION TEMPERATURE (℃)
INRUSH CURRENT LIMIT (mV)
-50
DC HOLD THRESHOLD (mV)
Class 4 to OCP
Class 2 to 3
Class 0 to 1
0
50
100
150
JUNCTION TEMPERATURE (℃)
Inrush Current Limit vs.
Junction Temperature
115
110
105
100
95
90
-50
0
50
100
150
JUNCTION TEMPERATURE (℃)
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 54V, set with a Class 4 PD load, TA = 25°C, unless otherwise noted.
No PD Connection
CH1: VOUTx
- VVIN
2V/div.
Class 0~3 PD Connection
CH1: VOUTx
- VVIN
20V/div.
100ms/div.
100ms/div.
Start-Up through VIN
Class 4 PD Connection
No PD connection
R1: VIN
50V/div.
CH1: VOUTx
- VVIN
20V/div.
CH4: OUT4
50V/div.
CH3: OUT3
50V/div.
CH2: OUT2
50V/div.
CH1: OUT1
50V/div.
100ms/div.
400ms/div.
Start-Up through VIN
Shutdown through VIN
Class 4 PD connection
No PD connection
R1: VIN
50V/div.
R1: VIN
50V/div.
CH4: OUT4
50V/div.
CH4: OUT4
50V/div.
CH3: OUT3
50V/div.
CH3: OUT3
50V/div.
CH2: OUT2
50V/div.
CH2: OUT2
50V/div.
CH1: OUT1
50V/div.
CH1: OUT1
50V/div.
400ms/div.
MP3924 Rev. 1.0
7/16/2021
400ms/div.
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 54V, set with a Class 4 PD load, TA = 25°C, unless otherwise noted.
Shutdown through VIN
Start-Up through EN
Class 4 PD connection
No PD connection
R1: VIN
50V/div.
R1: VEN
2V/div.
CH4: OUT4
50V/div.
CH4: OUT4
50V/div.
CH3: OUT3
50V/div.
CH3: OUT3
50V/div.
CH2: OUT2
50V/div.
CH2: OUT2
50V/div.
CH1: OUT1
50V/div.
CH1: OUT1
50V/div.
400ms/div.
400ms/div.
Start-Up through EN
Shutdown through EN
Class 4 PD connection
No PD connection
R1: VEN
2V/div.
R1: VEN
2V/div.
CH4: OUT4
50V/div.
CH4: OUT4
50V/div.
CH3: OUT3
50V/div.
CH3: OUT3
50V/div.
CH2: OUT2
50V/div.
CH2: OUT2
50V/div.
CH1: OUT1
50V/div.
CH1: OUT1
50V/div.
400ms/div.
400ms/div.
Shutdown through EN
PMAX Limit Triggered (10)
Class 4 PD connection
R1: VEN
2V/div.
CH4: OUT4
50V/div.
R1: IIN
500mA/div.
CH4: OUT4
50V/div.
CH3: OUT3
50V/div.
CH3: OUT3
50V/div.
CH2: OUT2
50V/div.
CH2: OUT2
50V/div.
CH1: OUT1
50V/div.
CH1: OUT1
50V/div.
400ms/div.
400ms/div.
Note:
10) The maximum power (PMAX) is set to 50W. If the load’s power exceeds 50W, port 4 shuts down with default priority.
MP3924 Rev. 1.0
7/16/2021
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 54V, set with a Class 4 PD load, TA = 25°C, unless otherwise noted.
ICUT Triggered
ILIM Triggered
CH2: VIN
20V/div.
CH1: OUT1
20V/div.
CH2: VIN
20V/div.
CH1: OUT1
20V/div.
CH4: IOUT1
500mA/div.
CH4: IOUT1
500mA/div.
20ms/div.
20ms/div.
Output SCP Triggered
Inrush Current Limit Triggered
CH2: VIN
20V/div.
CH2: VIN
20V/div.
CH1: OUT1
20V/div.
CH1: OUT1
20V/div.
CH4: IOUT1
1A/div.
CH4: IOUT1
1A/div.
100ms/div.
100ms/div.
Output Disconnection Triggered
CH2: VIN
20V/div.
CH1: OUT1
20V/div.
CH4: IOUT1
100mA/div.
200ms/div.
MP3924 Rev. 1.0
7/16/2021
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
FUNCTIONAL BLOCK DIAGRAM
VCC
VIN
VIN
VIN
VCC LDO
Detection
Classification
EN
UVLO
OVP
Enable
Output
Port x4
4V, 8V
8.8V, 18V
OUT 1~4
Current
Sense
PSE Interface
Logic Control
AUTO
MID
GATE Driver
Control
CLS5
GATE 1~4
PMAX
Register
Memory
A3~A0
INT1
INT2
I2 C
SCL SDAI SDAO
ADC
VIN, Temp, PMAX
ICUT, ILIM, Inrush,
Disconnect.
Control
Watchdog
PGND
SENSE 1~4
SGND 1~2
DGND
Figure 2: Functional Block Diagram
MP3924 Rev. 1.0
7/16/2021
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
OPERATION
The MP3924 is a quad-output power source
equipment (PSE) power controller for IEEE
802.3af/at power over Ethernet (PoE)
applications. The device establishes a method
of communication between the powered device
(PD) and PSE with detection, classification, and
marked events. The MP3924 also provides
functions for current and voltage protections in
automatic mode as well as I2C command
control mode.
Power Supply
The MP3924 is designed for PoE applications
that require a 44V to 57V input. The MP3924
powers the output port from this input source,
then generates an internal 3.3V for the digital
and analog circuits. The VCC regulator is
enabled after VIN powers on. When VIN
exceeds VIN_UVLO, the part is enabled after a
delay (tPOR). All functions can be enabled or
disabled by both VCC and EN going above or
below the under-voltage lockout (UVLO) value,
respectively.
The MP3924 uses the PORT_ENABLE register
to disable functions related to all ports, as well
as functions related to individual ports. The
PORT_ENABLE register does not include VIN,
VCC, or EN UVLO.
The device can be reset by any of the below
conditions:
VIN or VCC UVLO
EN turning off
Writing 0 to the ENAL bit
After the MP3924 resets, all internal register are
set to their default values. The following pins
are read and latched into the internal registers:
AUTO
MID
CLS5
PMAX
A3~A0
During normal operation, changes to these pins
do not affect the registers.
The MP3924 includes one VIN over-voltage
protection (OVP) threshold at about 65V. All
ports shut down if input OVP is triggered. The
MP3924 Rev. 1.0
7/16/2021
MP3924 outputs can restart with a new
detection cycle after OVP recovery.
PD Detection
In normal idle operation, the MP3924 detects
the output port for a valid PD connection, which
typically has a 24.9kΩ resistance (see Figure 3).
OUTx
Pin
VIN
80ms
VIN (4V)
VIN (8V)
140ms
140ms
Discharge
Detection for 24.9kΩ
Classify
t
Figure 3: PD Detection Process
During this detection process, the MP3924
generates a two-phase voltage (4V/8V) through
the OUTx pin. Meanwhile, the external
MOSFET is off (see Figure 4).
VIN
4V/8V
OUTx
Current
Sense
Figure 4: PD Detection Block Diagram
The OUTx pin sinking current capability is
limited to about 1.2mA. The current and voltage
through the OUTx pin are measured. If the
effective resistance with the two-point test is
valid, this means that one PD device is
connected to the PSE port. The MP3924
integrates a filter to avoid 50Hz/60Hz power line
noise.
After the detection cycle, the DETCx bit is set,
and an interrupt signal is generated to report
that detection has completed. The host can
read each port’s DET/CLS_RESULT register to
obtain the detection results. After one detection
cycle, the MP3924 enters classification mode if
the PD connection is valid.
If the output port is shorted or the detected
capacitance is too high, the OUTx pin limits the
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
sink current to about 1.2mA. Then the detection
cycle ends.
method to enable Class 5 is to use the enable
the CLS5_ENx bits on a port.
If the output port has an open circuit in the first
phase detection period, the MP3924 ends the
detection cycle. If the OUTx pin has a low
impedance
to
PGND,
detection
ends
immediately.
During classification, the MP3924 outputs a
18V voltage on the OUTx pin (see Figure 5).
The device then measures the current though
the OUTx pin to determine the classification
level. After classification is complete, the status
bits (CLSCx) and interrupt are set. The
classification result is stored in the DET/CLS
Result register.
For other invalid resistance signatures, the
MP3924 ends detection after two-phase
detection. After one invalid detection result, the
MP3924 stays in idle mode and re-enables
detection within an 80ms port reset time. In
midspan mode, there is one delay time (about
2.8s) before the 80ms reset time.
Midspan Mode
If a port is set to midspan mode, the device
waits about 2.8s before attempting to detect a
PD connection. This can avoid detection
collision. Midspan mode can be set or reset by
the MID pin before the MP3924 starts up.
Midspan mode can also be configured via the
MIDx bits via the I2C interface during normal
operation. If the detection is valid, the device
exits midspan mode.
PD Classification
If the PD detection resistance is valid, the
device enters classification mode to measure
the power level of the connected PD. Different
classifications support 4W, 7W, 15.4W, or 30W
of power to the port. Based on the
IEEE802.3af/at standard, the MP3924 provides
one additional class: Class 5 (see Figure 5).
Class 5 classification has a 40W load capability,
which is valid when the CLS5_EN bit is enabled
and the classification current exceeds the Class
4 upper current threshold. If Class 5 is not
enabled, a classification current that exceeds
50.5mA results in an over-current (OC)
condition and a classification failure. If Class 5
is enabled, a classification current that exceeds
50.5mA results in a Class 5 classification level.
In this scenario, an OC condition refers to when
the current has triggered the current limit
threshold. OC conditions can occur with all
classes.
The CLS5 pin is internally pulled down to
DGND to disable Class 5 classification. Pull the
CLS5 pin high during a power-on reset (POR)
to enable Class 5 classification. Another
MP3924 Rev. 1.0
7/16/2021
VIN
18V
OUTx
Current
Sense
Figure 5: Classification Block Diagram
Classification is based on the IEEE802.3at
standards. If a classification result is in Class
0~3, the MP3924 only performs one-time
classification in accordance with IEEE 802.3af.
If Class 4 or Class 5 is detected in the first
classification event, the MP3924 performs a
second classification event when the voltages
on VIN and OUTx are the same. 2-event
classification can be enabled by 2EVNTENx
(see Figure 6).
OUTx
Pin
VIN
2-Event for Class 4/5
Valid
Detection
Class 1~3
t
Figure 6: 1-Event and 2-Event Classification
Between the two classifications, the MP3924
performs two time mark events between VIN
and OUTx with an 8.8V mark voltage. The
second classification result must be equal to the
first classification result, or the classification is
considered invalid.
After each 2-event classification, the output port
generates an 8.8V voltage to perform the mark
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
event. During a classification mark event, the
OUTx pins have sink and source current
capability. This means that the output port
voltage can use a 0.1µF capacitor to follow the
OUTx pin’s regulated voltage.
OUT
Pin
VIN
OUT1
OUT3
OUT2
If the detection is valid but the port does not
start up within 400ms in automatic or semiautomatic mode, then the port initializes a new
detection cycle.
Four-Channel Sequence
The MP3924 detects, classifies, and starts up
the ports one at a time. Port one is first,
followed by the second, third, and fourth ports.
If no PD is plugged in, the detection process
goes one by one (see Figure 7).
OUT
Pin
VIN
OUT1
OUT2
OUT3
OUT4
OUT1
OUT3
160ms
t
Figure 8: PD Plug into Port 2
If one of the ports has a PD load and the port
starts up, then the other ports repeat the
detection cycle, from channel one to channel
four. After one channel shuts down, it returns to
its place in the queue (see Figure 9).
OUT
Pin
VIN
OUT3
OUT4
OUT1
OUT2
OUT3
OUT4
OUT1
OUT2
Wait for the
next cycle
Internal
Discharge
t
Figure 9: PD Plug Out from Port 2
Over-Current Protection (OCP)
When the port is powered up, the MP3924
controls the inrush current. As a result, the
output port voltage ramps up smoothly until the
connected PD capacitor charges up to the
power source voltage. In this scenario, the
GATE pin voltage is controlled to limit the input
current (IIN) below 106.25mV / RSENSE.
If the PD capacitor value is too large or the
output port is shorted, the inrush current lasts
for a set time (tINRUSH). After tINRUSH, the port
output power turns off. tINRUSH can be configured
via the TINRUSH bit.
OUT2
80ms
Detection ends
due to open port
t
Figure 7: No PD on an Output Port
The next port starts detecting within the 80ms
discharge time after the previous port’s
detection cycle ends. Within this 80ms delay,
the port can be discharged below 4V before
detection starts (see Figure 8).
MP3924 Rev. 1.0
7/16/2021
OUT1
80ms
The classification circuit is disabled when the
classification result is valid and the port output
is powered up.
Start-Up
If the detection and classification results are
valid, the MP3924 ramps up the port’s output
power. This power is delivered to the PD circuit.
The PENx and PECx bits are then set to
indicate the port status. When the power supply
(VIN) is between 44V and 57V, the MP3924 can
operate from 31V and report over-voltage (OV)
conditions at 65V. If the OUTx pin voltage drops
below 2V, the PGx and PGCx bits are set to
indicate the power good (PG) result.
OUT4
If 106.25mV / RSENSE exceeds ICUT during the
inrush period, the ICUT timer (tICUT) begins
counting. After tICUT, the output turns off. It is
recommended for RSENSE to be 0.25Ω for all
applications. If one port shuts down due to the
start-up inrush current, then the STFx bits are
set to indicate a start failure event.
After start-up, the PGx bits are set to high to
indicate the port’s output power status. If the
load current exceeds VCUT / RSENSE (VCUT is
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
controlled by the ICUTx bits), then a timer (tICUT)
is enabled to record the OC condition.
OUTx
Pin
VIN
>0.96s
8The port turns once this timer finishes
counting. If the load current exceeds VCUT and
triggers VILIM / RSENSE, then the GATE pin
regulates the load at the current limit level. An
additional timer (tILIM) is enabled to record the
current limit event. tILIM is counted even if the
MP3924 is in current foldback mode.
VCUT detects the OC threshold, which is below
the VILIM threshold. tICUT starts counting when
the OC condition begins. If the load current
drops below VCUT, tICUT does not reset
immediately. Instead, tICUT counts down at a
rate that is 1/16 of how quickly is counts up.
The tICUT timer records for a total of 60ms for
every 0.96s + 0.06s detection window.
If the port shuts down due to an OC condition,
the port can be re-enabled only after tICUT
counts down to 0. This logic can detect a short
or repeated OC condition. The logic also
protects
the
external
MOSFET
from
overheating. tILIM and tNRUSH operate with the
same logic.
The over-current protection (OCP) timer does
not reset even if the device shuts down or the
EN bit turns off. This means that the port cannot
be re-enabled until the timer counts to 0 again.
In manual mode, the host should read the Read
and Clear register address continuously until
the register is reset to 0. Then the port is reenabled. In automatic mode, the MP3924
automatically restarts after the timer counts
down to 0.
When tICUT is completed, the related OUT port
shuts down (see Figure 10). At the same time,
the
POWER_STATUS
and
OVER_LOAD_STATUS registers are set to
indicate the power condition.
The default VCUT is different for Classes 0~3
than Class 4 and Class 5. VCUT can also be
configured. VILIM has three fixed values for
Classes 0~3, Class 4, and Class 5.
MP3924 Rev. 1.0
7/16/2021
Detect.
t
Current
ILIM
ICUT
5µF) if the cable is connected to a
legacy PD with a high input capacitor. The
LEGENx bits enable legacy detection mode. By
default, the LEGENx bits are set to 00 to
disable legacy detection. Table 1 on page 25
MP3924 Rev. 1.0
7/16/2021
lists the detection parameters. Legacy detection
returns
the
results
of
the
LEGACY_DETECT_RESULTx registers.
The MP3924 starts legacy detection after the
PD input voltage is discharged below 2.4V. If
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
the PD input voltage is high, a 250ms discharge
timer works with a 100kΩ load between the
OUTx pin and VIN. If the PD input exceeds
2.4V, a secondary 500ms discharge timer
begins. If the PD input voltage does not fall
below 2.4V after the two discharge times, then
the MP3924 is set to 0010 in the
LEGACY_DETECT_RESULTx registers.
After legacy detection starts, a fixed current is
charged to the PD input. The voltage difference
between two points is used to calculate the
effective capacitance.
If the capacitance is too great and the
measured voltage difference is below 0.5V,
then the MP3924 reports 0110. If the
capacitance is too low and the measured
voltage reaches 18.5V, then the MP3924
reports 0100 or 0101. All of these results are
invalid in legacy detection.
Table 1: Legacy Detection Measurements
Parameter
Minimum measurable
capacitance
Maximum measurable
capacitance
Capacitance test charge
current
Nominal measurement time
Maximum voltage before
start measurement
Duration of first port
discharge period
Duration of second port
discharge period
Maximum voltage during
measurement
Value
Units
5
µF
100
µF
500
µA
150
ms
2.4
V
250
ms
500
ms
18.5
V
If legacy detection is enabled and a legacy
device is detected in automatic mode, then the
detection
status
is
reported
in
the
LEGACY_DETECT_RESULTx
registers.
However, the device does not start up
immediately, as it requires a host command
through the I2C.
If LEGENx is set to 01 or 10 in automatic or
semi-automatic mode, there is initially one
standard detecting cycle. If the standard
resistance detection result is valid, then the
MP3924 does not continue legacy detection
and the classification process begins instead. If
MP3924 Rev. 1.0
7/16/2021
the standard resistance detection result is not
valid and legacy detection is valid, the MP3924
does not start the classification process, even if
the CLSENx bit is set. In this scenario, a
software command is required to trigger the
classification process.
If the following conditions are met, then PON
automatically powers the port (even if the
classification result does not match, or there is
an OC condition):
PON is enabled by the software after the
legacy detection is determined to be valid.
The MP3924 is in automatic or semiautomatic mode.
If the LEGENx bit is enabled in automatic or
semi-automatic mode, the legacy detection
result
repeats
and
refreshes
the
LEGACY_DETECT_RESULTx registers. This
process repeats until the LEGENx bit is
disabled. In manual mode, legacy detection
occurs once, then the LEGENx bits resets
automatically. It is recommended to use manual
mode.
Operation Modes
The MP3924 provides four operation modes to
flexibly control PoE communication and start-up:
automatic mode, semi-automatic mode, manual
mode, and shutdown mode. The AUTO pin and
the MODEx bits set the different modes, which
are described below in greater detail.
Automatic Mode
In automatic mode, the MP3924 automatically
controls and responds to all detection,
classification, and start-up functions. The
MP3924 handles these processes for each port
independently and without external I2C control.
Float the AUTO pin to force the MP3924 to
work in automatic mode.
In automatic mode, the MODEx bits are set to
11 when device turns on. The AUTO pin status
is only read once when the device turns on or
the MP3924 is reset. If a master is connected to
the MP3924 via the I2C, then the master can
change the MODEx bits to change the
operation mode. If there is no valid PD on the
port in automatic mode, then the MP3924
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
repeats the detection cycle until a valid PD is
connected.
If the MP3924 runs in automatic mode after
start-up or reset, the DETENx and CLSENx bits
are set high based on the AUTO pin. If a port is
set to automatic mode via the I2C, the DETENx
and CLSENx bits do not change.
Semi-Automatic Mode
In semi-automatic mode, the MP3924
automatically detects and classifies the
connected PD. However, the port does not start
up until an I2C command is issued. Set the
MODEx bits to 10 to force the MP3924 to
operate in semi-automatic mode.
When the port is set to semi-automatic mode,
the DETENx and CLSENx bits to not change. If
the DETENx and CLSENx bits are high in semiautomatic mode, the port repeats the detection
(and classification if the PD detection result is
valid) continuously. However, the port does not
start up until an I2C command is issued. If the
detection and classification are valid, the port
power can be turned on by a PONx bit. If the
port is powered off in semiautomatic mode, the
DETENx and CLSENx bits are reset to 0.
If the detection is valid and the port does not
turn on within 400ms in automatic or semiautomatic mode, then the port initiates a new
detection sequence. If the final detection and
classification sequences are determined to be
invalid before the start-up command is received,
the device fails to turn on. At the same time, the
STFx bit is set and the MP3924 resets the
command. If the detection and classification
sequences are valid but a start-up command is
not issued after 400ms, then the STFx bit is set.
Manual Mode
In manual mode, all functions are controlled via
the
I2C
interface.
Manual
mode
is
recommended for system diagnostics. Set the
MODEx bits to 01 to force the ports to operate
in manual mode.
In manual mode, the DETENx and CLSENx bits
are set to 0. Set these bits to 1 to enable onetime detection or classification. These bits reset
to 0 automatically.
The PONx bits power the port in manual mode.
The port turns on any time the PONx bit is set.
If the DETENx, CLSENx, and PONx bits are set
MP3924 Rev. 1.0
7/16/2021
simultaneously, then the MP3924 executes a
detection cycle first. If the DETENx and
CLSENx bits are set after the port starts up, the
MPM3924 ignores the DETENx and CLSENx
commands. The RDETx and RCLSx bits follow
the same logic.
If a PONx command is received while the
device recovers from a protection, then the
MP3924 does not turn on and the failure is
reported to the STFx bit.
Shutdown Mode
In shutdown mode, all detection, classification,
and port power output functions are off. To
force the MP3924 to operate in shutdown mode,
pull the AUTO pin to DGND before the device
starts up or resets. Set the MODEx bits to 00 to
set a port to shutdown mode.
Once a port is in shutdown mode, the power is
turned off and the corresponding port
event/status registers are cleared, except for
the PECx and PGCx bits. The I2C interface still
operates in shutdown mode, but the ports do
not respond to any detection, classification, or
port start-up commands.
In certain AUTO pin configurations, the MODE
bits are set to 00 or 11 after start-up (or after a
reset). After start-up, all ports can switch
between the four modes. The registers and port
states are not changed by these bits unless
shutdown mode is selected.
9-Bit ADC
The MP3924 integrates a 9-bit analog-to-digital
converter (ADC) to continuously measure the
input voltage, output voltage, load current, and
junction temperature. The ADC also measures
PMAX once following start-up, or if the device is
reset. When any ADC information is required,
the host controller can read the corresponding
data registers. ADC conversion only works
when the port is enabled and if there is no data
update for the corresponding port when the port
is shut down. The register cannot be updated
while it is read, even if ADC conversion is
complete for that segment of data.
I2C Interface
The MP3924 features an I2C interface. The 7-bit
device address is defined as 010 xxxx, where
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
the lower 4 bits are set by A3~A0 pins. When
the master sends an 8-bit address value, the 7bit I2C address should be followed by a 0 or 1 to
indicate a write or read operation, respectively.
The MP3924 works as a slave and supports
standard mode (100kbps) and fast mode
(400kbps) communication.
The I2C is a two-wire, bidirectional serial
interface consisting of a data line (SDA) and a
clock line (SCL). The lines are externally pulled
to a bus voltage when they are idle. When
connecting to the line, a master device
generates the SCL signal and device address,
then arranges the communication sequence. To
support communication with an isolated host
controller, the data interface is split into two
ports: SDAI and SDAO. For non-isolated
applications, SDAI and SDAO can be
connected to on another.
The MP3924 includes one alert response
address for MP3924 devices that are connected
through the address 0x0C (000 1100). If the
bus master controller sends the alert response
address when INT1 is low during an interrupt
event, then the MP3924 with the interrupt
request responds with its device address on the
SDAI line before releasing the INT1 line.
If two MP3924 devices respond simultaneously,
then the device with the lower address
succeeds in transmitting to the master via the
SDAI and SDAO lines. The device that attempts
to send a 1 but detects a 0 on the SDAI line
does not respond. After this, the MP3924 with
the higher address finishes responding. Its INT1
pin remains low until it receives the host
controller’s next alert response address read.
The MP3924 has one global address: 0110000.
This means that the host controller can write to
multiple MP3924 devices through the address
0x60 (01100000). If the host controller reads
multiple MP3924 through the address 0x61
(01100001), it works as an alert response
address.
While reading or writing, the MP3924 register
address is determined by the host command.
After each read/write data byte operation, the
register address automatically increases by 1
byte, and the host can read/write the next byte
without the new address command information.
If the system works with several host controllers,
MP3924 Rev. 1.0
7/16/2021
the address set by host 1 can respond to host 2,
if host 1 does not have data to read/write in that
address. If different registers must be read or
written, one address information is required to
set the correct register address.
I2C Data Validity
One clock pulse is generated for each
transferred data bit. The data on the SDA line
must be stable during the high period of the
clock. The high or low state of the data line can
only change when the clock signal on the SCL
line is low (see Figure 15).
Figure 15: Bit Transfer on the I2C Bus
The start (S) and stop (P) commands are
signaled by the master device, which signifies
the beginning and the end of the I2C transfer. A
start command is defined as the SDA signal
transitioning from high to low while the SCL
signal is high. A stop command is defined as
the SDA signal transitioning from low to high
while the SCL signal is high (see Figure 16).
Start Condition
Stop Condition
Figure 16: Start and Stop Conditions
Start and stop commands are always generated
by the master. The bus is considered to be
busy after a start command. The bus is
considered to be free again a minimum of 4.7μs
after the stop condition. The bus remains busy
if a repeated start (Sr) command is generated
instead of a stop command. The start (S) and
repeated start (Sr) commands are functionally
identical.
I2C Transfer Data
Every byte put on the SDA line must be 8 bits
long. Each byte has to be followed by an
acknowledge (ACK) bit. The acknowledge clock
pulse is generated by the master. The
transmitter releases the SDA line (high) during
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
the acknowledgement clock pulse. The receiver
must pull down the SDA line during the
acknowledge clock pulse so that it remains low
during the high period of this clock pulse.
Figure 17 shows the data transfer sequence.
After the start condition (S), a slave address is
sent. This address is 7 bits long followed by an
8th data direction bit (R/W). A 0 indicates a
transmission (write), while a 1 indicates a
request for data (read). A data transfer is
always terminated by a stop condition (P)
generated by the master. However, if a master
must communicate on the bus, it can generate
a repeated start condition (Sr) and address
another slave without first generating a stop
condition.
Start
Address
Condition
Data
Data
Stop
Condition
Figure 17: Complete Data Transfer
The MP3924 includes a full I2C slave controller.
The I2C slave fully complies with I2C
specification requirements. It requires a start
condition, a valid I2C address, a register
address byte, and a data byte for a single data
update. The MP3924 acknowledges that it has
received each byte by pulling the SDA line low
during the high period of a single clock pulse. A
valid I2C address selects the MP3924. The
MP3924 performs an update on the falling edge
of the LSB byte.
Figure 18 shows an I2C write example.
8 Bits
S
8 Bits
Slave Address
Master to Slave
Slave to Master
Wr
A
8 Bits
Register Address K
A
Write Data
A
P
A = Acknowledge (SDA = Low)
S = Start Condition
Write (Wr) = 0
NA = Not Acknowledge (SDA = High)
P = Stop Condition
Read (Rd) = 1
Figure 18: I2C Write Example
Figure 19 shows an I2C write example.
8 Bits
S
Slave Address
8 Bits
Wr
A
8 Bits
8 Bits
Register Address K
A
Sr
Register address to read specified
Slave Address
Rd
A
Read Data K
NA
P
Read register data from current register location
Master to Slave
A = Acknowledge (SDA = Low)
S = Start Condition
Slave to Master
NA = Not Acknowledge (SDA = High)
P = Stop Condition
Sr = Repeat
Start Condition
Write (Wr) = 0
Read (Rd) = 1
Figure 19: I2C Read Example
Figure 20 shows that the 0x00C address has a different read command from the standard I2C.
8 Bits
S
0x0C
8 Bits
Rd
A
Interrupted Device Address
NA
P
Read device address data by alert response address
Master to Slave
A = Acknowledge (SDA = Low)
S = Start Condition
Slave to Master
NA = Not Acknowledge (SDA = High)
P = Stop Condition
Sr = Repeat
Start Condition
Write (Wr) = 0
Read (Rd) = 1
Figure 20: 0x0C Read Example
MP3924 Rev. 1.0
7/16/2021
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
Watchdog
The MP3924 implements a watchdog to monitor
the SCL line for I2C activity. If there is no
transition on the SCL line for about 2.5s during
I2C communication, then the I2C port and all
power output ports shut down. The WDS bit is
set to 1 to indicate the error condition. WDS
must be reset before any port can be reenabled. After watchdog protection is triggered,
the port shuts down until the host re-enables
the ENx bits.
Over-Temperature Protection (OTP)
Over-temperature
protection
(OTP)
is
implemented to prevent the chip from thermal
runaway. When the junction temperature
exceeds its upper threshold, the MP3924 shuts
down all ports (the I2C and registers still work).
Once the temperature drops below its recovery
threshold, the ports are enabled again with a
new detection cycle. The OTP bit is set to 1
after OTP recovery.
By default, the watchdog is off after start-up. To
enable the watchdog function, set the WDEN bit
to 1.
MP3924 Rev. 1.0
7/16/2021
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
REGISTER DESCRIPTION
Register Map
Addr
Register
Interrupt Register
00h
INTERRUPT
INTERRUPT_
01h
MASK
INTERRUPT_
02h
PRIORITY
Configuration Register
03h
MODE_SETTING
MIDSPAN_
04h
SETTING
05h
PORT_ENABLE
06h
DET/CLS_ENABLE
Type
D7
D6
D5
D4
D3
D2
D1
D0
R
VINF
VINF_
M
VINF_
P
STF
STF_
M
STF_
P
OCP
OCP_
M
OCP_
P
CLSC
CLSC_
M
CLSC_
P
DETC
DETC_
M
DETC_
P
DCDIS
DCDIS_
M
DCDIS_
P
PGC
PGC_
M
PGC_
P
PEC
PEC_
M
PEC_
P
R/W
R/W
R/W
MP3924 Rev. 1.0
7/16/2021
MODE3
MODE2
MODE1
R/W
-
-
-
-
MID4
MID3
R/W
CLSEN
4
LCSEN
3
CLSEN
2
ENAL
CLSEN
1
EN3
-
-
-
-
EN4
DETEN
4
DISEN
4
R/W
DISCONNECT_
R/W
ENABLE
08h
FAULT_TIMER
R/W
09h
RESERVED
0Ah
RESERVED
0Bh
FOLDBACK_ILIM
R/W
2-EVENT_CLASS_
0Ch
R/W
5_ENABLE
PMAX_
0Dh
SHUTDOWN_
R/W
PRIORITY
INTERRUPT_
0Eh
R/W
ENABLE
GENERAL_
0Fh
R/W
CONTROL
Manual Control Register
DET/CLS_
10h
R/W
TRIGGER
POWER_ON/OFF_
11h
R/W
TRIGGER
12h
LEGACY_ENABLE
R/W
Current Limit Configuration Register
ICUT1_
13h
R/W
THRESHOLD
ICUT2_
14h
R/W
THRESHOLD
ICUT3_
15h
R/W
THRESHOLD
ICUT4_
16h
R/W
THRESHOLD
ILIM1_
17h
R/W
THRESHOLD
ILIM2_
18h
R/W
THRESHOLD
ILIM3_
19h
R/W
THRESHOLD
ILIM4_
1Ah
R/W
THRESHOLD
Status Register
20h
POWER_
R
SOURCE_
21h
R/C (12)
STATUS1
22h
POWER_
R
SOURCE_
23h
R/C (12)
STATUS2
24h
DET/CLS_
R
COMPLETE_
R/C (12)
25h
STATUS
DET/CLS_
26h
R
RESULT_1
DET/CLS_
27h
R
RESULT_2
DET/CLS_
28h
R
RESULT_3
DET/CLS_
29h
R
RESULT_4
2Ah
POWER_STATUS
R
2Bh
POWER_
R
STATUS_
(12)
2Ch
R/C
CHANGE
07h
MODE4
TPMAX
-
-
CLS5_
EN4
CLS5_
EN3
TINRUSH
CLS5_
CLS5_
EN2
EN1
PRTY4
DETEN3
DISEN3
TILIM
2EVNT
EN4
PRTY3
2EVNTEN3
MID2
MID1
EN2
EN1
DETEN
DETEN
2
1
DISEN
DISEN1
2
TCUT
FBLIMT
2EVNT
2EVNT
EN2
EN1
PRTY3
PRTY1
Reset State
1000 0000
1A A0 0A00 (11)
1010 0000
AAAA AAAA (11)
0000 MMMM (11)
0001 1111
AAAA AAAA (11)
0000 AAAA (11)
1010 1110
0000 0000
0000 0000
0000 0001
CCCC AAAA (11)
1110 0100
-
-
-
-
-
CLRPIN
CLRAI
NT
INTEN
0000 0001
-
-
-
-
-
PMAXEN
ADCEN
WDEN
0000 0A 10 (11)
RCLS4
RCLS3
RCLS2
RCLS1
RDET4
RDET3
RDET2
RDET1
0000 0000
POFF4
POFF3
POFF2
POFF1
PON4
PON3
PON2
PON1
0000 0000
LEGEN4
LEGEN3
LEGEN2
LEGEN1
0000 0000
-
-
-
-
-
ICUT1
0000 0000
-
-
-
-
-
ICUT2
0000 0000
-
-
-
-
-
ICUT3
0000 0000
-
-
-
-
-
ICUT4
0000 0000
-
-
-
-
-
-
-
ILIM1
0000 0000
-
-
-
-
-
-
-
ILIM2
0000 0000
-
-
-
-
-
-
-
ILIM3
0000 0000
-
-
-
-
-
-
-
ILIM4
0000 0000
FETF4
FETF3
FETF2
FETF1
VCCUV
OTP
VINOV
VINUV
0000 1001
-
-
-
-
-
-
VINOK
OVP
MAX
0000 0000
CLSC4
CLSC3
CLSC2
CLSC1
DETC4
DETC3
DETC2
DETC1
0000 0000
PEN3
PEN2
PEN1
0000 0000
PEC3
PEC2
PEC1
0000 0000
PG4
PG3
PG2
PG1
2EVNT
C1
2EVNT
C2
2EVNT
C3
2EVNT
C4
PEN4
PGC4
PGC3
PGC2
PGC1
PEC4
CLSR1
CLSR2
CLSR3
CLSR4
DETR1
0000 0000
DETR2
0000 0000
DETR3
0000 0000
DETR4
0000 0000
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
Addr
2Dh
2Eh
2Fh
30h
31h
32h
Register
OVER_LOAD_
STATUS
CURRENT_LIMIT_
STATUS
DISCONNECT_
STATUS
WATCHDOG_
33h
STATUS
34h
PIN_STATUS
LEGACY_
35h
DETECT_
RESULT1
LEGACY_
36h
DETECT_
RESULT2
ADC Results Register
40h
PORT_1_
CURRENT
41h
42h
OUT1_PIN_
VOLTAGE
43h
44h
PORT_2_
CURRENT
45h
46h
OUT2_PIN_
VOLTAGE
47h
48h
PORT_3_
CURRENT
49h
4Ah
OUT3_PIN_
VOLTAGE
4Bh
4Ch
PORT_4_
CURRENT
4Dh
4Eh
OUT4_PIN_
VOLTAGE
4Fh
50h
INPUT_VOLTAGE
51h
52h
JUNCTION_
TEMPERATURE
53h
54h
PMAX_POWER_
SETTING
55h
60h
DIE_ID
Type
R
R/C (12)
R
R/C (12)
R
R/C (12)
D7
D6
D5
D4
D3
D2
D1
D0
Reset State
OCUT4
OCUT3
OCUT2
OCUT1
STF4
STF3
STF2
STF1
0000 0000
-
-
-
-
OLIM4
OLIM3
OLIM2
OLIM1
0000 0000
-
-
-
-
DCDIS
4
DCDIS3
DCDIS2
DCDIS1
0000 0000
R
-
-
-
-
-
-
-
WDS
0000 0000
R
-
-
-
AUTO
A3
A2
A1
A0
000A DDDD (11)
R
LEGDET2
LEGDET1
0000 0000
R
LEGDET4
LEGDET3
0000 0000
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
Bit[8]
Bit[8]
Bit[8]
Bit[8]
Bit[8]
Bit [8]
Bit [8]
Bit [8]
Bit [8]
Bit [8]
Bit [8]
R
FAB
Bit [7]
Bit [7]
Bit [7]
Bit [7]
Bit [7]
Bit [7]
Bit [7]
Bit [7]
Bit [7]
Bit [7]
Bit [7]
MAJOR
_REV
Bit [6]
Bit [6]
Bit [6]
Bit [6]
Bit [6]
Bit [6]
Bit [6]
Bit [6]
Bit [6]
Bit [6]
Bit [6]
MINOR
_REV
Bit [5]
Bit [5]
Bit [5]
Bit [5]
Bit [5]
Bit [5]
Bit [5]
Bit [5]
Bit [5]
Bit [5]
Bit [5]
VENDO
R_ID
Bit [4]
Bit [4]
Bit [4]
Bit [4]
Bit [4]
Bit [4]
Bit [4]
Bit [4]
Bit [4]
Bit [4]
Bit [4]
0000
0000
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [3]
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Bit [2]
Bit [0]
Bit [1]
Bit [0]
Bit [1]
Bit [0]
Bit [1]
Bit [0]
Bit [1]
Bit [0]
Bit [1]
Bit [0]
Bit [1]
Bit [0]
Bit [1]
Bit [0]
Bit [1]
Bit [0]
Bit [1]
Bit [0]
Bit [1]
Bit [0]
Bit [1]
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 000P
PPPP PPPP (11)
-
-
-
-
Notes:
11) “A” represents the AUTO pin’s status during start-up. “M” represents the MID pin’s status during start-up. “C” represents CLS5 pin’s status
during start-up. “D” represents the A3~A0 address pin statuses during start-up. “P” represents the PMAX pin setting ADC results during
start-up.
12) R/C is read and clear address. Reading R/C clears the bit status after reading is complete.
MP3924 Rev. 1.0
7/16/2021
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
INTERRUPT REGISTERS
INTERRUPT (00h)
Read-only
Bits
Bit Name
Default Value
Description
Interrupt signal for VIN power failure. If this bit is set to 1, one of the following
scenarios has occurred:
The power on VIN is below 29.5V
VIN over-voltage protection (OVP)
VCC is under the under-voltage lockout (UVLO) threshold
Thermal shutdown
A power MOSFET failure
A PMAX event
D[7]
VINF
1
D[6]
STF
0
Interrupt signal for a start-up failure. If this bit is set to 1, at least one of the ports has
experienced a start-up failure, or if a port shuts down due to the start-up inrush
current.
D[5]
OCP
0
Interrupt signal for over-current (OC) conditions. If this bit is set to 1, at least one of
the ports has met the ILIMT current limit timer or the ICUT OC timeout condition.
D[4]
CLSC
0
Interrupt signal for classification completion. This bit is set to 1 if at least one port
has completed its classification process.
D[3]
DETC
0
Interrupt signal for detection completion. This bit is set to 1 if at least one port has
completed its detection process.
D[2]
DCDIS
0
Interrupt signal for a disconnected DC load. This bit is set to 1 if at least one port
has had its DC load disconnected (load < 7.5mA).
D[1]
PGC
0
Interrupt signal for power good (PG) status change. This bit is set to 1 if at least one
port has a new PG status.
D[0]
PEC
0
Interrupt signal for power enable status change. This bit is set to 1 if at least one
port has changed its enable or disable status.
Read the register address with an R/C byte, or write 1 to CLRAIN to reset the corresponding bit. The
IN1 and INT2 pins go low to report if an interrupt bit is set to 1. These pins do not go low if the interrupt
signal is masked.
INTERRUPT_MASK (01h)
Read/write
Bits
Bit Name
Default Value
D[7]
VINF_M
1
Masks the interrupt signal for VIN power failures. Set this bit to 0 to disable the
interrupt function.
D[6]
STF_M
A
Masks the interrupt signal for start-up failures. Set this bit to 0 to disable the
interrupt function.
D[5]
OCP_M
A
Masks the interrupt signal for over-current (OC) conditions. Set this bit to 0 to
disable the interrupt function.
D[4]
CLSC_M
0
Masks the interrupt signal for classification completion. Set this bit to 0 to disable the
interrupt function.
D[3]
DETC_M
0
Masks the interrupt signal for detection completion. Set this bit to 0 to disable the
interrupt function.
D[2]
DCDIS_M
A
Masks the interrupt signal for DC load disconnection. Set this bit to 0 to disable the
interrupt function.
D[1]
PGC_M
0
Masks the interrupt signal for power good (PG) status change interrupt. Set this bit
to 0 to disable the interrupt function.
MP3924 Rev. 1.0
7/16/2021
Description
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
D[0]
PEC_M
0
Masks the interrupt signal for power enable status change interrupt. Set this bit to 0
to disable the interrupt function.
Write 1 to enable the interrupt function; write 0 to disable the interrupt function. “A” is “1” if the AUTO
pin is set high during start-up or a reset. “A” is “0” if the AUTO pin is set low.
These bits only disable the response from the INT1 and INT2 pins. The corresponding interrupt bit
always changes. The device cannot mask certain interruptions during start-up or a reset event,
including VIN under-voltage lockout (UVLO) and VCC UVLO.
INTERRUPT PRIORITY (02h)
Read/write
Bits
Bit Name
Default Value
Description
D[7]
VINF_P
1
Selects if the INT2 pin responds to a VIN power failure interrupt signal.
D[6]
STF_P
0
Selects if the INT2 pin responds to a start-up failure interrupt signal.
D[5]
OCP_P
1
Selects if the INT2 pin responds to an over-current (OC) interrupt signal.
D[4]
CLSC_P
0
Selects if the INT2 pin responds to a classification completion interrupt signal.
D[3]
DETC_P
0
Selects if the INT2 pin responds to a detection completion interrupt signal.
D[2]
DCDIS_P
0
Selects if the INT2 pin responds to a DC load disconnect interrupt signal.
D[1]
PGC_P
0
Selects if the INT2 pin responds to a power good (PG) status change interrupt
signal.
D[0]
PEC_P
0
Selects if the INT2 pin responds to a power enable status change interrupt signal.
If a bit is set to 1, the INT2 pin pulls low in response to the corresponding interrupt signal. The INT1 pin
responds to all interrupt sources, as long as they are not masked. INT2 only responds to the interrupt
sources that are not masked.
MP3924 Rev. 1.0
7/16/2021
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
CONFIGURATION AND CONTROL REGISTERS
OPERATION_MODE_SETTING (03h)
Read/write
Bits
Bit Name
Default Value
D[7:6]
MODE4
AA
D[5:4]
MODE3
AA
D[3:2]
MODE2
AA
D[1:0]
MODE1
AA
Description
Sets the operation mode for ports 1 through 4. “A” is 1 if the AUTO pin is set high
during start-up or a reset. “A” is 0 if the AUTO pin is set low. The status is latched
only during start-up or a reset. This can be changed via the I2C.
00: Shutdown mode. The port is off, and there is no detection or classification
process
01: Manual mode. There is no automatic state change
10: Semi-automatic mode. The detection and classification processes are
automated, but the port does not turn on automatically
11: Automatic mode. Start-up, as well as detection and classification processes,
are automated
MIDSPAN_SETTING (04h)
Read/write
Bits
Bit Name
Default Value
D[7:4]
RESERVED
-
D[3]
MID4
M
D[2]
MID3
M
D[1]
MID2
M
D[0]
MID1
M
Description
Reserved.
Sets the midspan mode for ports 1 through 4. “M” is “1” if the MID pin is high
during start-up or a reset. “M” is “0” if MID pin is low. These changes can be
configured by writing to the I2C. Set this bit to 1 to enable midspan mode for the
corresponding port.
PORT_ENABLE (05h)
Read/write
Bits
Bit Name
Default Value
Description
D[7:5]
RESERVED
-
Reserved.
D[4]
ENAL
1
Enables the MP3924. If this bit is set to 1, all internal IC circuits are enabled.
Each port is enabled if the ENAL and ENx bits are set to 1. If ENAL is disabled,
the I2C continues to operate, but the ports are shut down.
D[3]
EN4
1
D[2]
EN3
1
D[1]
EN2
1
D[0]
EN1
1
Enables ports 1 through 4. These bits can disable the corresponding port, which
includes detection and classification processes, resets the port and status
registers, and shuts down the port. If a port is already turned off and these bits
are set to 0, then there is no change.
1: Enabled
0: Disabled
DET/CLS_ENABLE (06h)
Read/write
Bits
Bit Name
Default Value
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
CLSEN4
CLSEN3
CLSEN2
CLSEN1
DETEN4
DETEN3
DETEN2
DETEN1
A
A
A
A
A
A
A
A
MP3924 Rev. 1.0
7/16/2021
Description
Enables the classification process for the corresponding port. Set these bits to 1 to
enable classification.
Enables the detection process for the corresponding port. Set these bits to 1 to
enable detection.
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
“A” is “1” if the AUTO pin is set high during start-up or a reset. “A” is “0” if the AUTO pin is set low. In
automatic and semi-automatic mode, the detection and classification processes are enabled when the
bit is set to 1. In manual made, set the bit to 1 for one-time detection or classification. Then the bit is
reset to 0.
DISCONNECT_ENABLE (07h)
Read/write
Bits
Bit Name
Default Value
Description
D[7:4]
RESERVED
-
Reserved.
D[3]
D[2]
D[1]
D[0]
DISEN4
DISEN3
DISEN2
DISEN1
A
A
A
A
Enables DC load disconnection for ports 1 through 4. “A” is 1 if the AUTO pin is
set high during start-up or a reset. “A” is 0 if the AUTO pin is set low. If these bits
are set to 1, the DC load disconnection function is enabled on the corresponding
port.
FAULT_TIMER (08h)
Read/write
Bits
Bit Name
Default Value
Description
Sets the total power overload timer after start-up.
D[7:6]
TPMAX
10
00: 15ms
01: 30ms
10: 60ms
11: 120ms
Sets the start-up inrush current timer for all ports.
D[5:4]
TINRUSH
10
00: 15ms
01: 30ms
10: 60ms
11: 120ms
Sets the current limit trigger timer after start-up for all ports.
D[3:2]
TILIM
11
00: 7.5ms
01: 15ms
10: 30ms
11: 60ms
Set the over-current (OC) timer after start-up for all ports.
D[1:0]
TCUT
10
00: 15ms
01: 30ms
10: 60ms
11: 120ms
The timer begins counting up after a load triggers the threshold. If the current drops below the
threshold, the timer begins counting down at 1/16 of the rising rate. If it times out, the port shuts down.
The port cannot be redetected once the timer counts down to 0.
FOLDBACK_ILIM (0Bh)
Read/write
Bits
Bit Name
Default Value
D[7:1]
RESERVED
-
D[0]
FBLIMT
1
Description
Reserved.
Sets the foldback over-current (OC) threshold when the OUTx pin exceeds 46V.
MP3924 Rev. 1.0
7/16/2021
0: The foldback current limit is 22mV (88mA if RSENSE = 0.25Ω).
1: The foldback current limit is 40mV (160mA RSENSE = 0.25Ω).
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35
MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
2-EVENT_AND_CLASS_5_ENABLE (0Ch)
Read/write
Bits
Bit Name
Default Value
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
CLS5_EN4
CLS5_EN3
CLS5_EN2
CLS5_EN1
2EVNTEN4
2EVNTEN3
2EVNTEN2
2EVNTEN1
C
C
C
C
A
A
A
A
Description
Enables Class 5 classification for all ports. If these bits are set to 1, Class 5
classification is enabled on the corresponding port, and the default current limit
can support up to 40W of power.
Enables two-event classification for all ports. If these bits are set to 1, two-event
classification is enabled when the first classification result on the port is Class 4 or
Class 5.
“A” is “1” if the AUTO pin is set high during start-up or a reset. “A” is “0” if the AUTO pin is set low. “C” is
“1” if the CLS5 pin is set high during start-up or a reset. “C” is “0” if the CLS5 pin is set low. The CLS5
pin has a high power level under the IEEE802.3 at classification, but it is not a standard class level that
is compatible with IEEE802.3.
PMAX_SHUTDOWN_PORT_PRIORITY (0Dh)
Read/write
Bits
Bit Name
Default Value
D[7:6]
PRTY4
11
D[5:4]
PRTY3
10
D[3:2]
PRTY2
01
D[1:0]
PRTY1
00
Description
Sets the shutdown priority for all ports after the PMAX limit is triggered. If the value
is the same on several ports, priority is arranged based on the default priority. For
example, if both port 1 and port 2 are 00, then port 2 shuts down first.
11: The lowest priority port, which shuts down first if the PMAX limit is triggered
10: The third level priority port if the PMAX limit is triggered
01: The second level priority port if the PMAX limit is triggered
00: The highest priority port, which shuts down last if the PMAX limit is triggered
INTERRUPT_ENABLE_CONTROL (0Eh)
Read/write
Bits
Bit Name
Default Value
Description
D[7:3]
RESERVED
-
Reserved.
D[2]
CLRPIN
0
Controls the reset function for the INT1 and INT2 pins. If this bit is set to 1,
resetting the INT1 and INT2 pins does not affect the registers. This bit is
automatically set to 0 after the INT1 and INT2 pins are reset.
D[1]
CLRAINT
0
Controls the reset function for the interrupt source. If this bit is set to 1, all
registers and the INT1 and INT2 bit are reset. This bit is automatically set to 0
after the INT1 and INT2 pins are reset.
D[0]
INTEN
1
Enables the interrupt function. This bit does not affect the event register. If this bit
is set to 1, the interrupt function is enabled.
GENERAL_ENABLE_CONTROL (0Fh)
Read/write
Bits
Bit Name
Default Value
Description
D[7:3]
RESERVED
-
Reserved.
D[2]
PMAXEN
A
Enables the maximum total load power limit. If this bit = 1, automatic shutdown is
triggered when the PMAX pin reaches its maximum input power setting.
D[1]
ADCEN
1
Enables the ADC. If this bit = 1, the ADC is enabled.
D[0]
WDEN
0
Enables the I2C watchdog. If this bit is set to 0, the watchdog is disabled.
“A” is “1” if the AUTO pin is set high during start-up or a reset. “A” is “0” if the AUTO pin is set low.
MP3924 Rev. 1.0
7/16/2021
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36
MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
MANUAL MODE AND LEGACY DETECTION CONTROL REGISTERS
DET/CLS_TRIGGER (10h)
Read/write
Bits
Bit Name
Default Value
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
RCLS4
RCLS3
RCLS2
RCLS1
RDET4
RDET3
RDET2
RDET1
0
0
0
0
0
0
0
0
Description
Re-enables the classification function on all ports. If these bits are set to 1, a onetime classification event is enabled on the corresponding port. These bits are reset
after classification is complete.
Re-enables the detection function on all ports. If these bits are set to 1, a one-time
detection event is enabled on the corresponding port. These bits are reset after
detection is complete.
In manual mode, one-time detection or classification occurs after the corresponding bit is set. In semiautomatic or automatic mode, detection and classification are controlled by the DETENx and CLSENx
bits. These processes are repeated once they are enabled.
POWER_ON/OFF_TRIGGER (11h)
Read/write
Bits
Bit Name
Default Value
D[7]
D[6]
D[5]
D[4]
POFF4
POFF3
POFF2
POFF1
0
0
0
0
D[3]
PON4
0
D[2]
PON3
0
D[1]
PON2
0
Description
Triggers a shutdown on the corresponding port. If these bits are set to 1, the port
powers off. The bit automatically resets afterward.
Triggers start-up on the corresponding port. If these bits are set to 1, the
corresponding port powers on. These bits are reset after start-up is complete. The
device performs a detection cycle first if the DETENx and PONx bits are set
simultaneously.
The PONx bits are operational in manual mode. If the port is powered on or in
shutdown mode, the port does not respond to these bits.
The PONx bits are operational in semi-automatic mode. The port responds to
these bits if the detection and classification results are valid.
The PONx bits are only functional during legacy detection if the device is set to
automatic mode.
D[0]
PON1
0
For all modes, the PONx bits may be cleared by DET/CLS/LEGACY_DET failures,
start-up failures, or if the PON signal lasts for 400ms when the port is operational.
LEGACY_ENABLE (12h)
Read/write
Bits
Bit Name
Default Value
D[7:6]
LEGEN4
00
Enables legacy detection mode for all ports.
D[5:4]
D[3:2]
LEGEN3
LEGEN2
00
00
D[1:0]
LEGEN1
00
00: Legacy detection is disabled
01: Legacy detection is enabled while standard detection is disabled
10: Legacy detection is enabled after standard detection is complete
11: Reserved
MP3924 Rev. 1.0
7/16/2021
Description
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
CURRENT LIMIT CONFIGURATION REGISTER
ICUT1_THRESHOLD (13h)
Read/write
Bits
Bit Name
Default Value
D[7:3]
RESERVED
-
Description
Reserved.
Sets port 1’s over-current (OC) threshold. The default value is 000. In automatic
mode, the bits are set to 000 for Class 0~3 results, 100 for Class 4 results, and
101 for Class 5 results. In semi-automatic mode or manual mode, the bits do not
change unless changes are made via the I2C.
D[2:0]
ICUT1
000
000 = 93.75mV (375mA with RSENSE = 0.25Ω)
001 = 27.5mV (110mA with RSENSE = 0.25Ω)
010 = 47mV (188mA with RSENSE = 0.25Ω)
011 = 93.75mV (375mA with RSENSE = 0.25Ω)
100 = 162.5mV (650mA with RSENSE = 0.25Ω)
101 = 230mV (920mA with RSENSE = 0.25Ω)
110 = 125mV (500mA with RSENSE = 0.25Ω)
111 = 156.25mV (625mA with RSENSE = 0.25Ω)
ICUT2_THRESHOLD (14h)
Read/write
Bits
Bit Name
Default Value
D[7:3]
RESERVED
-
Description
Reserved.
Sets port 2’s over-current (OC) threshold. The default value is 000. In automatic
mode, the bits are set to 000 for Class 0~3 results, 100 for Class 4 results, and
101 for Class 5 results. In semi-automatic mode or manual mode, the bits do not
change unless changes are made via the I2C.
D[2:0]
ICUT2
000
000 = 93.75mV (375mA with RSENSE = 0.25Ω)
001 = 27.5mV (110mA with RSENSE = 0.25Ω)
010 = 47mV (188mA with RSENSE = 0.25Ω)
011 = 93.75mV (375mA with RSENSE = 0.25Ω)
100 = 162.5mV (650mA with RSENSE = 0.25Ω)
101 = 230mV (920mA with RSENSE = 0.25Ω)
110 = 125mV (500mA with RSENSE = 0.25Ω)
111 = 156.25mV (625mA with RSENSE = 0.25Ω)
ICUT3_THRESHOLD (15h)
Read/write
Bits
Bit Name
Default Value
D[7:3]
RESERVED
-
Description
Reserved.
Sets port 3’s over-current (OC) threshold. The default value is 000. In automatic
mode, the bits are set to 000 for Class 0~3 results, 100 for Class 4 results, and
101 for Class 5 results. In semi-automatic mode or manual mode, the bits do not
change unless changes are made via the I2C.
D[2:0]
ICUT3
MP3924 Rev. 1.0
7/16/2021
000
000 = 93.75mV (375mA with RSENSE = 0.25Ω)
001 = 27.5mV (110mA with RSENSE = 0.25Ω)
010 = 47mV (188mA with RSENSE = 0.25Ω)
011 = 93.75mV (375mA with RSENSE = 0.25Ω)
100 = 162.5mV (650mA with RSENSE = 0.25Ω)
101 = 230mV (920mA with RSENSE = 0.25Ω)
110 = 125mV (500mA with RSENSE = 0.25Ω)
111 = 156.25mV (625mA with RSENSE = 0.25Ω)
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
ICUT4_THRESHOLD (16h)
Read/write
Bits
Bit Name
Default Value
D[7:3]
RESERVED
-
Description
Reserved.
Sets port 4’s over-current (OC) threshold. The default value is 000. In automatic
mode, the bits are set to 000 for Class 0~3 results, 100 for Class 4 results, and
101 for Class 5 results. In semi-automatic mode or manual mode, the bits do not
change unless changes are made via the I2C.
D[2:0]
ICUT4
000
000 = 93.75mV (375mA with RSENSE = 0.25Ω)
001 = 27.5mV (110mA with RSENSE = 0.25Ω)
010 = 47mV (188mA with RSENSE = 0.25Ω)
011 = 93.75mV (375mA with RSENSE = 0.25Ω)
100 = 162.5mV (650mA with RSENSE = 0.25Ω)
101 = 230mV (920mA with RSENSE = 0.25Ω)
110 = 125mV (500mA with RSENSE = 0.25Ω)
111 = 156.25mV (625mA with RSENSE = 0.25Ω)
ILIM1_THRESHOLD (17h)
Read/write
Bits
Bit Name
Default Value
D[7:1]
RESERVED
-
Reserved.
0
Sets port 1’s over-current (OC) limit. The default value is 0. In automatic mode, the
bits are set to 0 for Class 0~3, and set to 1 for Class 4 or Class 5 results. In semiautomatic mode and manual mode, the bits do not change unless changes are
made via the I2C.
D[0]
ILIM1
Description
0: 106.25mV (425mA if RSENSE = 0.25Ω)
1: 212.5mV. The current limit is 265mV under Class 5 conditions
ILIM2_THRESHOLD (18h)
Read/write
Bits
Bit Name
Default Value
D[7:1]
RESERVED
-
Reserved.
0
Sets port 2’s over-current (OC) limit. The default value is 0. In automatic mode, the
bits are set to 0 for Class 0~3, and set to 1 for Class 4 or Class 5 results. In semiautomatic mode and manual mode, the bits do not change unless changes are
made via the I2C.
D[0]
ILIM2
Description
0: 106.25mV (425mA if RSENSE = 0.25Ω)
1: 212.5mV. The current limit is 265mV under Class 5 conditions
ILIM3_THRESHOLD (19h)
Read/write
Bits
Bit Name
Default Value
D[7:1]
RESERVED
-
Reserved.
0
Sets port 3’s over-current (OC) limit. The default value is 0. In automatic mode, the
bits are set to 0 for Class 0~3, and set to 1 for Class 4 or Class 5 results. In semiautomatic mode and manual mode, the bits do not change unless changes are
made via the I2C.
D[0]
ILIM3
Description
0: 106.25mV (425mA if RSENSE = 0.25Ω)
1: 212.5mV. The current limit is 265mV under Class 5 conditions
MP3924 Rev. 1.0
7/16/2021
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MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
ILIM4_THRESHOLD (1Ah)
Read/write
Bits
Bit Name
Default Value
D[7:1]
RESERVED
-
Reserved.
0
Sets port 4’s over-current (OC) limit. The default value is 0. In automatic mode, the
bits are set to 0 for Class 0~3, and set to 1 for Class 4 or Class 5 results. In semiautomatic mode and manual mode, the bits do not change unless changes are
made via the I2C.
D[0]
ILIM4
Description
0: 106.25mV (425mA if RSENSE = 0.25Ω)
1: 212.5mV. The current limit is 265mV under Class 5 conditions
MP3924 Rev. 1.0
7/16/2021
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40
MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
STATUS REGISTERS
POWER_SOURCE_STATUS1 (20h and 21h)
(20h) Read-only
(21h) Read and clear
Bits
Bit Name
Default Value
Description
D[7]
D[6]
D[5]
D[4]
FETF4
FETF3
FETF2
FETF1
0
0
0
0
Indicates whether an external power MOSFET failure has occurred. This bit is set
to 1 if the external MOSFET on the corresponding port has failed. If this occurs, the
current limit cannot be reached, or the OUTx pin is high after start-up.
D[3]
VCCUV
1
Indicates whether a VCC under-voltage condition has occurred. This bit is set to 1
if VCC has recovered from a shutdown or reset condition.
D[2]
OTP
0
Indicates whether an over-temperature (OT) condition has occurred. This bit is set
to 1 if the junction temperature exceeds 150°C. For more details, see the OverTemperature Protection (OTP) section on page 28.
D[1]
VINOV
0
Indicates whether a VIN over-voltage (OV) condition has occurred. This bit is set to
1 if VIN exceeds 65V.
D[0]
VINUV
1
Indicates whether a VIN under-voltage (UV) condition has occurred. This bit is set
to 1 if VIN drops below 29.5V.
Read and Clear (0x21h) means that the bit is reset after a read operation. If read on 0x20h, the bits are not
cleared.
POWER_SOURCE_STATUS2 (22h and 23h)
(22h) Read-only
(23h) Read and clear
Bits
Bit Name
Default Value
Description
D[7:2]
RESERVED
-
Reserved.
D[1]
VINOK
0
Indicates whether the VIN source power is working normally. This bit is set to 1 if
VIN exceeds 40V.
D[0]
OVPMAX
0
Indicates whether a power overload condition has occurred. This bit is set to 1 if
the total power load on all ports exceeds the PMAX threshold set by the PMAX pin.
DET/CLS_COMPLETE_STATUS (24h and 25h)
(24h) Read-only
(25h) Read and clear
Bits
Bit Name
Default Value
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
CLSC4
CLSC3
CLSC2
CLSC1
DETC4
DETC3
DETC2
DETC1
0
0
0
0
0
0
0
0
MP3924 Rev. 1.0
7/16/2021
Description
Indicates whether a port has completed its classification process. These bits are
set to 1 if classification has completed on the corresponding bit.
Indicates whether a port has completed its detection process. These bits are set to
1 if detection has completed on the corresponding bit.
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© 2021 MPS. All Rights Reserved.
41
MP3924 – QUAD-PORT IEEE 802.3AF/AT PSE CONTROLLER
DET/CLS_RESULT1 (26h)
Read-only
Bits
Bit Name
Default Value
Description
Returns the classification result for port 1.
D[7:4]
CLSR1
0000
0000: Classification is not done
0001: Class 1
0010: Class 2
0011: Class 3
0100: Class 4
0101: Class 5
0110: Class 0
0111: Over-current (OC) condition
1000: The first and secondary class results do not match
If Class 5 is enabled, any current that exceeds Class 4’s upper limit is considered a
Class 5 result. An OC condition triggers a current limit. If Class 5 is disabled, any
current exceeding Class 4’s upper limit is considered an OC condition.
D[3]
2EVNTC1
0
Indicates whether two-event classification has been completed on port 1. This bit is
set to 1 if two-event classification has been completed. This bit is only set once
Class 4 and Class 5 are successfully detected.
Indicates port 1’s detection result.
D[2:0]
DETR1
000
000: Detection has not completed (default after a power-on reset)
001: The port is shorted (VIN - OUT < 1.5V)
010: CDET too high (exceeds 5µF)
011: RDET is too low (below 19kΩ)
100: Detection is valid (19kΩ < RDET < 26.5kΩ)
101: RDET is too high (exceeds 26.5kΩ)
110: The port is open (
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